JP2001024478A - Digital filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continuously shift frequency characteristic in a frequency axis direction and maintaining the shape of original frequency characteristic also at the time of shifting by executing arithmetic processing for outputting only an optional frequency band in synchronization with a second clock pulse with respect to rate conversion data and converting the arithmetic result to data synchronizing with a first clock pulse to output. SOLUTION: A VFO 4 being a variable frequency oscillator generates a clock pulse 9 of a frequency fv to be fixed by a frequency control signal 7d inputted from a signal line 7. In addition, the sampling clock 6s of a frequency fs is inputted. Digital data sampled by synchronizing with the clock 6s of the line 6 is inputted to a signal line 5 and a sampling rate is converted from the frequency fs to fv by a first sampling rate converter 1. After being processed by the digital filter 2 of a fixed coefficient, the data is outputted to a signal line 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital filter circuit capable of arbitrarily shifting a frequency characteristic of an original signal by changing a sampling rate.

[0002]

2. Description of the Related Art In a conventional digital signal processing circuit, in particular, in a digital filter circuit, a method of shifting a frequency characteristic has been realized mainly by switching an arithmetic coefficient which governs a frequency characteristic of a filter.

Digital filters are generally classified into an IIR filter having an infinite impulse response characteristic by having a path for returning processed data, and an FIR filter having no finite impulse response characteristic without a feedback path. However, in any case, it is composed of a holding circuit, an adding circuit, and a multiplying circuit. As a typical example of such a digital filter, an example of a signal flow of a second-order IIR filter called Biquad is shown in FIG.
6 is shown.

[0004] The characteristics of this type of filter are determined by a calculation procedure and a multiplication factor represented by a signal flow. Therefore, changing the characteristics of the filter requires changing the signal flow or changing the coefficient. However, it is possible to change the signal flow only in a highly versatile system that performs signal processing by software, and it is common for dedicated systems to use dedicated hardware with a fixed signal flow. There is no means for changing the characteristics of the filter other than changing the coefficients. Also, if the calculation procedure is changed, the basic characteristics of the filter will change greatly, and it is not suitable for the purpose of continuously shifting the frequency characteristics.

On the other hand, when the coefficient is switched,
In order to reduce the amount of change in the frequency characteristic to such a degree that it can be regarded as continuous in use, many coefficients are required, and the scale of a ROM or the like for storing the coefficients is also increased.

[0006] For example, Japanese Patent Laid-Open Publication No. 60-24131
In the digital filter disclosed in Japanese Patent Application Laid-Open No. 4 (1994) -208, hardware in which the number of stages of a delay circuit can be selected, and EPR in which coefficients corresponding to a plurality of filter characteristics can be set
By mounting the OM, filters having different characteristics are realized by one piece of hardware. However, in the case of this example, it is necessary to selectively read out from the EPROM a coefficient group required for each of a plurality of desired characteristics, so that an increase in the scale of the EPROM cannot be avoided.

[0007] In contrast to this method, for example,
As disclosed in JP-A-6-164319, a method for interpolating coefficients has been proposed. This method does not have all coefficient sets corresponding to all the frequency characteristics to be set, but has only a set of coefficients selected at appropriate intervals in a table. By performing interpolation, a continuous frequency characteristic shift is realized.

[0008]

However, in recent years,
As digital LSIs become faster, more integrated, and lower in price, the application range of digital filters expands. Especially, taking advantage of digital circuits that are not affected by temperature, voltage, mechanical shock, etc., conventional analog circuits can be used. Digitization is also progressing in the fields where it was used.

As an application field of such a digital filter, for example, IF (intermediate frequency) or A
There are an F (low frequency) filter and a low-pass filter for a voice band in a telephone. In the former case, a steep cutoff characteristic is required in order to remove interference of other stations in the nearby frequency, and in the latter case, the whole system such as a telephone and a switch is digitally processed to sample at 8 kHz. Therefore, it is required that the component of 4 kHz or more, which is aliasing noise, be sufficiently attenuated, and that the gain of the pass band be flat.

In any case, it is preferable that the cut-off characteristics be extremely flat below the cut-off and extremely sharp above the cut-off. A filter having such characteristics is realized by using a high-order digital filter and appropriately selecting zeros and poles of the transfer function.

However, in such a situation, the prior art has the following problems. That is, in the case where the cutoff frequency is finely adjusted with respect to the filter having the ideal characteristics, it is difficult to maintain good characteristics with the conventional technology. The reason is that, as described above, in a high-order filter having both passband flatness and steep cutoff characteristics, the influence of the zero point and the pole on the frequency characteristics is extremely high.

For example, Japanese Patent Laid-Open Publication No.
In the method disclosed in Japanese Patent No. 64319, an error occurs at the zero point and the pole due to the interpolation, so that there is a problem that the characteristics near the cutoff frequency change.

In order to avoid this problem, it is necessary to shorten the section to be interpolated. However, this means that the coefficient table is enlarged at the same time, and this leads to an increase in the manufacturing cost especially in the case of LSI. This is not an effective means. Even if it is permitted to have all necessary coefficients in the table without performing interpolation, since the coefficients themselves are digital data having a finite word length, the LSB is compared with the theoretical ideal value. It can have a considerable error. This error occurs when the ideal value is rounded to the word length of the actual circuit.

Therefore, in the case of a system having a plurality of sets of coefficients, even if each coefficient is selected so as to have ideal characteristics, the degree of the rounding error differs for each coefficient. Can not be. As an example, an eighth-order I with a sampling rate of 32 kHz
14 and 15 show frequency characteristics of the IR filter when there is no coefficient error and when there is a coefficient error.
14 shows a case where there is no error, and FIG. 15 shows a case where each coefficient includes an error corresponding to an 8-bit LSB. From this example, it can be seen that an abnormal peak exists near the cutoff in the characteristic having the error.

The present invention has been made in view of such a problem, and an object of the present invention is to enable the frequency characteristic to be continuously shifted in the frequency axis direction, and to maintain the original frequency even when shifted. An object of the present invention is to provide a digital filter circuit in which the shape of the characteristic is maintained.

[0016]

Means for Solving the Problems In order to solve the above problems, the present invention has the following constitution. The gist of the invention according to claim 1 is a digital filter circuit capable of arbitrarily shifting a frequency characteristic, wherein a receiving unit to which a first clock pulse is input and a cycle can be arbitrarily set. Variable frequency clock generating means for generating a second clock pulse, and converting digital data input in synchronization with the first clock pulse into rate conversion data in synchronization with the second clock pulse, and outputting the converted data. A first rate conversion means, a digital filter for performing an arithmetic processing for outputting only an arbitrary frequency band on the rate converted data in synchronization with the second clock pulse, and outputting an arithmetic result; Second rate conversion means for converting the calculation result synchronized with the second clock pulse into data synchronized with the first clock pulse and outputting the data. It consists in the digital filter circuit according to claim Rukoto. The gist of the invention according to claim 2 resides in the digital filter circuit according to claim 1, wherein the variable frequency clock generating means is a voltage controlled oscillator. Claim 3
The gist of the described invention is that the variable frequency clock generating means is a counter circuit to which a clock pulse having a frequency sufficiently higher than the second clock pulse is inputted, and that the clock circuit is configured to count an arbitrarily set number of times. The digital filter circuit according to claim 1, wherein the digital filter circuit is a variable frequency dividing circuit that outputs a pulse. The gist of the invention according to claim 4 is that the first rate conversion means synchronizes the first clock pulse with the second clock pulse and a clock output from the synchronization means. Delay means for delaying a pulse by the cycle of the second clock pulse, wherein the digital signal is inputted only during a time difference between the clock pulse output from the synchronization means and the clock pulse output from the delay means. The digital filter circuit according to any one of claims 1 to 3, wherein data is passed, and the input digital data is masked during other periods. The gist of the present invention is that the second rate conversion means synchronizes the first clock pulse with the second clock pulse and a clock output from the synchronization means. The digital filter circuit according to any one of claims 1 to 4, wherein the calculation result input from the digital filter is latched and output by a pulse. The gist of the invention according to claim 6 resides in the digital filter circuit according to any one of claims 1 to 5, wherein the second clock pulse has a higher frequency than the first clock pulse. . The gist of the present invention resides in an IC including the digital filter circuit according to any one of claims 1 to 6. The gist of the present invention resides in an electronic circuit board including the digital filter circuit according to any one of claims 1 to 6.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram illustrating an example of an embodiment of the present invention. As shown in FIG. 1, in the digital filter circuit according to the present embodiment, VFO4 is a variable frequency oscillator, and has a frequency f determined by a frequency control signal 7d input from the signal line 7.
v clock pulse 9 is generated. Further, a sampling clock 6 s having a frequency fs is input to the signal line 6. On the other hand, digital data sampled in synchronization with the sampling clock 6 s of the signal line 6 is input to the signal line 5, the sampling rate is converted from fs to fv by the first sampling rate converter 1, and a digital filter having a fixed coefficient After the processing at 2, the sampling rate is returned from fv to fs by the second sampling rate converter 3 and output to the signal line 8.

The fixed coefficient digital filter 2 may be any circuit as long as the digital filter has a sampling rate of fv.

In general, in a filter circuit such as a digital filter circuit that performs processing on sampled data, a time for data to be processed is defined based on a sampling rate. Therefore, all parameters related to time, such as a time constant and a frequency, have no meaning unless the sampling rate is determined. This means that even if the circuits perform the same processing, the characteristics of the circuits change if the sampling rates of the data supplied to the circuits are different.

The present invention utilizes this feature to convert a data sequence sampled at a constant sampling rate fs into a data sequence with a variable sampling rate fv, and perform filtering in a system with a sampling rate fv. , Arbitrarily shifts the frequency characteristics of the filter in the frequency direction.

FIG. 2 shows a first sampling rate converter 1
FIG. 3 is a timing chart showing an example of a specific circuit diagram of FIG. 2 and 3, the sampling clock 6s having the frequency fs has a frequency fv which is sufficiently higher than the frequency fs.
Of the clock pulse 9 (f) by the flip-flop and the logic circuit 21 which operate in synchronization with the clock pulse 9 of FIG.
In addition to receiving a delay in synchronization with v), a one-shot pulse 22 generated once every time the rising edge of the sampling clock 6s (fs) is input to the mask circuit 23. The mask circuit 23 is a circuit that allows the input data 5d to pass through the rate conversion output 24 as it is only during a period in which the one-shot pulse 22 is active, and outputs zero data otherwise. The AND logic is applied to each bit of the input data 5d. It is realized by taking.

Thus, the sampling clock 6s (f
s) is synchronized with the clock pulse 9 (f
v), and even if the clock pulse 9 (fv) is asynchronous with respect to the sampling clock 6 s (fs), the data is output to the rate conversion output 24 avoiding the transition point of the input data 5 d. Therefore, data always changes in synchronization with the clock pulse 9 (fv).

FIG. 4 shows the second sampling rate converter 3.
FIG. 5 is an example of a specific circuit diagram of FIG. 4 and 5, the sampling clock 6s having the frequency fs is delayed by the flip-flop and the logic circuit 32 synchronized with the clock pulse 9 having the frequency fv in synchronization with the clock pulse 9 (fv), and the sampling clock 6s ( A one-shot pulse 33 generated once at every rising edge of the clock fs) is input to the data holding circuit 34.

The data holding circuit 34 operates to update the value only when the one-shot pulse 33 is active. The input signal (the output 31 of the digital filter 2) synchronized with the clock pulse 9 (fv) is a sampling clock. The signal is output at a timing delayed from the change point of 6 s (fs) and synchronized with the clock pulse 9 (fv).
In this case, the output timing is the sampling clock 6 s
(Fs) Although not synchronized, the sampling clock 6
Since it can be considered that the signal of s (fs) synchronization is delayed,
Except for the point that an external circuit that handles this signal in synchronization with the sampling clock 6s (fs) acts to increase the margin of the hold time, the sampling clock 6s
(Fs) There is no particular problem in handling as a synchronous signal.

FIG. 6 is a circuit diagram of the VFO (variable frequency oscillator) 4. In this embodiment, VFO4 is VCO
(Voltage-controlled oscillator) realizes the function of a variable frequency oscillator. In FIG. 6, the current supplied from the constant current circuit 61 is divided into a path flowing to the GND through the MOSFET 62 and a path supplied to the oscillation circuit 63. When the frequency control signal 7d is applied to the gate of the MOSFET 62, the current flowing to GND is controlled, and accordingly, the current supplied to the oscillation circuit 63 is determined. Then, the current injected into the capacitor 64 is also determined, and the time until the voltage of the capacitor 64 reaches the threshold voltage of the inverter circuit 65 is also determined. Thus, the oscillation frequency is controlled by the voltage of the frequency control signal 7d.

FIG. 7 shows another embodiment of the VFO 4 shown in FIG.
FIG. In this embodiment, a variable frequency division ratio counter is used, and the frequency control signal 74 is given as digital data unlike the case of FIG. Here, for the sake of explanation, it is assumed that the oscillation output frequency is 1024 kHz.
And an example of a circuit that can be set in 1% steps. The counter circuit 71 is a circuit that counts and outputs the number of pulses of the 102.4 MHz clock pulse 73, and the coincidence determination circuit 72 is a circuit that compares the value of the counter circuit 71 with the value given as the frequency control signal 74. is there. When the match determination circuit 72 determines a match, the counter circuit 71 is reset. Therefore, since the counter circuit 71 counts only up to the value given as the frequency control signal 74, it operates as a variable frequency dividing circuit whose frequency dividing ratio is set by the frequency control signal 74. Therefore, a clock pulse 73 of an arbitrary frequency appears on the output.

Since the digital filter circuit according to the embodiment is configured as described above, the following effects can be obtained. Based on the case where fs = 32 kHz and fv = 1024 kHz, the case where fv is changed by ± 10% and the case where fv is changed by ± 2%
FIGS. 9 to 13 show the frequency characteristics of the present invention when changed by 0%. At this time, the frequency (fv) of the clock pulse 9 and the conversion ratio f of the sampling rate
FIG. 8 shows the values of v / fs. However, the digital filter 2 having a fixed coefficient used as an example here is an eighth-order IIR filter in which four-stage IIR filters represented by the signal flow shown in FIG. 16 are cascaded.

As is clear from FIGS. 9 to 13, the cutoff is shifted by changing fv, but the external shape of the frequency characteristic does not change.

As described above, according to the present invention, there is provided a digital signal processing circuit capable of continuously shifting the frequency characteristic in the frequency axis direction and maintaining the original shape of the frequency characteristic when the frequency characteristic is shifted. It can be realized only by adding a simple circuit.

Note that, in the present embodiment, the present invention is not limited to this, and can be applied to a mode suitable for applying the present invention.

Further, the number, position, shape, etc. of the above-mentioned constituent members are not limited to the above-mentioned embodiment, but can be set to a suitable number, position, shape, etc. for carrying out the present invention.

In each of the drawings, the same components are denoted by the same reference numerals.

[0033]

Since the present invention is configured as described above, it is possible to shift the frequency characteristic continuously in the frequency axis direction, and to maintain the original frequency characteristic shape even when shifting. There is an effect that a filter circuit is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an embodiment of the present invention.

FIG. 2 is an electronic circuit diagram of the first sampling rate converter 1 shown in FIG.

FIG. 3 is a timing chart of the first sampling rate converter 1 shown in FIG.

FIG. 4 is an electronic circuit diagram of the second sampling rate converter 3 shown in FIG.

FIG. 5 is a timing chart of the second sampling rate converter 3 shown in FIG.

FIG. 6 is an electric circuit diagram of the VFO 4 shown in FIG.

FIG. 7 is another embodiment of the VFO 4 shown in FIG. 6;
It is an electronic circuit diagram of 4A.

8 is a diagram illustrating values of fv / fs, which is a conversion ratio between fv and a sampling rate, at each time shown in FIGS. 9 to 13. FIG.

9 is a diagram showing frequency characteristics of the digital filter circuit of the present invention shown in FIG. 1 when fv is changed by -20%.

10 is a diagram illustrating frequency characteristics of the digital filter circuit of the present invention illustrated in FIG. 1 when fv is changed by −10%.

11 is a diagram illustrating frequency characteristics of the digital filter circuit of the present invention illustrated in FIG. 1 when fv is not changed.

12 is a diagram illustrating frequency characteristics of the digital filter circuit of the present invention illustrated in FIG. 1 when fv is changed by + 10%.

13 is a diagram showing frequency characteristics of the digital filter circuit of the present invention shown in FIG. 1 when fv is changed by + 20%.

FIG. 14 is a frequency characteristic diagram when the coefficient has no error in the conventional digital filter shown in FIG.

FIG. 15 is a frequency characteristic diagram when a coefficient has an error in the conventional digital filter shown in FIG. 16;

FIG. 16 shows a conventional digital filter, Biquad.
FIG. 4 is a diagram illustrating an example of a signal flow of a second-order IIR filter called a second-order IIR filter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st sampling rate converter 2 Digital filter 3 2nd sampling rate converter 4 VFO 4A VFO 5 Signal line 6 Signal line 7 Signal line 8 Signal line 5d Input data 6s Sampling clock 7d Frequency control signal 8d Rate conversion output 9 Clock pulse 21 Logic circuit 22 One shot pulse 23 Mask circuit 24 Rate conversion output 31 Output of digital filter 2 32 Logic circuit 33 One shot pulse 34 Data holding circuit 61 Constant current circuit 62 MOSFET 63 Oscillation circuit 64 Capacitance 65 Inverter circuit 71 Counter circuit 72 coincidence determination circuit 73 clock pulse 74 frequency control signal 100 adder 101 delay unit 102 multiplier

Claims (8)

[Claims] 1. A digital filter circuit capable of arbitrarily shifting a frequency characteristic, comprising: receiving means to which a first clock pulse is input; and a second clock capable of arbitrarily setting a period. Variable frequency clock generating means for generating a pulse; first rate conversion for converting digital data input in synchronization with the first clock pulse into rate conversion data in synchronization with the second clock pulse and outputting the converted data; Means, for the rate-converted data, an arithmetic processing for outputting only an arbitrary frequency band in synchronization with the second clock pulse, and a digital filter for outputting an arithmetic result; A second rate converter for converting the synchronized operation result into data synchronized with the first clock pulse and outputting the data. Digital filter circuit to be. 2. The digital filter circuit according to claim 1, wherein said variable frequency clock generating means is a voltage controlled oscillator. 3. The variable frequency clock generating means is a counter circuit to which a clock pulse having a frequency sufficiently higher than the second clock pulse is inputted, wherein the variable frequency clock generating means generates a pulse every time the count is arbitrarily set. The digital filter circuit according to claim 1, wherein the digital filter circuit is a variable frequency dividing circuit that outputs. 4. The first rate converting means includes: a synchronizing means for synchronizing the first clock pulse with the second clock pulse; and a synchronizing means for synchronizing the clock pulse output from the synchronizing means with the second clock pulse.
Delay means for delaying the clock pulse by the period of the clock pulse, passing the digital data input only during the time difference between the clock pulse output from the synchronization means and the clock pulse output from the delay means, 4. The digital filter circuit according to claim 1, wherein the input digital data is masked during other periods. 5. The second rate conversion means includes: a synchronization means for synchronizing the first clock pulse with the second clock pulse; and the digital filter based on a clock pulse output from the synchronization means. The digital filter circuit according to any one of claims 1 to 4, wherein the operation result input from the input terminal is latched and output. 6. The method according to claim 6, wherein the second clock pulse includes the first clock pulse.
6. The digital filter circuit according to claim 1, wherein the frequency is higher than the frequency of the clock pulse. 7. An IC comprising the digital filter circuit according to claim 1. 8. An electronic circuit board comprising the digital filter circuit according to claim 1.