JP2001023400A - Semiconductor device and its defect analyzing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its defect analysis method which can improve defect analysis property and can perform easily defect classification. SOLUTION: This device is a defect analyzing circuit section included in a CMOS-SRAM, connected to a memory cell 1 arranged at an intersection of a word line and bit lines BL, BR and connected to a bit line drive circuit driving the bit lines BL, BR by separated paths. It is constituted of a bit line driving circuit 2 for analyzing a defect driving directly the bit lines BL, BR by an external signal. This bit line driving circuit 2 by analyzing a defect is provided with MOS transistors 3, 4 driving directly each bit line BL, BR, an input signal line 7 supplying a signal for analyzing a defect, a word line 9 for analyzing a defect for controlling a gate of each MOS transistor 3, 4, and the like. Test is performed by combining a bit line external operation test using this bit line driving circuit 2 for analyzing a defect, a data-through-test, and a write/read test.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure analysis technique for a semiconductor device, and more particularly to a semiconductor device and a failure analysis method suitable for specifying any one of an input circuit, a memory cell, and an output circuit as a failure. Regarding effective technology to apply.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in a failure analysis technique such as a CMOS / SRAM as an example of a semiconductor device, writing / writing to a memory cell is performed.
A read test and the like are being performed. In the write / read test for this memory cell, a predetermined memory cell is selected by an address signal, data supplied from a write circuit is written to the selected memory cell, and after this write, a predetermined memory cell is again specified by an address signal. Of the selected memory cell, read data from the selected memory cell via an output circuit, determine the match / mismatch between the written data and the read data, and determine a failure in the case of mismatch. .

[0003] With respect to such a failure analysis technique for a semiconductor device, for example, on May 30, 1997, "Monthly Semiconductor" published by Press Journal Inc.
TOR World Special Issue ULSI Test Technology ".

[0004]

The inventors of the present invention have studied the above-described semiconductor device failure analysis technology, and as a result, have found the following.

That is, a write / read test for a memory cell is performed, for example, in a functional configuration as shown in FIG. 11 by using an address circuit including a decoder 11, a word line driver 12, an input circuit including a write circuit 13, a memory cell 1 and the like. , And all circuit operations such as the output circuit 14 are required. In addition, when a defect occurs, it is difficult to specify the defective portion. That is, at the time of failure analysis, as shown in FIG. 12, for example, an address signal and a write signal are input from the outside of the semiconductor device, and an output signal is output.
Looks like a simple black box of AM macro.

Therefore, an object of the present invention is to focus on a failure analysis technique including a write / read test for a memory cell,
It is an object of the present invention to provide a semiconductor device capable of improving defect analysis and easily performing defect classification by adding a functional configuration capable of directly writing data to a bit line, and a defect analysis method thereof.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor device according to the present invention comprises a memory cell disposed at an intersection of a word line and a bit line;
A bit line drive circuit for driving a bit line of the memory cell is connected by a different path from the bit line drive circuit for driving the bit line of the memory cell, and has a bit line drive circuit for failure analysis for directly driving the bit line of the memory cell by an external signal.

In this configuration, one of the bit line driving circuits for failure analysis is connected to the bit line of the memory cell,
A MOS transistor that directly drives the bit line; an input signal line that is connected between the other of the MOS transistors and an external terminal for an input signal to supply a signal for failure analysis; And a word line for failure analysis for gate-controlling the MOS transistor.
It is applied to such as.

Further, in the failure analysis method for a semiconductor device according to the present invention, at the time of failure analysis, the gate of a MOS transistor is directly controlled from an external terminal for failure analysis through a word line for failure analysis, and the external terminal for input signal is connected to A signal for failure analysis is supplied to a bit line via a MOS transistor through an input signal line, a failure analysis signal supplied to the bit line is taken out through an output circuit, and the signal is supplied to an external circuit through the output circuit. A signal for failure analysis taken out at
Compare the signal for failure analysis supplied from the external terminal for the input signal, and determine that the output circuit is defective due to the mismatch.
It has each step.

In particular, as described above, the data directly supplied to the bit line is output through the output circuit, the bit line external operation test for judging the output circuit as defective, and the data supplied from the input circuit is output. A data through test that outputs through a circuit and determines that an input circuit or an output circuit is defective, and writes data supplied from the input circuit to a memory cell,
The reading is performed via the output circuit, and the writing / reading test for judging the input circuit or the memory cell or the output circuit as defective is performed in combination.

Therefore, according to the semiconductor device and its failure analysis method, there is provided a failure analysis bit line drive circuit including a MOS transistor, an input signal line, a failure analysis word line, and the like. By performing a data line test and a write / read test in combination with a bit line external operation test using a bit line drive circuit,
Any one of the input circuit, the memory cell, and the output circuit can be specified as a defect. As a result, the defect analysis of a RAM or the like is improved, and the classification of the defective portion is facilitated.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a functional configuration diagram showing a main part (failure analysis circuit portion) of a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a schematic functional configuration diagram showing the whole of the semiconductor device according to this embodiment. 3 and 4 are flowcharts and explanatory diagrams showing a failure analysis method (data through test), FIGS. 5 and 6 are flowcharts and explanatory diagrams showing a failure analysis method (write / read test), and FIGS. 9 and 10 are a functional configuration diagram and an explanatory diagram showing a classification configuration at the time of failure analysis.

First, with reference to FIG. 1, an example of the configuration of the failure analysis circuit portion of the semiconductor device according to the present embodiment will be described. Although FIG. 1 shows one memory cell portion, it is actually composed of a plurality of memory cells arranged in a grid at intersections of a plurality of word lines and a plurality of bit lines.

The failure analysis circuit portion of the semiconductor device of the present embodiment is, for example, included in a CMOS SRAM, and has a memory cell 1 arranged at an intersection of a word line W and bit lines BL, BR, and a memory cell 1 And a bit line driving circuit 2 for failure analysis, which is connected by a different path from the bit line driving circuit for driving the bit lines BL and BR of the memory cell 1 and directly drives the bit lines BL and BR of the memory cell 1 by an external signal. Have been.

One (source) of each of the bit lines BL and BR of the memory cell 1 is connected to the bit line drive circuit 2 for failure analysis, and the MOS transistors 3 and 3 directly drive the bit lines BL and BR, respectively. 4, the other (drain) of the MOS transistor 3 and an external terminal 5 for an input signal.
An input signal line 7 connected between the other (drain) of the MOS transistor 4 and the input signal external terminal 5 via the inverter 6 for supplying a signal for failure analysis; A word line 9 for failure analysis and the like, which is connected between the gates of the transistors 3 and 4 and the external terminal 8 for failure analysis and controls the gates of the MOS transistors 3 and 4, is provided. The bit line drive circuit 2 for failure analysis is arranged, for example, at a position farthest from the write circuit on the side opposite to the write circuit.

In this CMOS SRAM, in addition to the memory cell 1 and the bit line driving circuit 2 for failure analysis, a decoder 11 to which an address signal is input, as shown in FIG. 12 and an address circuit, a write circuit 1 to which a write signal is input
3, an output circuit 14 for outputting an output signal, a timing generation circuit (not shown) for generating a control signal for an internal circuit, an internal voltage generation circuit for generating an operation voltage of the internal circuit, and the like. And is formed on one semiconductor chip by a well-known semiconductor manufacturing technique.

Next, the operation of the present embodiment will be described with reference to FIG.
10A to 10C, three types of tests in the failure analysis method, that is, a data through test, a write / read test, and a bit line external operation test will be described in order.

1. Data Through Test (FIGS. 3 and 4) In this data through test, the data supplied from the input circuit 15 is output via the output circuit 14, and a test is performed to determine whether or not the input signal is output as it is as an output signal. This is a test for determining that the input circuit 15 or the output circuit 14 is defective.

First, the input circuit 15 is operated to supply, for example, "H" (high level) input data (step 301). Then, the output circuit 14 is operated, and the data supplied to the input circuit 15 is taken out as output data via the output circuit 14 (step 302). The output data is compared with the input data. If the output data is "H", which is the same as the input data, due to a match, it is determined that the output data is normal (step 303). ).

Similarly, the input data of "L", which is the inverted data, is supplied to the input circuit 15 and taken out as output data via the output circuit 14, and this output data is the same as the input data "L". Is normal, and "H" is abnormal. In the data through test, when it is determined that the input circuit 15 or the output circuit 14
Can be determined to be defective.

2. Write / Read Test (FIGS. 5 and 6) In this write / read test, the data supplied from the input circuit 15 is written into the memory cell 1 and the output circuit 14
To test whether the input signal read and written through the input circuit 15 is read as an output signal as it is, and the input circuit 15 or the memory cell 1 or the output circuit 1
This is a test for determining that No. 4 is defective.

First, the input circuit 15 is operated to supply, for example, "H" (high level) write data (step 501). Further, the memory cell 1 is selected, and the “H” data supplied from the input circuit 15 is
(Step 502). And the output circuit 14
Is operated, and the data written in the memory cell 1 is taken out as read data via the output circuit 14 (step 503). The read data and the write data are compared, and if the read data is "H" which is the same as the write data due to a match, it is determined to be normal (step 50).
4) In the case of "L" (low level) due to mismatch, it is determined to be abnormal (step 505).

Similarly, "L" write data, whose data has been inverted, is supplied to the input circuit 15 and written to the memory cell 1, and the data of the memory cell 1 is read out as read data via the output circuit 14 to the outside. If the read data is “L”, which is the same as the write data, it is determined to be normal, and if it is “H”, it is determined to be abnormal. If it is determined in this writing / reading test that there is an abnormality, any one of the input circuit 15, the memory cell 1, and the output circuit 14 can be determined to be defective.

3. Bit line external operation test (FIGS. 7 and 8) In this bit line external operation test, data directly supplied to bit lines BL and BR is output via output circuit 14 and input circuit 15 and memory cell 1 are operated. This is a test for determining that the output circuit 14 is defective without performing the above operation. In the corresponding prior art, when the bit lines BL and BR are to be operated, the bit lines BL and B are written using a write circuit.
It is necessary to operate R or perform a read operation using the address circuit and the memory cell 1.

First, the gates of the MOS transistors 3 and 4 are directly controlled from the external terminal 8 for failure analysis through the word line 9 for failure analysis (step 701). For example, in order to activate each of the MOS transistors 3 and 4, a gate control signal of "H" is supplied from an external terminal 8 for failure analysis.

Further, a signal for failure analysis is supplied from the external terminal 5 for input signals to the bit lines BL and BR via the MOS transistors 3 and 4 through the input signal line 7 (step 702). For example, “H” data is supplied from an external terminal 5 for an input signal and the MOS transistor 3
, And “L” data is supplied to the bit line BL via the inverter 6 and the MOS transistor 4.

Subsequently, the failure analysis signal supplied to each of the bit lines BL and BR is taken out through the output circuit 14 (step 703). Then, the signal for failure analysis taken out via the output circuit 14 is compared with the signal for failure analysis supplied from the external terminal 5 for the input signal. 704), if they do not match, it is determined to be abnormal (step 705). For example, if the data taken out is the same “H” (bit line BL) and “L” (bit line BR) as the supplied data, it is normal, “L” (bit line BL), “H” ( In the case of the bit line BR), an error occurs.

Similarly, "L" failure analysis data, which is the inverted data, is supplied to each bit line BL, BR, taken out through the output circuit 14 and compared, and the taken out data is In the case of "L" (bit line BL) and "H" (bit line BR) which are the same as the supplied data, it is determined that the data is normal,
In the case of "H" (bit line BL) and "L" (bit line BR), it is abnormal. In this bit line external operation test,
When it is determined that the output circuit 14 is abnormal, the output circuit 14 can be determined to be defective.

By combining the above three types of tests, ie, the data through test, the write / read test, and the bit line external operation test, the classification at the time of failure analysis, for example, as shown in FIG. Defective parts occurring in the input circuit 15, the memory cell 1, and the output circuit 14 can be classified and specified. For example, as shown in FIG. 10, when the input circuit 15 is defective, the data through test is abnormal and the bit line external operation test is normal. When the memory cell 1 is defective, the write / read test is abnormal. When the data through test is normal and the output circuit 14 is defective, only the bit line external operation test is abnormal.

In the bit line external operation test, the data directly supplied to the bit lines BL and BR is written into the memory cell 1, the data of the memory cell 1 is read via the output circuit 14, and the written input is written. Test whether the signal is read as it is as an output signal,
Either the memory cell 1 or the output circuit 14 can be determined to be defective.

Therefore, according to the semiconductor device of this embodiment, as the bit line drive circuit 2 for failure analysis, the MOS transistors 3 and 4 for directly driving the bit lines BL and BR, respectively, and the signal for failure analysis are provided. Input signal line 7 to be supplied,
A failure analysis word line 9 for controlling the gates of the MOS transistors 3 and 4 is provided. When a data through test, a write / read test, and a bit line external operation test are performed in combination, a failure point is detected. Any one of the input circuit 15, the memory cell 1, and the output circuit 14 can be specified as a defect. As a result, the failure analysis is improved, the failure location can be easily classified, and in particular, a BIST (Built In Self Test) that generates test information by itself.
For an SRAM that cannot be easily evaluated from outside the LSI, such as an SRAM with a chip, the analysis performance can be improved by installing the bit line drive circuit 2 for failure analysis.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, C
The case where the present invention is applied to a MOS / SRAM has been described.
It is not limited to this, but general-purpose SRAM, DRA
The present invention can be applied to other semiconductor devices equipped with memory cells such as M.

[0036]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) A MOS transistor for directly driving a bit line of a memory cell, an input signal line for supplying a signal for analysis of a failure, a word line for failure analysis for controlling a gate of the MOS transistor, etc. By having the bit line driving circuit, the gate of the MOS transistor is directly controlled at the time of failure analysis, a failure analysis signal is supplied to the bit line through the input signal line, and the failure analysis signal supplied to the bit line is supplied. Can be taken out,
The signal for failure analysis taken out and the supplied signal for failure analysis are compared, and it is possible to determine that the output circuit is defective due to a mismatch.

(2) A data-through test in which an input circuit or an output circuit is determined to be defective is performed in a bit line external operation test in which the output circuit is determined to be defective using the bit line driving circuit for failure analysis described in (1). And a write / read test for judging an input circuit, a memory cell, or an output circuit as defective, it is possible to identify any one of the input circuit, the memory cell, and the output circuit as defective. .

(3) According to the above (1) and (2), in a semiconductor device on which a memory cell such as an SRAM is mounted, by performing a combination of three types of tests, defect analysis is improved,
Failure classification can be easily performed. In particular, RAMs for which failure analysis has become difficult due to the adoption of BIST etc.
On the other hand, it is possible to improve the defect analysis performance and facilitate the defect classification.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram showing a main part (failure analysis circuit part) of a semiconductor device according to an embodiment of the present invention.

FIG. 2 shows a semiconductor device according to an embodiment of the present invention;
It is a schematic functional block diagram showing the whole.

FIG. 3 illustrates a semiconductor device according to an embodiment of the present invention;
It is a flowchart which shows a failure analysis method (data through test).

FIG. 4 illustrates a semiconductor device according to an embodiment of the present invention.
It is explanatory drawing which shows a failure analysis method (data through test).

FIG. 5 illustrates a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a flowchart showing a failure analysis method (write / read test).

FIG. 6 shows a semiconductor device according to an embodiment of the present invention;
FIG. 4 is an explanatory diagram showing a failure analysis method (write / read test).

FIG. 7 shows a semiconductor device according to an embodiment of the present invention;
FIG. 9 is a flowchart showing a failure analysis method (bit line external operation test).

FIG. 8 illustrates a semiconductor device according to an embodiment of the present invention;
FIG. 4 is an explanatory diagram showing a failure analysis method (bit line external operation test).

FIG. 9 illustrates a semiconductor device according to an embodiment of the present invention.
It is a functional block diagram which shows the classification structure at the time of failure analysis.

FIG. 10 is an explanatory diagram showing a classification configuration at the time of failure analysis in the semiconductor device according to one embodiment of the present invention;

FIG. 11 is a schematic functional configuration diagram showing the entirety of a semiconductor device on which the present invention is based;

FIG. 12 is a functional configuration diagram showing a classification configuration at the time of failure analysis in a semiconductor device as a premise of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell 2 Bit line drive circuit 3, 4 MOS transistor 5 External terminal for input signal 6 Inverter 7 Input signal line 8 External terminal for failure analysis 9 Word line for failure analysis 11 Decoder 12 Word line driver 13 Write circuit 14 Output circuit 15 Input circuit W Word line BL, BR Bit line

Claims (5)

[Claims] 1. A memory cell disposed at an intersection of a word line and a bit line, and a bit line drive circuit for driving a bit line of the memory cell are connected by another path, and the memory cell is connected to the memory cell by an external signal. And a bit line drive circuit for failure analysis for directly driving the bit line. 2. The semiconductor device according to claim 1, wherein the bit line drive circuit for failure analysis includes a MOS transistor having one connected to a bit line of the memory cell and directly driving the bit line; An input signal line connected between the other of the MOS transistors and an external signal input terminal for supplying a signal for failure analysis, and connected between a gate of the MOS transistor and an external terminal for failure analysis. A defect analysis word line for gate-controlling the MOS transistor, and at the time of failure analysis, performing gate control of the MOS transistor through the defect analysis word line directly from the external terminal for failure analysis; The MOS from the external terminal for the input signal through the input signal line
A semiconductor device, wherein the signal for failure analysis is supplied to the bit line via a transistor. 3. The semiconductor device according to claim 2, wherein said semiconductor device is a RAM. 4. A memory cell disposed at an intersection of a word line and a bit line, a MOS transistor for directly driving a bit line of the memory cell by an external signal, and an external terminal for input signal for failure analysis. Input signal line for supplying a signal of
A failure analysis bit line drive circuit comprising a failure analysis word line for controlling a gate of a transistor, the failure analysis method for a semiconductor device comprising: Gate controlling the MOS transistor through an analysis word line; and supplying the failure analysis signal from the external terminal for the input signal to the bit line via the MOS transistor through the input signal line. Taking out a signal for failure analysis supplied to the bit line to the outside via an output circuit, a signal for failure analysis taken out via the output circuit, and an external terminal for the input signal. Comparing the output circuit with a signal for failure analysis supplied from the semiconductor device and determining that the output circuit is defective due to a mismatch. Failure analysis method of the location. 5. The failure analysis method for a semiconductor device according to claim 4, wherein the data directly supplied to said bit line is output via said output circuit, and said bit line external circuit determines that said output circuit is defective. An operation test, data supplied from an input circuit are output through the output circuit, a data through test for determining that the input circuit or the output circuit is defective, and data supplied from the input circuit are stored in a memory cell. Writing, reading through the output circuit, and performing a combination of a write / read test for determining that the input circuit or the memory cell or the output circuit is defective,
A failure analysis method for a semiconductor device, wherein any one of the input circuit, the memory cell, and the output circuit is specified as a failure.