JP2001023399A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a test time for guaranteeing the minimum power source voltage previously determined, by which data are normally held can be shortened. SOLUTION: In pull-down circuits 3.1-3.n of a SRAM chip 1, an external power source voltage Vcc is kept at the minimum standard voltage Vr at the time of data retention, while an internal voltage Vi of power source wiring L1-Ln is pulled down in response to a test signal TE1 made a 'H' level. Therefore, compared with a conventional method in which voltage drop is performed according to the external power source voltage Vcc through wiring resistance R1-Rn, newly provided internal voltage Vi of power source wiring L1-Ln can be dropped in a short time so that the test time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a test mode for guaranteeing a predetermined minimum power supply voltage capable of normally retaining data.

[0002]

2. Description of the Related Art FIG. 22 is a block diagram showing a configuration of a conventional static random access memory (hereinafter referred to as SRAM).

Referring to FIG. 22, this SRAM has a plurality of SRAMs arranged in a matrix (four for simplicity of description).
, Memory cells MC1 to MC4, word lines WL1 and WL2 provided corresponding to each row, and bit line pairs BL1 and / BL1; BL2 and / BL2 provided corresponding to each column.

As shown in FIG. 23, a memory cell MC1 has load resistance elements 71 and 72, driver transistors (N-channel MOS transistors) 73 and 74, and an access transistor (N-channel MOS transistor) 7.
5 and 76 and storage nodes N71 and N72. Load resistance elements 71 and 72 are connected between the node of power supply potential Vcc and storage nodes N71 and N72, respectively. Driver transistors 73 and 74 are connected between storage nodes N71 and N72 and a node of ground potential GND, respectively, and have respective gates at storage nodes N72 and N7, respectively.
Connected to 1. The access transistors 75 and 76
The storage nodes N71, N72 and the bit lines BL1,
/ BL1, and each gate is connected to the word line WL1.

The memory cell MC1 sets the access transistor 7 by setting the word line WL1 to the "H" level of the selected level.
The word line WL1 is activated by making it conductive, and the word line WL1 is made inactive by turning off the access transistors 75 and 76 by setting the word line WL1 to the "L" level of the non-selection level.

At the time of a write operation, memory cell MC1 is activated and bit lines BL1, / BL according to write data DI.
One of the signals is set to the “H” level, and the other is set to the “L” level. Thereby, the driver transistors 73, 7
4 is turned on, the other is turned off, and the storage node N
The levels of bit lines BL1 and / BL1 are latched at 71 and N72. After the memory cell MC1 is deactivated,
A current is supplied from the node of the power supply potential Vcc to the storage nodes N71 and N72 via the load resistance elements 71 and 72,
The level of storage nodes N71 and N72, that is, write data DI is held.

At the time of a read operation, when memory cell MC1 is activated, bit lines BL1 and BL1 are driven through the conductive one of driver transistors 73 and 74.
A current flows out of the bit line of / BL1 corresponding to the transistor to the node of ground potential GND, and the bit line goes to "L" level. In this state, bit line B
By comparing the levels of L1 and / BL1, data of memory cell MC1 is read.

The SRAM has bit lines BL1 to BL1.
Bit line load 5 for charging / BL2 to a predetermined potential
1 to 54, and a bit line pair BL1, / BL during a read operation.
1; equalizers 55 and 56 for equalizing the potential between BL2 and / BL2, and a pair of data input / output lines IO and / I
O, bit line pair BL1, / BL1; BL2, / BL2
And column select gates 57 and 58 for connecting the data input / output line pairs IO and / IO to each other.

Each of bit line loads 51-54 is an N-channel MOS diode-connected between a node of power supply potential Vcc and one end of corresponding bit line BL1- / BL2.
It is composed of transistors. Each of equalizers 55 and 56 has a corresponding bit line pair BL1, / BL1;
It is connected between BL2 and has a gate formed of a P-channel MOS transistor receiving bit line equalize signal BLEQ.

The column selection gate 57 is connected between the other end of the bit line BL1 and one end of the data input / output line IO.
A channel MOS transistor, and an N-channel MOS transistor connected between the other end of bit line / BL1 and one end of data input / output line / IO, the gates of two N-channel MOS transistors are connected to column select line CSL1. Connected to one end. The column selection gate 58 is connected to the bit line B
An N-channel MOS transistor connected between the other end of L2 and one end of data input / output line IO;
An N-channel MOS transistor connected between the other end of L2 and one end of data input / output line / IO, the gates of two N-channel MOS transistors are connected to column select line C
Connected to one end of SL2.

Further, this SRAM has a row decoder 5
9, a control circuit 60, a column decoder 61, a write circuit 62, and a read circuit 63. Row decoder 59 raises any one of a plurality of word lines WL1 and WL2 to a selected level “H” according to an externally applied row address signal RA. Control circuit 60 controls S in accordance with an externally applied chip select signal / CS, write enable signal / WE and read enable signal / OE.
It controls the entire RAM. Column decoder 61 includes a plurality of column select lines C according to an externally applied column address signal CA.
One of the column selection lines SL1 and CSL2 is raised to the selected level "H".

Write circuit 62 and read circuit 63 are both connected to the other end of data input / output line pair IO, / IO. Write circuit 62 has an externally applied write data D
I is written into the memory cell selected by the row decoder 59 and the column decoder 61. Read circuit 63 externally outputs read data DO from a memory cell selected by row decoder 59 and column decoder 61.

Next, the SRA shown in FIGS.
The operation of M will be described. At the time of the write operation, for example, word line WL1 is raised to the selected level "H" level by row decoder 59, and memory cells MC1, MC
2 is activated. Then, for example, column select line CSL1 is raised to the selected level "H" by column decoder 61, column select gate 57 is rendered conductive, and activated memory cell MC1 is connected to bit line pair BL1, / BL1 and data input. Output line pair IO, / IO is connected to write circuit 62.

Write circuit 62 sets one of data input / output line pairs IO and / IO to "H" level and the other to "L" level according to externally applied data DI to memory cell MC1. Write the data. When word line WL1 and column select line CSL1 fall to "L" level, data is stored in memory cell MC1.

At the time of a read operation, column select line CSL1 is raised to the selected level "H" level by column decoder 61, column select gate 57 is rendered conductive, and bit line pair B is turned on.
L1 and / BL1 are connected to read circuit 63 via data input / output line pair IO and / IO. Next, bit line equalize signal / BLEQ attains the activation level of "L" level, equalizers 55 and 56 conduct, and the potentials of bit lines BL1 and / BL1 and BL2 and / BL2 are equalized, respectively. Bit line equalize signal / BLEQ attains the "H" level of the inactivation level, and equalizers 55 and 56
Is turned off, row decoder 59 raises, for example, word line WL1 to the selected level of "H" level, and memory cells MC1 and MC2 are activated. Thereby, a current flows into memory cell MC1 from one of bit line pair BL1, / BL1 according to the data stored in memory cell MC1, and data input / output line pair I
The potential of one of O and / IO decreases. Readout circuit 6
3 compares the potentials of the data input / output lines IO and / IO, and outputs data DO according to the comparison result to the outside.

In such an SRAM, a test for guaranteeing a minimum voltage standard at the time of data retention is performed before shipment. Hereinafter, this test will be described.

FIG. 24 is a circuit block diagram showing a main part of the SRAM chip 81. In FIG. 24, this SRA
The M chip 81 includes n (where n is a natural number) power supply wirings L1 to Ln.

One ends of power supply lines L1 to Ln are commonly connected and receive an external power supply potential Vcc. Power supply lines L1 to Ln
Are supplied to the entire surface of the chip to supply the power supply potential Vcc to the internal circuits (including all the circuits shown in FIG. 22).
The power supply wirings L1 to Ln have wiring resistances R1 to Rn and wiring capacitances C1 to Cn, respectively.

FIG. 25 is a time chart showing the operation of the SRAM chip 81 during the test. In FIG. 25, first, the SRAM chip 81 is set to a normal active state, and predetermined data is written to all memory cells (time t0 to t3). At this time, the chip select signal / CS is at the “L” level, the external power supply potential Vcc is at the normal level Va, and the potentials Vi at the other ends of the power supply lines L1 to Ln are also at Va.

Next, at time t3, chip select signal / CS attains the "H" level of the inactive level, and SRAM chip 81 is set to the standby state, and external power supply potential Vcc is set to minimum standard voltage Vr at the time of data retention. (Vr <Va). Power supply wiring L1
The internal potential Vi of Ln approaches the external power supply potential Vcc (= Vr) via the wiring resistances R1 to Rn. After the internal potential Vi of the power supply lines L1 to Ln has reached the minimum standard potential Vr, the SRAM chip 81 is left in a data retention state (standby state) for a predetermined time.

Next, the chip select signal / CS is set to the "H" level of the activation level and the external power supply potential V
cc is set to the normal level Va, and the SRAM chip 81
Is returned to the normal active state. In this state, the data of each memory cell is read and compared with the write data. If the read data and the write data of all the memory cells match, the minimum voltage standard is guaranteed.

[0022]

However, the conventional SRA
In the M chip 81, since it took a long time from lowering the external power supply voltage Vcc to the minimum standardized voltage Vr until the internal voltage Vi of the power supply lines L1 to Ln became the minimum standardized voltage Vr,
There is a problem that the test time becomes longer and the productivity becomes lower. In addition, with the recent increase in the capacity of the SRAM, the wiring resistances R1 to Rn and the wiring capacitances C1 to Cn of the power supply wirings L1 to Ln increase, and the test time tends to be longer.

Accordingly, a main object of the present invention is to provide a semiconductor memory device capable of shortening a test time for a test for guaranteeing a predetermined minimum power supply voltage capable of normally retaining data. It is to provide.

[0024]

The invention according to claim 1 is
A semiconductor memory device having a test mode for guaranteeing a predetermined minimum power supply voltage capable of holding data normally, wherein one end of the semiconductor memory device is supplied with a normal power supply voltage during a normal operation to perform a test. In the mode, the power supply wiring to which the minimum power supply voltage is applied, the memory circuit driven by the power supply voltage from the power supply wiring to hold data, and the test signal for instructing the execution of the test mode are given And a pull-down circuit for reducing the voltage of the power supply wiring to the minimum power supply voltage.

According to a second aspect of the present invention, in the pull-down circuit according to the first aspect of the present invention, one or more diode elements each having a sum of threshold voltages equal to a minimum power supply voltage, and a test signal supplied thereto. And a connection circuit for connecting one or more diode elements in series between the power supply wiring and the node of the reference potential in accordance with the operation.

According to a third aspect of the present invention, there is provided the pull-down circuit according to the first aspect of the present invention, wherein the pulse generating circuit outputs a pulse signal having a predetermined pulse width in response to the application of the test signal; A switching element that is connected between the wiring and the node of the reference potential and that conducts in a pulsed manner in response to a pulse signal from the pulse generation circuit.

In the invention according to claim 4, claims 1 to 3 are provided.
The semiconductor memory device according to any one of the above aspects is a static semiconductor memory device, and the memory circuit includes a plurality of static memory cells arranged in a matrix and each holding data.

[0028]

[First Embodiment] FIG. 1 is a circuit block diagram showing a main part of an SRAM chip 1 according to a first embodiment of the present invention. 1, this SRAM chip 1 includes n power supply lines L1 to Ln, an input buffer 2
And n pull-down circuits 3.1 to 3. n.

One ends of power supply lines L1 to Ln are commonly connected to receive external power supply potential Vcc. Power supply lines L1 to Ln
Are supplied to the entire surface of the chip to supply the power supply potential Vcc to the internal circuits (including all the circuits shown in FIG. 22).
The power supply wirings L1 to Ln have wiring resistances R1 to Rn and wiring capacitances C1 to Cn, respectively.

The input buffer 2 receives the external test signal TE1
, An internal test signal TE1 'is generated, and the internal test signal TE1' is supplied to the pull-down circuits 3.1-3. n. External test signal TE1 attains an active level of “H” during data retention, and at an inactive level of “L” during other periods. The internal test signal TE1 'goes high when the external test signal TE1 goes high, and goes low when the external test signal TE1 goes low. Become.

Pulldown circuits 3.1 to 3. n is provided corresponding to the power supply lines L1 to Ln, respectively. Pull-down circuit 3.1 includes N-channel MOS transistors 4 to 6 connected in series between input node N1 and a node of ground potential GND, as shown in FIG. Input node N1
Are connected to the other end of the corresponding power supply line L1 and receive the internal potential Vi of the power supply line L1. The gates of the N-channel MOS transistors 4 and 5 are connected to their respective drains. Each of N channel MOS transistors 4 and 5 operates as a diode. N channel MOS
The gate of transistor 6 receives internal test signal TE1 '.

When internal test signal TE1 'attains the "H" level of the activation level, N-channel MOS transistor 6
Is turned on to activate the pull-down circuit 3.1, and when the internal test signal TE1 'goes to the "L" level of the inactivation level, the N-channel MOS transistor 6 is turned off and the pull-down circuit 3.1 is inactivated. You.

The sum of the threshold voltage Vth4 of the N-channel MOS transistor 4 and the threshold voltage Vth5 of the N-channel MOS transistor 5, VT = Vth4 + Vth5,
It is set to the minimum standard voltage Vr at the time of data retention. Here, assuming that the potentials at the drains of N-channel MOS transistors 4 to 6 are V4 to V6, N-channel MOS transistor 4 is turned off at V5> V4-Vth4, and N-channel MOS transistor 5 is V6> V5-V.
Turns off at th5. N channel MOS transistor 4,
5 is on, V5 = V4-Vth4, V6 =
V5−Vth5, and V6 = V4−VT.

Therefore, the wiring resistance value R of the power supply wiring L1
Assuming that 1 is sufficiently larger than the sum of the on-resistance values of the N-channel MOS transistors 4 to 6, the N-channel MOS transistor 6 turns on and the pull-down circuit 3.
1 is activated, when Vcc ≧ VT, Vi = VT, and when Vcc <VT, Vi = V
cc. When the N-channel MOS transistor 6 is turned off and the pull-down circuit 3.1 is inactivated, Vi = Vcc. Other pull-down circuits 3.2
~ 3. n has the same configuration as the pull-down circuit 3.1.

FIG. 3 shows the SRAM shown in FIGS.
5 is a time chart illustrating an operation of the chip 1 during a test.

In FIG. 3, first, the SRAM chip 1 is set to a normal active state, and predetermined data is written to all memory cells (time t0 to t3). At this time, external test signal TE1 attains “L” level, and external power supply potential V
cc is at the normal level Va. Therefore, internal test signal TE1 'attains "L" level, and pull-down circuits 3.1-3. n N-channel MOS transistor 6
Is turned off, the internal potential Vi of the power supply lines L1 to Ln also becomes Va, and V6 = Va−VT.

Next, at time t3, the chip select signal / CS goes to the "H" level of the inactive level, and the SRAM chip 1 is set to the standby state.
External test signal TE1 attains an "H" level, and external power supply potential Vcc attains minimum specified potential Vr. As a result, internal test signal TE1 'attains "H" level, and pull-down circuits 3.1 to 3. n N-channel MOS transistor 6 is turned on, V6 = GND, and power supply lines L1 to Ln
Internal potential Vi sharply falls to the minimum specified potential Vr,
The SRAM chip 1 is set in a data retention state.
At this time, when Vi <Vr, the N-channel MOS transistors 4 and 5 are turned off, so that Vi does not become lower than Vr.

Accordingly, the internal potential Vi of the power supply lines L1 to Ln can be reduced to the minimum standard potential Vr in a shorter time than in the conventional case, and the test time can be reduced.

The SRAM chip 1 is brought into a normal active state after being brought into a data retention state for a predetermined time, and data in each memory cell is read and compared with write data. If the read data and the write data of all the memory cells match, the minimum voltage standard is guaranteed, and if they do not match, the minimum voltage standard is not guaranteed.

When VT> Vr is set instead of VT = Vr, as shown in FIG. 4, when Vi <VT, the N-channel MOS transistors 4 and 5 are turned off, so that Vi = VT. Thereafter, the internal potential Vi of the power supply wirings L1 to Ln is changed to the external power supply potential V via the wiring resistances R1 to Rn.
It gradually decreases toward cc (= Vr) (time t4 to t5). Therefore, when VT> Vr, V
The internal potential V of the power supply lines L1 to Ln is higher than when T = Vr.
The time required for i to decrease to the minimum standard potential Vr increases.

When VT <Vr is set instead of VT = Vr, as shown in FIG.
The internal potential Vi of n rapidly drops to VT. Accordingly, the time when Vi decreases to Vr is the same as when VT = Vr, but there are cases where Vi falls below Vr and data cannot be held normally. Therefore, in this case, the test cannot be performed normally.

In this embodiment, the pull-down circuits 3.1 to 3. Although two N-channel MOS transistors diode-connected to each of n are provided, VT = V
If it can be set to r, one diode-connected N-channel MOS transistor may be provided.
More than one may be provided.

In this embodiment, the pull-down circuits 3.1 to 3. Although n is connected to the other end of power supply lines L1 to Ln, it may be connected to another portion, for example, an intermediate portion of power supply lines L1 to Ln.

In this embodiment, the power supply line L1
To Ln, one pull-down circuit is provided, but a plurality of pull-down circuits may be provided.

Hereinafter, a modified example of the pull-down circuit 3.1 will be described. In the pull-down circuit of FIG. 6, the diode-connected N-channel M of the pull-down circuit 3.1 of FIG.
OS transistors 4 and 5 are replaced by diode-connected P-channel MOS transistors 10 and 11, respectively.

In the pull-down circuit shown in FIG. 7, the diode-connected N-channel MO of the pull-down circuit 3.1 shown in FIG.
P-channel M in which S transistor 5 is diode-connected
Replaced by OS transistor 12. In the pull-down circuit of FIG. 8, the diode-connected N-channel MOS transistor 4 of the pull-down circuit 3.1 of FIG. 2 is replaced by a diode-connected P-channel MOS transistor 13.

In the pull-down circuit of FIG. 9, the N-channel MOS transistor 6 of the pull-down circuit 3.1 of FIG.
It is replaced by a channel MOS transistor 14. Internal test signal TE1 'is input to the gate of P-channel MOS transistor 14 via inverter 15. FIG.
In the pull-down circuit of FIG. 9, the N-channel MOS transistors 4, 5 which are diode-connected of the pull-down circuit of FIG.
Are replaced by diode-connected P-channel MOS transistors 16 and 17, respectively.

In the pull-down circuit of FIG. 11, the diode-connected N-channel MOS transistor 5 of the pull-down circuit of FIG.
Replaced by transistor 18. In the pull-down circuit of FIG. 12, the diode-connected N-channel MOS transistor 4 of the pull-down circuit of FIG. 9 is replaced by a diode-connected P-channel MOS transistor 19. Instead of the pull-down circuit 3.1 of FIG. 2, that is, the pull-down circuits 3.1 to 3. n for each of n
The same effect can be obtained by using any one of the pull-down circuits in FIG.

[Second Embodiment] FIG. 13 is a circuit block diagram showing a main part of an SRAM chip 21 according to a second embodiment of the present invention. 13, this SRAM chip 21 includes n power supply lines L1 to Ln, an input buffer 2
2, 23, a pulse generation circuit 24, and n pull-down circuits 25.1 to 25. n. Power supply wiring L1 to L
n is as described in FIG.

The input buffer 22 receives the external test signal TE
2 to generate an internal test signal TE2 'and apply the internal test signal TE2' to the pulse generation circuit 24. External test signal TE2 attains an active level of “H” during a predetermined period including a data retention period during a test, and attains an inactive level of “L” during other periods. Internal test signal TE2 'attains "H" level when external test signal TE2 attains "H" level, and at "L" level according to external test signal TE2 attaining "L" level. become.

Input buffer 23 generates internal chip select signal / CS 'in response to chip select signal / CS, and supplies internal chip select signal / CS' to pulse generating circuit 24. The chip select signal CS is at "L" level when active, and is at "H" level during standby. The internal chip select signal / CS 'becomes "H" level when the chip select signal CS becomes "H" level, and becomes "H" level when the chip select signal / CS becomes "L" level. L "level.

The pulse generating circuit 24 includes AND gates 31 and 32 and a delay circuit 33, as shown in FIG. 14, and the delay circuit 33 is an odd-numbered stage (3 in FIG. 14) connected in series.
Stage) inverter 34. AND gate 31 receives internal test signal TE2 'and internal chip select signal /
Receive CS '. The output of the AND gate 31 is directly input to one input node of the AND gate 32,
The signal is input to the other input node of the AND gate 32 via the delay circuit 33. The output of the AND gate 32 becomes the output signal φ24 of the pulse generation circuit 24.

When test signal TE2 'is at the "L" level of the inactivation level, pulse generation circuit 24 is inactivated, the outputs of AND gates 31 and 32 are fixed at the "L" level, and signal φ24 is also output. Fixed at “L” level. When test signal TE2 'attains the activation level of "H", pulse generation circuit 24 is activated. While the internal chip select signal CS ′ is at “L” level, the output of the AND gate 31 is at “L” level, the output of the delay circuit 33 is at “H” level, and the output signal φ24 of the AND gate 32 is “ L "level. When internal chip select signal / CS 'rises to "H" level, AND gate 3
1 goes high, the signal φ24 rises to the “H” level, and after the delay time of the delay circuit 33 elapses, the output of the delay circuit 33 falls to the “L” level, and the signal φ24
Falls to the “L” level. Therefore, the signal φ24
Delay circuit 33 in response to internal chip select signal CS 'rising from "L" level to "H" level.
Rises to "H" level for the delay time of. Signal φ24
Are pull-down circuits 25.1 to 25. n.

Pulldown circuits 25.1 to 25. n is provided corresponding to the power supply lines L1 to Ln, respectively. Pull-down circuit 25.1, as shown in FIG. 15, includes N connected between input node N2 and a node of ground potential GND.
It includes a channel MOS transistor 35. Input node N
2 is connected to the other end of the corresponding power supply line L1 and receives the internal potential Vi of the power supply line L1. The gate of N-channel MOS transistor 35 receives output signal φ24 of pulse generation circuit 20. While signal φ24 is at “L” level, N-channel MOS transistor 35 is turned off and signal φ2
4 becomes "H" level for a predetermined time, the N-channel MO
The S transistor 35 is turned on for that time and the power supply line L
1 is connected to the node of ground potential GND. The time during which the signal φ24 is at the “H” level is set so that the internal potential Vi of the power supply line L1 falls from Va to Vr.

FIG. 16 shows the SRA shown in FIGS.
5 is a time chart illustrating an operation of the M chip 21 during a test.

In FIG. 16, first, the SRAM chip 21
Is set to a normal active state, and predetermined data is written to all memory cells (time t0 to t1). At this time, external test signal TE2 and chip select signal / CS are both at "L" level, and external power supply potential Vcc is at normal level Va. Therefore, internal test signal TE2 'and internal chip select signal CS' both attain an "L" level, signal .phi.24 attains an "L" level, and pull-down circuits 25.1-25. n N channels M
The OS transistor 35 is turned off, and Vi = Va.

Next, at time t1, external test signal TE2 attains the activation level "H" level, internal test signal TE2 'attains the "H" level, and pulse generation circuit 24 is activated. Next, at time t3, the chip select signal / CS goes to the “H” level of the inactivation level, the SRAM chip 21 enters the standby state, and the external power supply potential Vcc becomes the minimum standard potential Vr. In accordance with chip select signal / CS, internal chip select signal / CS 'also rises to "H" level, and in response to this, pulse signal P of predetermined pulse width W1 is generated by pulse generation circuit 24. In response to this pulse signal P (φ24), pull-down circuits 25.1 to 25. The n-channel N-channel MOS transistor 35 is turned on for a predetermined time W1, the internal potential Vi of the power supply wirings L1 to Ln sharply falls to the minimum specified potential Vr, and the SRAM chip 21 is in a data retention state.

Therefore, the internal potential Vi of the power supply lines L1 to Ln can be reduced to the minimum standard potential Vr in a shorter time than before, and the test time can be shortened.

The SRAM chip 21 is brought into a normal active state after being brought into the data retention state for a predetermined time, and the data of each memory cell is read and compared with the write data. If the read data and the write data of all the memory cells match, the minimum voltage standard at the time of data retention is guaranteed, and if they do not match, it is not guaranteed.

The internal potential Vi of the power supply lines L1 to Ln
Changes depending on the pulse width of the pulse signal P. In FIG. 16, at the same time when the internal potential Vi of the power supply lines L1 to Ln becomes the minimum specified potential Vr, the pulse signal P goes to the “L” level and the pull-down circuits 25.1 to 25. n N-channel MOs
The S transistor 35 turned off.

However, when the pulse width of the pulse signal P is W2 smaller than W1, as shown in FIG. 17, during the period of the pulse width W2 of the pulse signal P, the pull-down circuit 25.1 is used.
~ 25. The n-channel MOS transistor 35 is turned on and the internal potential Vi of the power supply lines L1 to Ln drops sharply. However, since the N-channel MOS transistor 35 is turned off, Vi is applied to the external power supply via the wiring resistances R1 to Rn. It gradually decreases toward the potential Vcc (= Vr). For this reason, the pulse width of the pulse signal P becomes longer than the case of W1 in which the internal potential Vi of the power supply lines L1 to Ln falls to the minimum standard potential Vr.

In the case where the pulse width of the pulse signal P is W3 larger than W1, as shown in FIG. 18, the pulse width is set such that the internal potential Vi of the power supply lines L1 to Ln falls to the minimum standard potential Vr. Same as W1, but Vi drops below internal power supply potential Vcc (= Vr),
Pull-down circuits 25.1 to 25. n N-channel MOS
Data may not be held during a period from when the transistor 35 is turned off to when Vi rises to Vr.
Therefore, in this case, the test cannot be performed normally.

Hereinafter, a modification of the second embodiment will be described. In the pull-down circuit of FIG. 19, the N-channel MOS transistor 3 of the pull-down circuit 25.1 of FIG.
5 is replaced by a P-channel MOS transistor 36.
The output signal φ24 of the pulse generation circuit 24 is
7 is input to the gate of the P-channel MOS transistor 36. Pull-down circuit 25.1 shown in FIG.
Instead of the pull-down circuit 25.1 of FIG.
~ 25. The same effect can be obtained by using the pull-down circuit of FIG. 19 instead of each of n.

In the SRAM chip 41 shown in FIG.
The input buffers 22 and 23 and the pulse generation circuit 24 of the SRAM chip 21 are replaced with the input buffer 2 and the pulse generation circuit 42.

The input buffer 2 receives the external test signal TE1
And generates an internal test signal TE1 'in response to the Signals TE1 and TE1 'are the same as those described in the first embodiment.

As shown in FIG. 21, pulse generating circuit 42 includes an AND gate 43 and a delay circuit 44. Delay circuit 44 includes an odd-numbered (three in the figure) inverter 45 connected in series. The internal test signal TE1 'is AND
The signal is directly input to one input node of the gate 43, and is input to the other input node of the AND gate 43 via the delay circuit 44. The output of the AND gate 43 becomes the output signal φ42 of the pulse generation circuit 42.

While internal test signal TE1 'is at "L" level, the output of delay circuit 44 is at "H" level and signal φ42 is at "L" level. When internal test signal TE1 'rises to "H" level, signal .phi.42 rises to "H" level, and when the delay time of delay circuit 44 elapses and the output of delay circuit 44 falls to "L" level, signal .phi. φ42 also falls to the “L” level. Therefore, the pulse generation circuit 42 responds to the external test signal TE1 'to output the pulse signal P having the predetermined pulse width W1 to the pull-down circuit 2.
5.1-25. n. Pulldown circuits 25.1 to 25.1
25. n is the power supply line L1 in response to the pulse signal P.
ＬLn is reduced to the minimum specified potential Vr.
Therefore, even in this SRAM chip 41, S in FIG.
The same effect as that of the RAM chip 21 can be obtained.

In the SRAM chip 41 shown in FIG. 20, the pulse generation circuit 42 is removed, and the output signal TE1 'of the input buffer 2 is supplied to the pull-down circuits 25.1 to 25. The external test signal TE1 may be converted into a pulse signal after being directly input to n.

The pull-down circuits 25.1 to 25... Of the SRAM chips 21 and 41 shown in FIGS. n with the pull-down circuits 3.1 to 3. It may be replaced by n.

It should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0071]

As described above, according to the first aspect of the present invention, the pull-down circuit for reducing the voltage of the power supply wiring to the minimum power supply voltage in response to the test signal is provided.
Therefore, the internal voltage of the power supply wiring can be reduced to the minimum power supply voltage in a short time as compared with the conventional method in which a current flows through only one end of the power supply wiring to reduce the internal voltage of the power supply wiring, thereby shortening the test time. Can be achieved.

According to a second aspect of the present invention, there is provided the pull-down circuit according to the first aspect of the present invention, wherein the pull-down circuit includes one or more diode elements each having a sum of threshold voltages equal to a minimum power supply voltage, and responding to a test signal. And a connection circuit for connecting one or more diode elements in series between the power supply wiring and the node of the reference potential. In this case, the internal voltage of the power supply wiring can be accurately reduced to the minimum power supply voltage.

According to a third aspect of the present invention, there is provided the pull-down circuit according to the second aspect of the present invention, wherein the pulse generating circuit outputs a pulse signal having a predetermined pulse width in response to a test signal; And a switching element that is turned on in a pulsed manner in response to the pulse signal. In this case, the internal voltage of the power supply wiring can be reduced in a shorter time.

In the invention according to claim 4, claims 1 to 3 are provided.
The semiconductor memory device according to any one of the above is a static semiconductor memory device, and the memory circuit includes a plurality of static memory cells arranged in a matrix. The present invention is particularly effective in this case.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of an SRAM chip according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a pull-down circuit shown in FIG.

FIG. 3 is a time chart for explaining effects of the SRAM chip shown in FIG. 1;

FIG. 4 is another time chart for explaining the effect of the SRAM chip shown in FIG. 1;

FIG. 5 is still another time chart for explaining the effect of the SRAM chip shown in FIG. 1;

FIG. 6 is a circuit diagram showing a modification of the first embodiment.

FIG. 7 is a circuit diagram showing another modification of the first embodiment.

FIG. 8 is a circuit diagram showing still another modification of the first embodiment.

FIG. 9 is a circuit diagram showing still another modification of the first embodiment.

FIG. 10 is a circuit diagram showing still another modification of the first embodiment.

FIG. 11 is a circuit diagram showing still another modification of the first embodiment.

FIG. 12 is a circuit diagram showing still another modification of the first embodiment.

FIG. 13 is a circuit block diagram showing a configuration of an SRAM chip according to a second embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of a pulse generation circuit shown in FIG.

FIG. 15 is a circuit diagram showing a configuration of the pull-down circuit shown in FIG.

FIG. 16 is a time chart for explaining effects of the SRAM chip shown in FIG. 13;

FIG. 17 is another time chart for explaining the effect of the SRAM chip shown in FIG. 13;

FIG. 18 is still another time chart for describing effects of the SRAM chip shown in FIG. 13;

FIG. 19 is a circuit diagram showing a modification of the second embodiment.

FIG. 20 is a circuit block diagram showing a configuration of another modification of the second embodiment.

FIG. 21 is a circuit diagram showing a configuration of a pulse generation circuit shown in FIG. 20;

FIG. 22 is a circuit block diagram showing a configuration of a conventional SRAM.

FIG. 23 is a circuit diagram showing a configuration of a memory cell shown in FIG. 22.

FIG. 24 is a circuit block diagram showing a main part of a conventional SRAM chip.

FIG. 25 is a time chart for explaining a problem of the SRAM chip shown in FIG. 24;

[Explanation of symbols]

1,21,41,81 SRAM chip, 2,22,2
3. Input buffer, 3.1 to 3. n, 25.1-25.
n pull-down circuit, L1 to Ln power supply wiring, R1 to R
n wiring resistance, C1 to Cn wiring capacitance, 4 to 6, 35
N-channel MOS transistor, 10 to 14, 16 to 1
9,36 P-channel MOS transistor, 15,3
4, 37, 45 inverter, 24, 42 pulse generating circuit, 32, 33, 43 AND gate, 34, 44
Delay circuit, 51-54 bit line load, 55, 56 equalizer, 57, 58 column selection gate, 59 row decoder, 60 control circuit, 61 column decoder, 62 write circuit, 63 read circuit, MC1-MC4 memory cell, W
L1, WL2 word lines, BL1, / BL1, BL2
/ BL2 bit line, CSL1, CSL2 column select line,
IO, / IO data input / output lines, 71, 72 load resistance elements, 73, 74 driver transistors, 75, 76
Access transistor.

Claims (4)

[Claims] 1. A semiconductor memory device having a test mode for guaranteeing a predetermined minimum power supply voltage capable of normally retaining data, wherein one end of the semiconductor memory device has a normal power supply during normal operation. A power supply line to which a voltage is applied and the minimum power supply voltage is applied in the test mode; a memory circuit driven by a power supply voltage from the power supply line to retain the data; and an instruction for executing the test mode. A semiconductor memory device, comprising: a pull-down circuit for lowering the voltage of the power supply wiring to the minimum power supply voltage in response to the application of a test signal. 2. The pull-down circuit according to claim 1, wherein one or two or more diode elements having a sum of respective threshold voltages equal to the minimum power supply voltage and the test signal supplied thereto. 2. The semiconductor memory device according to claim 1, further comprising a connection circuit for connecting two or more diode elements in series between said power supply wiring and a node of a reference potential. 3. A pulse generation circuit for outputting a pulse signal having a predetermined pulse width in response to the application of the test signal, and a circuit between the power supply line and a node of a reference potential. 2. The semiconductor memory device according to claim 1, further comprising: a switching element connected to conduct in a pulsed manner in response to a pulse signal from said pulse generation circuit. 4. The semiconductor memory device is a static semiconductor memory device, wherein the memory circuit includes a plurality of static memory cells arranged in a matrix and each holding data.
The semiconductor memory device according to claim 1.