JP2001022467A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contract a layout area of a clock power feeding system. SOLUTION: This device is provided with a clock synthesizing means (10) for forming a synthetic clock signal on the basis of a first clock signal (ϕ0P) and a second clock signal (ϕ1P) whose phase is different from that of the first clock signal, transmission means (41 and AMP1 to AMP5) for transmitting the synthetic clock signal to each part, a first flip-flop circuit (SM-FF) for synchronization operating with a waveform leading edge of the synthetic clock signal as a trigger, and a second flip-flop circuit (MS-FF) for synchronization operating with a waveform trailing edge of the synthesis clock signal as a trigger. Then, formation of the transmission means (41 and AMP1 to AMP5) per each phase is made unnecessary and contraction of a layout area of a clock power feeding system is attained by making transmission objects of the transmission means the synthesis clock signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
Furthermore, the present invention relates to a clock signal distribution technique therein.

[0002]

2. Description of the Related Art As a conventional clock distribution circuit, for example, Japanese Unexamined Patent Application Publication No. Hei 5-233092 discloses that a wiring length and a width of a wiring through which a clock signal is propagated are made uniform, and the wiring is formed in the letter H of the alphabet. A technique for reducing skew by arranging the skew is described. The deterioration of the input clock signal is reduced by connecting a multistage relay buffer. That is, a plurality of circuit blocks each having a predetermined circuit operated by inputting a clock signal distributed from a clock buffer, and a clock from a clock input circuit receiving an external clock signal to a clock buffer of each circuit block is provided. The transmission path is formed hierarchically by branching the clock wiring for each relay buffer, and forming the clock wiring in each layer in an H-shape with the same length and width. A flip-flop constituting a required circuit is arranged in a circuit block connected to the end of the clock wiring hierarchically formed with the same length and the same width,
A clock signal is supplied to each flip-flop.

[0003]

However, when the inventors of the present application examined a semiconductor integrated circuit to which a plurality of clock signals having different phases from each other are distributed, a transmission means for transmitting a clock for each phase was provided. It has been found that the adoption of the method of reducing the skew by arranging the wiring in the letter H of the alphabet increases the layout area of the clock power supply system and hinders the miniaturization of the chip size of the semiconductor integrated circuit. In other words, by providing a transmission means for transmitting a clock for each phase, the number of clock wirings and the number of relay buffers increase, so that the layout area of the clock power supply system increases and the chip size of the semiconductor integrated circuit decreases. I have to grow.

An object of the present invention is to apply a technique for reducing a layout area of a clock power supply system.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, clock synthesizing means for forming a synthetic clock signal based on a first clock signal and a second clock signal having a phase different from that of the first clock signal, and transmitting means for transmitting the synthetic clock signal to each section. A first flip-flop circuit that operates synchronously with a rising edge of the waveform of the composite clock signal transmitted by the transmission unit as a trigger, and performs a synchronous operation with a waveform falling edge of the composite clock signal distributed by the transmission unit as a trigger A semiconductor integrated circuit is configured including the second flip-flop circuit.

According to the above means, the clock synthesizing means synthesizes the first clock signal and the second clock signal,
The transmitting unit transmits the synthesized clock signal synthesized by the clock synthesizing unit to each unit. By setting the transmission target of the transmission means to the synthesized clock signal, it is not necessary to form the transmission means for each phase, which achieves a reduction in the layout area of the clock power supply system.

Further, the clock synthesizing means includes a first synthesizing means.
A set reset circuit that forms a rising edge of the waveform of the synthesized clock signal in synchronization with a rising edge of the waveform of the clock signal and forms a falling edge of the waveform of the synthesized clock signal in synchronization with the second clock signal; be able to.

Further, the clock synthesizing means includes a shape circuit for narrowing a pulse width of the first clock signal, an input buffer for receiving the second clock signal, and a first clock output from the shape circuit. A set reset for forming a rising edge of the waveform of the synthesized clock signal in synchronization with a rising edge of the waveform of the signal and forming a falling edge of the waveform of the synthesized clock signal in synchronization with the second clock signal output from the input buffer; The circuit may include a circuit and an output buffer for supplying the synthesized clock signal output from the set reset circuit to the transmission unit.

[0010]

FIG. 4 shows an example of a clock power supply system in a semiconductor integrated circuit according to the present invention. FIG.
Is a microprocessor formed on a single semiconductor substrate such as a single-crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique, although not particularly limited.

At the center of such a semiconductor integrated circuit 100, a clock synthesizing circuit 10 for forming a synthetic clock signal based on the first clock signal and the second clock signal is arranged. From the clock synthesizing circuit 10, the clock transmission paths of the respective circuit blocks are hierarchically formed by wiring branches, and the clock wiring is formed in an H-shape with the same length and the same width for each hierarchy. Flip-flops constituting a required circuit are arranged in a circuit block connected to the ends of clock wirings having a hierarchically equal length and width, and a clock signal is supplied to each flip-flop.

Focusing on one route in the clock power supply system, after the output signal of the clock synthesizing circuit 10 is buffered in the relay buffer AMP1, the circuit connected to the end of the clock wiring via the relay buffers AMP2 to AMP5. Is transmitted to

Here, transmission means for transmitting the composite clock signal is formed, including the clock wiring 41 formed in an H shape and the relay buffers AMP1 to AMP5.

FIG. 1 shows a main configuration of a clock power supply system.

As shown in FIG. 1, a first clock signal φ0P and a second clock signal φ1P are formed in the clock synthesizing circuit 10. A composite clock signal outP is formed based on the first clock signal φ0P and the second clock signal φ1P, and is supplied to the transmission means (41, AMP1 to AMP5) at the subsequent stage. Based on this, the composite clock signal outP is output. Specifically, as shown in FIG. 3, the first clock signal φ
The rising edge of the waveform of the synthesized clock signal outP is formed in synchronization with the rising edge of the waveform 0P, and the falling edge of the waveform of the synthesized clock signal outP is formed in synchronization with the second clock signal.

Such a synthesized clock signal outP is
The signal is transmitted to a circuit connected to the end of the clock wiring via the relay buffers AMP1 to AMP5. In this circuit,
Waveform rising edge trigger type flip-flop circuit SM-FF which operates synchronously with the rising edge of synthesized clock signal outP as a trigger, and waveform falling edge trigger type flip-flop circuit which operates synchronously with the falling edge of synthesized clock signal outP as a trigger A circuit MS-FF is included.

Here, when it is desired to operate a flip-flop circuit included in a circuit connected to the end of the clock wiring in synchronization with the first clock signal φ0, a flip-flop circuit SM of a waveform rising edge system is used as the flip-flop circuit. -FF is applied. When a flip-flop circuit included in a circuit connected to the end of the clock wiring is to be operated in synchronization with the first clock signal φ1, a flip-flop circuit MS-FF of a waveform falling edge trigger system is used as the flip-flop circuit. Is applied.

FIG. 2 shows a configuration example of the clock synthesizing circuit 10.

As shown in FIG. 2, the clock synthesizing circuit 10 includes a shape circuit 101 for narrowing the pulse width of the first clock signal φ0P and a second clock signal 1
An input buffer 102 for taking in P, a set / reset circuit 103 which is set by an output signal of the shape circuit 101 and is reset by an output signal of the buffer 102, and supplies an output signal of the set / reset circuit 103 to clock distribution means. Output buffer 104. By the set reset operation in the set reset circuit 103, the first clock signal φ0P
In synchronization with the rising edge of
Is formed, and the second clock signal φ1
Synthesized clock signal ou in synchronization with the falling edge of P
A falling edge of tP is formed (see FIG. 3).

FIG. 5 shows a configuration example of the set reset circuit and a truth table.

As shown in FIG. 5A, the set / reset circuit 103 is formed by combining two NOR gates 51 and 52. Set terminal S of set / reset circuit 103
Is drawn out from one input terminal of the NOR gate 52. The other input terminal of the NOR gate 52 is the NOR gate 51
Output terminal. The reset terminal R of the set reset circuit 103 is drawn out from one terminal of the NOR gate 51. The other input terminal of NOR gate 51 is coupled to the output terminal of NOR gate 52. From the output terminal of the NOR gate 51 to the output terminal Q of the set / reset circuit 103
Is pulled out.

In the above configuration, as shown in the truth table of FIG. 5B, the n-th state R of the reset terminal R
When both n and the n-th state Sn of the set terminal S are at the low (L) level, the (n + 1) -th state Qn + 1 of the output terminal Q is set to the immediately preceding output state Qn. When the n-th state Rn of the reset terminal R is set to the high (H) level, the (n + 1) -th state Qn + 1 of the output terminal Q is reset to the logical value “0”. Also, n of the set terminal S
The nth state Qn + 1 of the output terminal Q is set to the logical value “1” by setting the nth state Sn to the high level. Note that it is prohibited to set both the n-th state Rn of the reset terminal R and the n-th state Sn of the set terminal S to high level. By performing the set reset, the synthesized clock signal outP is formed.

FIG. 6A shows a configuration example of the flip-flop circuit SM-FF of the waveform rising edge type.

The rising edge type flip-flop circuit SM-FF has two input selectors 61 and 6.
3 and buffers 62, 64 and 65 are combined.
The two-input selectors 61 and 63 have two input terminals I0 and I
1 and a selection terminal SEL, and an output terminal O * (* means low active or logical inversion). Input terminal I
From 0, the data input terminal D of this waveform rising edge type flip-flop circuit SM-FF is drawn. The synthesized clock signal outP is input to the selection terminal SEL via the clock terminal CK. When the selection terminal SEL is at a high level, the input logic of the input terminal I1 is selected and output from the output terminal O *. Also, the selection terminal S
When EL is at the low level, the input logic of the input terminal I0 is selected and output from the output terminal O *. FIG. 6 (C)
Shows the logical expressions of the two-input selectors 61 and 63.

The output signal from the output terminal O * of the two-input selector 61 is transmitted to the input terminal I1 of the two-input selector 61 via the buffer 62 at the subsequent stage and to the input terminal I1 of the two-input selector 63. You. The output signal from the output terminal O * of the two-input selector 63 is
To the input terminal I0 of the two-input selector 63, and to the output terminal Q of the flip-flop circuit SM-FF of the waveform rising edge type via the buffer 65.

FIG. 6B shows a truth table of the flip-flop circuit SM-FF of the waveform rising edge type.

The input logic of the data input terminal D is output from the output terminal Q in synchronization with the rising edge of the waveform of the synthesized clock signal outP input via the clock input terminal CK. The logical output state is determined by the synthesized clock signal outP input via the clock input terminal CK.
Irrespective of the logical value of and the falling edge of the waveform.

FIG. 7A shows a configuration example of a flip-flop circuit MS-FF of the waveform falling edge type.

The waveform falling edge type flip-flop circuit MS-FF has two input selectors 71 and 7.
3 and buffers 72, 74 and 75 are combined.
The two-input selectors 71 and 73 have two input terminals I0 and I
1 and a selection terminal SEL and an output terminal O *. From the input terminal I0, the data input terminal D of the flip-flop circuit MS-FF of the waveform falling edge system is drawn out. The synthesized clock signal outP is input to the selection terminal SEL via the clock terminal CK. Select terminal SE
When L is at the high level, the input logic of the input terminal I1 is selected and output from the output terminal O *. When the selection terminal SEL is at a low level, the input logic of the input terminal I0 is selected and output from the output terminal O *. Here, the logical expressions of the two-input selectors 71 and 73 are as shown in FIG.
Are the same as the two-input selectors 61 and 63 shown in FIG.

The output signal from the output terminal O * of the two-input selector 71 is transmitted to the input terminal I1 of the two-input selector 71 and the input terminal I1 of the two-input selector 73 via the buffer 72 at the subsequent stage. You. The output signal from the output terminal O * of the two-input selector 73 is
To the input terminal I0 of the two-input selector 73, and to the output terminal Q of the waveform falling edge type flip-flop circuit MS-FF via the buffer 75.

FIG. 7B shows a truth table of the above-mentioned waveform falling edge type flip-flop circuit MS-FF.

The input logic of the data input terminal D is output from the output terminal Q in synchronization with the falling edge of the waveform of the synthesized clock signal outP input via the clock input terminal CK. The logical output state is determined by the synthesized clock signal outP input via the clock input terminal CK.
Is held irrespective of the logical value of and the rising edge of the waveform.

According to the above-described example, the following effects can be obtained.

A clock synthesizing circuit 1 for forming a synthesized clock signal outP based on a first clock signal φ0P and a second clock signal φ1P having a phase different from that of the first clock signal φ0P.
0, transmission means including a clock wiring 41 for transmitting the synthesized clock signal to each section and relay buffers AMP1 to AMP5, and a first flip-flop which operates synchronously with a rising edge of a waveform of the synthesized clock signal transmitted thereby as a trigger Integrated circuit 100 includes a flip-flop circuit SM-FF and a second flip-flop circuit MS-FF that operates synchronously with the falling edge of the waveform of the synthesized clock signal transmitted by the transmission means as a trigger. The transmission target of the transmission means is the synthesized clock signal outP. Therefore, it is not necessary to form a transmission means for each phase. That is, in order to separately transmit the first clock signal φ0P and the second clock signal φ1P, it is necessary to provide transmission means corresponding to each of the first clock signal φ0P and the second clock signal φ1P. The first clock signal φ0
By forming the synthesized clock signal outP based on P and the second clock signal φ1P, and by setting the synthesized clock signal outP as a transmission target, the transmission means may form a signal corresponding to the synthesized clock signal outP. The number of clock wirings and the number of relay buffers to be formed can be greatly reduced, thereby reducing the layout area of the clock power supply system.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, in the above-described example, the case where the clock wiring 41 is formed in an H-shape has been described, but the clock wiring 41 may have any shape.

The present invention can be applied to a case where a clock signal of a complementary level is taken in. That is, when each of the first clock signal and the second clock signal is composed of a non-inverted signal and an inverted signal, a non-inverted composite clock signal and an inverted composite clock signal are formed correspondingly. May be supplied to each unit. Also in this case, as in the case of the above-described example, the synthesized clock signal formed based on the first clock signal and the second clock signal is set as a transmission target by the transmission unit, so that the layout of the clock power supply system layout is improved. The area can be reduced.

In the above description, the case where the invention made by the present inventor is mainly applied to a microprocessor, which is the application field in which the invention is based, has been described. However, the present invention is not limited thereto, and various types of semiconductor integrated circuits may be used. It can be widely applied to circuits.

The present invention can be applied on condition that at least a clock signal is handled.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, clock synthesizing means for forming a synthetic clock signal based on a first clock signal and a second clock signal having a phase different from that of the first clock signal, and transmitting means for transmitting the synthetic clock signal to each unit. A first flip-flop circuit that operates synchronously with a rising edge of the waveform of the composite clock signal distributed by the distribution unit as a trigger, and performs a synchronous operation with a waveform falling edge of the composite clock signal transmitted by the transmission unit as a trigger By configuring the semiconductor integrated circuit including the second flip-flop circuit, the transmission target of the transmission means is a synthesized clock signal, so that it is not necessary to form a transmission means for each phase, and the clock The layout area of the power supply system can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a configuration example of a main part of a clock power supply system in a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a clock synthesis circuit included in the clock power supply system.

FIG. 3 is an operation waveform diagram of the clock synthesis circuit.

FIG. 4 is an explanatory diagram of an overall configuration example of a clock power supply system in the semiconductor integrated circuit.

FIG. 5 is a block diagram illustrating a configuration example of a set reset circuit included in the clock power supply system and an operation explanatory diagram thereof.

FIG. 6 is a block diagram showing a configuration example of a flip-flop circuit of a waveform rising edge type applied to the clock power supply system and an operation explanatory diagram thereof.

FIG. 7 is a block diagram of a configuration example of a flip-flop circuit of a waveform falling edge trigger system applied to the clock power supply system and an explanatory diagram of its operation.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 clock synthesis circuit 41 clock wiring 51, 52 OR gate 61, 63, 71, 73 2 input selection circuit 100 semiconductor integrated circuit 101 shape circuit 102 input buffer 103 set reset circuit 104 output buffer SM-FF waveform rising edge type flip-flop circuit MS-FF Waveform falling edge trigger type flip-flop circuit AMP1 to AMP5 Relay buffer

Claims (3)

[Claims] 1. A clock synthesizing means for forming a synthesized clock signal based on a first clock signal and a second clock signal having a phase different from the first clock signal, and a transmitting means for transmitting the synthesized clock signal to each unit. A first flip-flop circuit that operates synchronously with a rising edge of the waveform of the composite clock signal transmitted by the transmitting unit as a trigger, and performs a synchronous operation with a waveform falling edge of the composite clock signal transmitted by the transmitting unit as a trigger And a second flip-flop circuit. 2. A clock synthesizing means for forming a synthetic clock signal based on a first clock signal and a second clock signal having a phase different from the first clock signal, and a transmitting means for transmitting the synthetic clock signal to each unit. A first flip-flop circuit that operates synchronously with a rising edge of the waveform of the composite clock signal transmitted by the transmitting unit as a trigger, and performs a synchronous operation with a waveform falling edge of the composite clock signal transmitted by the transmitting unit as a trigger A second flip-flop circuit, wherein the clock synthesizing means forms a rising edge of the waveform of the synthesized clock signal in synchronization with a rising edge of the waveform of the first clock signal, and forms the rising edge of the waveform of the synthesized clock signal in synchronization with the second clock signal. Set reset circuit that forms the falling edge of the clock signal waveform The semiconductor integrated circuit characterized in that it comprises a. 3. A clock synthesizing means for forming a synthetic clock signal based on a first clock signal and a second clock signal having a phase different from the first clock signal, and a transmitting means for transmitting the synthetic clock signal to each unit. A first flip-flop circuit that operates synchronously with a rising edge of the waveform of the composite clock signal transmitted by the transmitting unit as a trigger, and performs a synchronous operation with a waveform falling edge of the composite clock signal transmitted by the transmitting unit as a trigger A second flip-flop circuit, wherein the clock synthesizing means includes: a shape circuit for narrowing a pulse width of the first clock signal; an input buffer for receiving the second clock signal; and an output signal from the shape circuit. The synthesized clock signal is synchronized with the rising edge of the waveform of the first clock signal. A set reset circuit that forms a rising edge of the waveform of the second clock signal and forms a falling edge of the waveform of the synthesized clock signal in synchronization with the second clock signal output from the input buffer; And an output buffer for supplying a clock signal to the transmission means.