JP2001016289A - Array transmission circuit and array reception circuit for parallel optical signal transmission - Google Patents

Abstract

PROBLEM TO BE SOLVED: To select parallel transmission of a clock signal and a data signal or parallel transmission of only the data signal. SOLUTION: In the case of parallel transmission of a data signal and a clock signal, buffers 3, 9 with a clock signal/control signal switching function distribute a clock signal from a clock signal transmission system to data signal latch means 21, 22,..., 2n, 81, 82,..., 8n to provide a latch function and the transmission system is used for a transmission system having a latch function to transmit a plurality (n) of data signals in parallel under the control of latch/ through control signal output circuits 4, 10. In the case of parallel transmission of only the data signal, the buffers 3, 9 with a clock signal/control signal switching function set the data signal latch means 21, 22,..., 2n, 81, 82,..., 8n through so as to transmit a plurality (n+1 at maximum) of the data signals in parallel under the control of the latch/through control signal output circuits 4, 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic integrated parallel optical system capable of switching between transmitting a clock signal and a data signal in parallel and transmitting only a data signal in a parallel optical signal transmission system. The present invention relates to an array transmission circuit and an array reception circuit for signal transmission.

[0002]

2. Description of the Related Art In recent years, with the progress and development of communication technology,
High-speed data transmission is required not only in the trunk system but also between or within communication devices such as transmission terminal devices and exchanges, or between computers or within computers. In such a transmission interface, particularly, an in-building interface that emphasizes transmission delay, a parallel optical transmission system that transmits a large number of signals in parallel is effective.

The parallel optical transmission system includes a method of transmitting a clock signal in parallel with a data signal, and a method of transmitting only a data signal in parallel and extracting a clock signal from the data signal. In the former method, a transmission circuit, which is a transmission interface circuit, is used to absorb a skew (difference in propagation delay) between data signals, which is a problem unique to the parallel optical transmission system.
A plurality of data signals can be latched by a clock signal transmitted in parallel in a receiving circuit to make the phases of the clock signals uniform. On the other hand, the latter method requires means for absorbing skew generated in the output signal of the receiving circuit.

Next, a monolithically integrated array transmitting / receiving circuit in a conventional parallel optical signal transmission system will be described mainly with reference to an array receiving circuit. FIG. 4 is a diagram showing an example of a conventional array receiving circuit for parallel optical signal transmission for transmitting clock signals in parallel. A circuit for transmitting data signals of a plurality of channels and a circuit for transmitting a clock signal of one channel are provided corresponding to the signal light received from the optical transmission line 6. This monolithically integrated array receiving circuit for parallel optical signal transmission includes an equalizing / amplifying means 71 for receiving and equalizing / amplifying a received data signal of an optical signal received from the transmitting circuit via the transmission line 6. , 72,... 7n, received data signal latching means 81, 82,... 8n for latching the outputs of the equalizing / amplifying means 71, 72,. 11n, a path including a buffer 7c for receiving and amplifying a clock signal of an optical signal, an output circuit 11c for outputting a clock signal from the buffer 7c, and a clock signal from the buffer 7c for each data signal. Latch means 81, 82,
.., 8n.

The array transmission circuit for transmitting the data signal and the clock signal of the optical signal to the array reception circuit has a similar parallel transmission configuration, and includes an electrical transmission data signal of a plurality of channels and a clock signal of one channel. And transmits the data signal and the clock signal of the optical signal to the transmission line 6 shown in FIG. 4 after the electrical / optical conversion.

[0006]

In a conventional array transmission / reception LSI for parallel optical signal transmission, the problem of skew between a plurality of data signals can be solved. In the case where the parallel transmission is performed, there is a problem that it is necessary to separately design and manufacture an LSI, and it is not possible to perform flexible transmission and reception in which the mode of the parallel transmission is appropriately switched and used depending on the application.

(Purpose) The present invention provides a monolithically integrated array transmission circuit for parallel optical signal transmission that can switch between parallel transmission of a clock signal and a data signal and parallel transmission of only a data signal with a simple configuration. And an array receiving circuit.

[0008]

An array transmission (reception) circuit for parallel optical signal transmission according to the present invention comprises latch means (data signal latch means 21, 22,..., 2n, 81) for latching a data signal by a clock signal. , 82,..., 8n) and a monolithically integrated array for parallel optical signal transmission (reception) having a plurality of data channels having a distribution path for distributing the clock signal to the latch means. In the circuit, buffer means (clock signal / control signal switching function buffer 3, provided in a distribution path of the clock signal to the latch means,
9) and a selection means (latch / through control signal output circuits 4 and 10) for controlling the buffer means to distribute either a clock signal or a control signal to the latch means. When distributing a clock signal to the latch means, the latch means outputs a data signal as a latch output, and when the buffer means distributes a control signal to the latch means, the latch means outputs a data signal as a through output. Features.

In the array transmission (reception) circuit, the distribution path of the clock signal has a tree-type configuration, and the buffer means is arranged at an arbitrary symmetrical branch point of the distribution path. . Also, the clock signal distribution path is characterized in that the path length from the clock channel to the latch means of each data channel is substantially equal.

Further, in the array transmission (reception) circuit, a plurality of data channels are arranged at symmetric positions with respect to the clock channel. Further, the selection means is controlled by an externally applied signal. When the control signal is distributed to the latch means and the data signal is output as a through signal, the data signal is transmitted by a clock channel.

An array transmission (reception) signal transmission circuit for parallel optical signal transmission according to the present invention comprises a plurality of data channels having latch means for outputting either a data signal latch output by a clock signal or a data signal through output. A clock channel having a distribution path for the clock signal to the latch means, buffer means provided at at least one position in the distribution path for the clock signal, and selection means for controlling the buffer means, Under control of the means, the buffer means switches and distributes a clock signal or a control signal for selecting either a latch output or a through output from the latch means, and controls the function of the latch means connected to the buffer means. Switching is characterized.

(Operation) In the case of transmitting a data signal and a clock signal in parallel, the buffer means is controlled by the selection means, and the clock signal is distributed to the latch means of the data channel from the clock signal transmission system to have a latch function. A plurality of (maximum n) data signals are transmitted in parallel as a transmission system having a latch function. When transmitting only the data signal in parallel, the control signal is distributed to the buffer means by the selection means, the latch means is provided with a through function, and a plurality of data signals (maximum n + 1 when all transmission systems are used) are transmitted in parallel. I do.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an array transmitting circuit and an array receiving circuit for transmitting parallel optical signals according to the present invention will be described.

FIG. 1 is a diagram showing a configuration of an embodiment of an array transmitting circuit and an array receiving circuit for parallel optical signal transmission according to the present invention. In the present embodiment, a monolithic integrated transmission circuit that outputs a plurality of parallel electric signals as parallel signal light to the optical transmission line 6 and a monolithic integrated reception circuit that outputs the plurality of parallel signal lights from the optical transmission line 6 as parallel electric signals And a circuit.

The monolithic integrated transmission circuit has buffers 11, 12,..., 1 for inputting a plurality of electrical data signals.
, a plurality of data signal latch means 21 having a function of latching the outputs of the buffers 11, 12,...
, 2n and a plurality of output circuits 51, 52,.
n, a buffer 1c for inputting a data signal or a clock signal, an output circuit 5c, and the clock signal or the control signal.
.., A buffer 3 with a clock signal / control signal switching function for switching and supplying to the 2n, and a latch / through control signal output circuit 4 for controlling the switching of the buffer 3 with a clock signal / control signal switching function.

The monolithically integrated array receiving circuit for parallel optical signal transmission receives the data signal light received from the array transmitting circuit via the transmission line 6 and equalizes it.
, 7n for amplifying, a function of latching the outputs of the equalization / amplification means 71, 72,..., 7n with a clock signal, and a function of making the outputs through with a control signal. Data signal latch means 81, 8
.. 8n and output means 11 for outputting latch data
, 11n, a buffer 7c for receiving and amplifying a data signal light or a clock signal light, an output circuit 11c for outputting a clock signal, and data signal latch means 81, 82,. A buffer 9 having a clock signal / control signal switching function for switching between a clock signal and a control signal, and a latch / through control signal output circuit 10 for controlling the switching of the buffer 9 having the clock signal / control signal switching function. Is done.

First, the operation of the array transmission circuit for transmitting parallel optical signals according to the present embodiment shown in FIG. 1 will be described.
First, a case where a clock signal and a data signal are transmitted in parallel will be described. In this case, the data signal and the clock signal of the electric signal input from the outside to each transmission system are input to the monolithically integrated array transmission circuit for transmitting the parallel optical signal. Data signal is buffer 1
Data signal latch means 2 via 1, 12, ..., 1n
1, 22, ..., 2n. On the other hand, buffer 1c
, The clock signal input to the output circuit 5c and the data signal latch means 21, 22,.
The buffer 3 with a clock signal / control signal switching function is provided on the distribution path, and the buffer 3 with a clock signal / control signal switching function is a latch / through control signal output circuit. 4, the data signal latch means 21, 22,.
The clock signal is set to be distributed to n.
Therefore, the data signal latch means 21, 22,.
, n receives data signals from the buffers 11, 12,..., 1n, absorbs skew by a latch operation, and outputs the data as latched data to the transmission line 6 through the output units 111, 112,.

Next, a case where only data signals are transmitted in parallel will be described. In this case, in the configuration of FIG. 1, for example, a data signal is input to all the buffers 11, 12,..., 1n and 1c. The buffer with clock signal / control signal switching function 3 controls the data signal latch means 21 and 2 under the control of the latch / through control signal output circuit 4.
2,..., 2n are set so as to distribute a control signal for not performing the latch operation. Therefore, the data signal latch means 21, 22,...
2,..., 1n have a through function. Therefore, when transmitting only the data signal,
The data signal light of the maximum (n + 1) channels including the channel of the buffer 1c can be transmitted in parallel.

Next, the array receiving circuit for parallel optical signal transmission of the present embodiment shown in FIG. 1 will be described.

When transmitting the clock signal and the data signal in parallel, the monolithically integrated array receiving circuit for parallel optical signal transmission includes the data signal light transmitted from the array transmitting circuit via the transmission line 6 and the data signal light. Clock signal light is input. The input data signal light is equalized / amplified by means 7
, 7n via the data signal latch means 8
1, 82,... 8n. On the other hand, the input clock signal light is output to the output unit 1 via the equalizing / amplifying unit 7c.
1c and the data signal latch means 8
, 8n, where the buffer 9 with the clock signal / control signal switching function is provided on the distribution path, and the buffer 9 with the clock signal / control signal switching function is latched / through. Under the control of the control signal output circuit 10, the data signal latch means 81, 8
The clock signal is set to be distributed to 2,..., 8n. Therefore, the data signal latch means 81, 8
, 8n receive the data signals from the buffers 11, 12,..., 1n, absorb the skew by the latch operation, and output as latch data via the output means 111, 112,.

When transmitting only data signals in parallel,
In the configuration shown in FIG. 1, the buffer 9 with the clock signal / control signal switching function controls the data signal latch means 81, 8 under the control of the latch / through control signal output circuit 10.
, 8n are set so as to distribute control signals for not performing the latch operation. In this case, the data signal latch means 81, 82,..., 8n have a through function for the data signals from the equalization / amplification means 71, 72,. And the data signal of the maximum (n + 1) channel is received and output.

FIG. 2 is a diagram showing the configuration of another embodiment of an array transmitting circuit and an array receiving circuit for parallel optical signal transmission according to the present invention. The blocks having the same functions as those in the embodiment shown in FIG. 1 are provided with the same photodetector array 13 as in FIG.

In this embodiment, instead of providing the electric / optical conversion means in the monolithic integrated circuit, the integrated semiconductor laser array 12 is provided at the output of the monolithic integrated transmission circuit.
In this embodiment, a photodetector array 13 is provided at the input section of the monolithic integrated receiving circuit, and an optical fiber ribbon is used as the transmission line 6. The output means 141, 142,..., 14n and 14c of the array transmitting circuit drive the respective laser elements of the integrated semiconductor laser array 12, and the preamplifier 15 of the array receiving circuit.
, 15n and 15c convert the output photocurrent of each photodetector element of the photodetector array 13 into a voltage and amplify it. Data signal latch means 21, 2
, 2n and 81, 82,..., 8n use flip-flop circuits, and when a latch operation is not performed, the clock signal /
DC from buffers 3 and 9 with control signal switching function
A (DC) voltage signal is output. The data signal latch means capable of switching between a latch function and a through function by a control signal has a flip-flop function when a clock signal is input, and is a circuit having a through function by the DC voltage signal. For example, a D-type flip-flop circuit or a master-slave type JK flip-flop circuit can be used.

FIG. 3 is a diagram showing that a D-type flip-flop circuit or the like can be applied as the data signal latch means. The data signal is input to the D terminal, and the output of the buffers 3 and 9 with the clock signal / control signal switching function is supplied to the clock signal terminal (cp). The buffers 3 and 9 with the clock signal / control signal switching function use the binary signal ("") as the clock signal cp when transmitting only the data signal in parallel.
0 "," 1 "), and outputs the clock signal cp as a DC voltage signal during the parallel transmission of the data signal and the clock signal.
By outputting one of the binary signals ("0"), the above-described function is realized.

In the embodiment of the array transmitting circuit and the array receiving circuit of the present invention, it is important that the clock signals distributed to each data channel have no delay time difference from each other. For this reason, it is preferable that the distribution path of the clock signal has a tree-type configuration as shown in FIG. Further, the buffers 3 and 9 with the clock signal / control signal switching function can be arranged at an arbitrary position, and one buffer is provided at the first symmetrical branch point of the distribution path of the clock signal having the tree structure. Or a plurality of symmetrical branch points may be provided. In particular, it is preferable that the distribution path of the clock signal is configured such that the path length from the clock channel to the latch means of each data channel is substantially equal. Further, it is preferable that the plurality of data channels be arranged symmetrically with respect to the clock channel, for example, symmetrically on both sides of the clock channel, so that the clock signal distribution path is shortened and the distribution path is symmetrical. In the above embodiment, the clock signal is distributed from the clock channel to all the data channels. However, the clock signal / control signal switching function is provided to selectively distribute the clock signal to the data channels. The attached buffers 3 and 9 can be arranged at appropriate locations. In this case, it is possible to configure an array transmitting circuit and an array receiving circuit that can simultaneously transmit a latch output, a non-latch output, and a clock signal of a data signal in parallel, and can transmit various data signals and clock signals with a simple configuration. It can be transmitted in a form.

Further, in the above-described embodiment, the data channel is provided in the data channel with respect to the clock channel in the data signal latch means 21, 22,..., 2n and 81, 82,.
In the case where the delay time in the data signal latch means cannot be ignored, a dummy circuit or the like for delay adjustment of the delay time corresponding to the delay time generated in the data signal latch means is provided in the clock channel. It can be configured to be arranged.

[0027]

As described above, according to the present invention, a function of transmitting a clock signal and a data signal in parallel and a function of transmitting only a data signal in a monolithically integrated array transmitting circuit and array receiving circuit. Can be switched by a control signal or the like. According to the present invention, there is no need to separately develop the array transmission circuit and the array reception circuit having the two functions, and a transmission / reception circuit having both functions can be realized with a simple configuration. That is,
Select the transmission mode of the data signal and the clock signal as appropriate,
An array transmitting circuit and an array receiving circuit for parallel transmission that can be flexibly switched and used according to the application can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing another embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a data signal latch unit.

FIG. 4 is a diagram showing a conventional array receiving circuit for parallel optical signal transmission.

[Explanation of symbols]

11, 12, ..., 1n Buffer for data channel of transmission circuit 1c Buffer for clock channel of transmission circuit 21, 22, ..., 2n Data signal latch means for transmission circuit 3 Clock signal / control signal switching for transmission circuit Buffer with function 4 Latch / through control signal output circuit for transmission circuit 51, 52,... 5n Output circuit for transmission circuit data channel 5c Output circuit for transmission circuit clock channel 6 Transmission lines 71, 72,. .., 8n Data signal latching means for receiving circuit 9 Buffer with clock signal / control signal switching function for receiving circuit 10 Latch / for receiving circuit Through control signal output circuit 111, 112, ..., 11n reception times 11c Output circuit for clock channel of receiving circuit 12 Integrated semiconductor laser array 141, 142,..., 14n Output means for data channel 14c Output means for clock channel 151, 152,. Preamplifier for channel 15c Preamplifier for clock channel

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K002 AA01 AA03 BA07 DA05 EA03 FA01 GA07 5K034 AA11 DD01 EE02 EE07 HH01 HH02 HH17 HH26 KK04 PP01 5K047 AA15 BB02 BB04 GG03 MM24 MM28

Claims (14)

[Claims] 1. A monolithically integrated parallel light having a plurality of data channels having latch means for latching a transmission data signal by a clock signal, and a clock channel having a distribution path for distributing the clock signal to the latch means. In an array transmission circuit for signal transmission, a buffer provided in a distribution path of a clock signal to the latch, and selection for controlling the buffer to distribute either a clock signal or a control signal to the latch. Wherein the buffer means distributes a clock signal to the latch means, the latch means outputs a transmission data signal as a latch output, and the buffer means distributes a control signal to the latch means, The means for outputting a transmission data signal as a through output. Array transmission circuit for transmission. 2. The array transmission circuit for parallel optical signal transmission according to claim 1, wherein said clock signal distribution path has a tree-type configuration. 3. The buffer according to claim 2, wherein said buffer means is arranged at any symmetric branch point of the distribution path.
4. An array transmission circuit for parallel optical signal transmission according to claim 1. 4. The clock signal distribution path according to claim 1, wherein a path length from a clock channel to said latch means of each data channel is substantially equal. An array transmission circuit for parallel optical signal transmission according to claim 1. 5. The parallel optical signal transmission according to claim 1, wherein a plurality of data channels are arranged symmetrically with respect to the clock channel. Array transmission circuit. 6. The apparatus according to claim 1, wherein said selection means is controlled by an externally applied signal.
An array transmitting circuit for transmitting a parallel optical signal according to claim 1. 7. The transmission data signal is transmitted by a clock channel when said buffer means distributes a control signal to said latch means and said latch means outputs a transmission data signal as a through output. An array transmission circuit for transmitting a parallel optical signal according to claim 6. 8. A monolithically integrated parallel light having a plurality of data channels having latch means for latching a received data signal by a clock signal, and a clock channel having a distribution path for distributing the clock signal to the latch means. In an array receiving circuit for signal transmission, buffer means provided on a distribution path of a clock signal to the latch means, and selection for controlling the buffer means to distribute either a clock signal or a control signal to the latch means. Wherein the buffer means distributes a clock signal to the latch means, the latch means outputs a received data signal as a latch output, and the buffer means distributes a control signal to the latch means, Means for outputting a received data signal as a through output. Array receiving circuit for transmission. 9. The array receiving circuit for parallel optical signal transmission according to claim 8, wherein the distribution path of the clock signal has a tree structure. 10. The array receiving circuit for parallel optical signal transmission according to claim 9, wherein said buffer means is arranged at an arbitrary symmetric branch point of a distribution path. 11. The clock signal distribution path according to claim 8, wherein the path length from the clock channel to the latch means of each data channel is substantially equal. An array receiving circuit for transmitting a parallel optical signal according to claim 11. 12. The parallel optical signal transmission according to claim 8, wherein a plurality of data channels are arranged symmetrically with respect to the clock channel. Array receiving circuit. 13. The array receiving circuit for parallel optical signal transmission according to claim 8, wherein said selection means is controlled by an externally applied signal. 14. A data signal is received by a clock channel when said buffer means distributes a control signal to said latch means and said latch means outputs a received data signal as a through output. An array transmitting circuit for transmitting a parallel optical signal according to claim 1.