JP2001015334A - Actuation detecting circuit for latching solenoid - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an actuation detecting circuit to surely make bottom detection with a simple circuit configuration composed of general purpose parts by providing a charging means which charges a capacitor until a second signal becomes a prescribed value in the circuit. SOLUTION: Immediately after a solenoid 3 is energized, the capacitor 703 of a CR delaying circuit is charged to the output voltage of a diode 705. When the current of the solenoid 3 increases and an original signal exceeds the output voltage of the diode 705 thereafter, the delaying circuit starts to follow the original signal. When the current of the solenoid further increases and the magnetic field generated by the solenoid 3 reaches the value required for moving a plunger, the delaying circuit starts the plunger and generates a bottom signal. Therefore, the delaying circuit can flexibly and inexpensively cope with various operating conditions without using the port of a microcomputer, etc., and, in addition, can prevent the occurrence of erroneous detection when the current value of the solenoid 3 is small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a latching solenoid valve that opens and closes a flow path of a fluid such as water or gas with low power consumption, and in particular, stops energization by detecting the completion of the operation of the latching solenoid. The present invention relates to a latching solenoid operation detection circuit suitable for the method of performing the above.

[0002]

2. Description of the Related Art Since a latching solenoid valve consumes power only when switching between open and closed states, it is widely used as a means for opening and closing a flow path of a fluid such as water, gas, and fuel, mainly in a battery-powered apparatus. I have. In order to make full use of the feature of low power consumption, many methods for reducing the power required for driving the latching solenoid valve have been conventionally devised. If the driving power can be reduced, for example, 1
The performance of the device can be improved, for example, a device that needs to be replaced every year can be replaced with a battery every two years. Even when an AC power supply is used, it is possible to greatly reduce the size and capacity of the power supply part by reducing the power consumption, or to guarantee the operation during a power failure in a short time.

The simplest method of driving a latching solenoid is to energize for a fixed time, and the setting of the constant energizing time includes a margin, so that there is always waste. On the other hand, the most efficient driving method is to operate the latching solenoid, that is, to detect the movement of the plunger in the solenoid and immediately stop energization. Is no waste. As a method of detecting the plunger movement, a method of detecting an inflection point of a solenoid current generated when the plunger moves is known. This method is also called “bottom detection” because the inflection point of the current takes a minimum value, that is, the bottom, and is possible only by current detection and signal processing. The signal processing method is disclosed in
No. 0-160031 has been proposed. As a conventional example,
Claims 10 to 1 of JP-A-10-160031
No. 1 is particularly relevant to the present invention, so that the content will be described in detail.

FIG. 7 is a circuit diagram showing a conventional example. 1 is a microcomputer for controlling the circuit, 2 is a battery serving as a power supply, and 3 is a solenoid portion of a latching solenoid valve, and is energized in a forward / reverse direction by a solenoid energizing circuit 4 composed of an H-type bridge circuit composed of transistors 401 to 404. Is done. When the port PO1 of the microcomputer 1 is Hi, the transistors 401 and 402 are turned on to energize the solenoid 3 in the opening direction. When the port PO2 of the microcomputer 1 is Hi, the transistors 403 and 404
Turns ON to energize the solenoid 3 in the closing direction. Reference numeral 5 denotes a detection resistor that converts a current flowing through the solenoid into a voltage.
Reference numeral 6 denotes an operation switch. For example, the switch 6 is turned on.
Then, it is conceivable that the valve is opened and the valve is closed when the switch 6 is turned off. A bottom detection circuit 7 detects an inflection point (bottom) from the voltage generated at the resistor 5 and outputs the result as a pulse to the microcomputer. The bottom detection circuit 7 includes a comparator 701 with hysteresis, a resistor 702, a capacitor 703, and a transistor 704. The resistor 702 and the capacitor 703 form a CR delay circuit.

FIG. 8 shows operation waveforms when the solenoid 3 is driven to open. When the port PO1 of the microcomputer 1 becomes Hi, the transistors 401 and 402 are turned on, and the current in the valve opening direction starts to flow through the solenoid 3. A voltage proportional to this current is generated in the detection resistor 5 and input to the bottom detection circuit 7. A comparator 70 is provided by a CR delay circuit including a resistor 702 and a capacitor 703 of the bottom detection circuit 7.
The non-inverting input of 1 is a delayed signal waveform. However, since the transistor 704 is turned on by the port PO3 of the microcomputer 1 until just before the timing when the bottom is predicted to occur from the start of energization, the transistor 704 does not function as a delay circuit during this time. For this reason, as shown in FIG. 8, when the port PO3 of the microcomputer 1 is in the Lo state, the delayed signal waveform follows the original signal waveform. When the timing at which the bottom occurs approaches, the transistor 704 is turned off by the port PO3 of the microcomputer 1, the CR delay circuit functions, and a voltage difference occurs between the original signal waveform and the delay signal waveform, and the pulse becomes the bottom detection signal. Is output. When a bottom detection pulse (falling) is input to the port PI2 of the microcomputer 1, it is determined that the valve has been opened, and the port PO1 is immediately determined.
To Lo, the energization of the solenoid 3 is terminated. In addition,
The transistor 704 is operated by the port PO3 of the microcomputer 1.
Is determined based on the experimental data.

Here, if the transistor 704 is not provided, the following problem occurs. The CR delay circuit is
Since the comparison voltage is set to detect a change in the original signal, the CR time constant needs to have a relatively large value. When the transistor 704 is not provided, as shown in FIG. 9, the delay signal cannot follow the rising speed of the current at the initial stage of the solenoid energization. Even when the bottom occurs, the delay signal remains lower than the original signal, and the bottom detection signal is not output. If the time constant of CR is reduced to avoid the situation as shown in FIG. 9, the result becomes as shown in FIG. When the solenoid current rises at the beginning of energization, the delay signal can follow the original signal, but it also follows the bottom detection, so that a voltage difference between the original signal waveform and the delayed signal waveform hardly occurs. If this voltage difference does not sufficiently exceed the offset voltage or hysteresis voltage of the comparator, a pulse that is a bottom detection signal will not be generated, or an erroneous pulse will be generated due to noise or the like.

Problems such as those shown in FIGS. 9 and 10 can be improved to some extent by setting the CR time constant to an appropriate value. However, individual differences among solenoids, water pressure used, drive voltage (particularly battery voltage), ambient temperature, Since the operation changes under various conditions such as water temperature, it is difficult to satisfy all cases with one CR time constant. The root cause is that if the optimum CR time constant is selected at the moment of bottom detection, it cannot follow the rise in current at the start of solenoid energization. As a countermeasure against this problem, in the conventional example shown in FIG. 7, the delay function is adjusted by changing the CR time constant by the transistor 704 in the first half and the second half of the solenoid energization.

[0008]

However, in the conventional method, there is no problem in operation, but there is a limitation in circuit configuration. That is, a transistor for changing the time constant of the delay circuit must be used in the circuit, and one control port such as a microcomputer must be used.

Such a circuit does not pose a problem in a system where there is a margin for a means such as integration into a dedicated IC, but when a general-purpose component is used, when there is no available port of the microcomputer, Alternatively, when the entire circuit is configured by a hard logic circuit without using a microcomputer, an attempt to implement the circuit using a relatively small-scale circuit imposes a heavy burden. In particular, since it is not always possible to add only one microcomputer port, it is necessary to change the microcomputer to a higher rank due to the lack of one port, and to add functions such as timers and A / D conversion Or the capacity of the ROM, which may lead to a significant increase in cost. Although the operation is different from the normal operation, if the solenoid is disconnected, the signal does not change at all.
When a noise or the like exceeding the hysteresis voltage is generated, a bottom detection pulse is generated, and there is a problem that it is determined that the operation is normal.

As described above, the device disclosed in Japanese Patent Application Laid-Open No. 10-160031 has sufficient performance in normal operation, and there is no major problem when it is used in a system having a sufficient circuit. There is a problem that it is not suitable for a simple configuration.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a latching solenoid operation detection circuit capable of performing reliable bottom detection with a circuit configuration using simple and general-purpose components. Is to provide.

[0012]

According to a first aspect of the present invention, a first signal proportional to an energizing current of a latching solenoid is input, and a second waveform which is a delay waveform of the first signal is provided. A delay circuit for generating a signal, and a latching solenoid operation detection circuit comprising a comparator for comparing the first signal and the second signal and outputting a third signal indicating completion of plunger movement in the latching solenoid. The delay circuit is a CR filter circuit including a capacitor and a resistor, and includes a charging unit that charges the capacitor until the second signal reaches a predetermined value. Therefore, the CR time constant is set to a relatively large value. Even so, the delay waveform follows the change in the rise at the start of energization of the solenoid current, and does not require a microcomputer port for that.

According to a second aspect of the present invention, there is provided the latching solenoid operation detecting circuit according to the first aspect, wherein the predetermined value is set to a predicted value of a first signal of a timing at which a plunger in the latching solenoid moves. Since the value is smaller than the predetermined amount, the operation of the latching solenoid is not erroneously detected when the solenoid current is small.

A third aspect of the present invention is the latching solenoid operation detecting circuit according to the second aspect, wherein the charging means is constituted by a voltage source and a first diode connecting the voltage source and the capacitor. So it is low cost.

According to a fourth aspect of the present invention, there is provided the latching solenoid operation detecting circuit according to the first aspect, wherein the predetermined value is set to a value lower than the first signal by a predetermined amount. Corresponding to

A fifth aspect of the present invention is the latching solenoid operation detection circuit according to the fourth aspect, wherein the charging means is constituted by a second diode connected in parallel with the resistor, so that it is very low. Cost.

According to a sixth aspect of the present invention, in the latching solenoid operation detecting circuit according to the first aspect, the predetermined value is a predicted value of a first signal of a timing at which a plunger in the latching solenoid moves. Value below the fixed amount,
Alternatively, since the value which is lower than the first signal by a predetermined amount is set to the higher one, the operation of both the second and fourth aspects is achieved.

According to a seventh aspect of the present invention, in the latching solenoid operation detecting circuit according to the sixth aspect, the charging means includes a voltage source; a first diode connecting the voltage source to the capacitor; The cost is low because the second diode is connected in parallel with the resistor.

An eighth aspect of the present invention is the latching solenoid operation detecting circuit according to the third and seventh aspects, wherein the voltage source outputs a voltage only while the solenoid is energized. No power consumption.

According to a ninth aspect of the present invention, in the latching solenoid operation detecting circuit according to the fifth and seventh aspects, the second diode is a Schottky barrier diode, so that a smaller signal change occurs. Can be detected.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to make the present invention easier to understand, a detailed description will be given below with reference to the drawings.

[0022]

FIG. 1 is a circuit diagram of a first embodiment of the present invention. The configuration of the bottom detection circuit 7 is different from that of FIG. The bottom detection circuit of FIG. 1 does not include the transistor 704 of FIG.
The port PO3 is also unnecessary. In FIG. 1, the solenoid 3
The resistor 706 and the resistor 707 are connected to the port PO1 of the microcomputer 1 which is set to the Hi level when the power is supplied to the open circuit, and divides the voltage of the port PO1 with respect to GND (ground, 0V). The divided voltage is connected to the capacitor 703 via the diode 705. The resistance 7
The time constants of the capacitor 02 and the capacitor 703 are set to be equal to those of the conventional example shown in FIG.

The operation of this circuit will be described with reference to FIG. 2, which is an operating voltage waveform. In FIG. 2, immediately after the start of energization of the solenoid 3, the capacitor 703 of the CR delay circuit is charged to the output voltage of the diode 705. Thereafter, when the solenoid current increases and the original signal exceeds the output voltage of the diode 705, the delay circuit starts following the original signal. At this time, the output of the comparator 701 changes from the Hi level to the Lo level as in the detection of the bottom for a short time immediately after the start of the energization of the open state. However, an error can be avoided by a simple determination process such as “the bottom detection pulse is not received for a certain period of time from the start of energization” and “the bottom detection pulse is received after the Lo level has passed for a predetermined time or longer”. FIG.
When the solenoid current further rises and the magnetic field generated by the solenoid reaches a value required for plunger movement, the plunger moves, and a bottom signal is generated. In other words, around the time when the plunger moves, the solenoid current has reached a certain large value,
The change is slowing down. Therefore, in the operation after the original signal exceeds the output voltage of the diode 705, the delay signal waveform does not largely lag behind the original signal waveform together with the short time until the bottom occurs. . When the bottom occurs, the time constant of the delay circuit is appropriately set, so that the bottom detection signal can be reliably output as in the case where the transistor 704 is ON / OFF controlled in the conventional example of FIG. .

Further, the number of components to be added is small, and there is no need to perform ON / OFF control of the transistor 704 as shown in FIG. 7, so that no burden is imposed on a microcomputer for controlling the whole. In addition, since the bottom pulse is not generated in a state where the solenoid current is small, the bottom is not erroneously detected with a current value at which the bottom should not be generated. In the conventional example, even if the solenoid is disconnected, for example, a bottom signal may be output if there is noise equal to or higher than the hysteresis voltage of the comparator. However, in the present invention, such an error cannot occur. Further, since the port PO1 of the microcomputer 1 is used as a voltage source, the resistors 706 and 707 are used.
Does not consume useless power except when the solenoid is turned on. Note that the voltage output from the diode 705 is ideally a value slightly lower than the value of the original signal when the bottom signal is generated. Actually, an appropriate value may be selected based on an experimental value in consideration of individual variations, operation variations, and the like.

Next, FIG. 3 shows a circuit diagram of a second embodiment of the present invention. The configuration of the bottom detection circuit 7 is different from that of FIG. In the bottom detection circuit of FIG. 3, the transistor 704 of FIG.
2 are connected in parallel. In FIG.
4 that does not have a microcomputer 4
The port PO3 is also unnecessary. The time constants of the resistor 702 and the capacitor 703 are set to be equal to those of the conventional example shown in FIG.

The operation will be described with reference to FIG. 4, which is an operating voltage waveform. When energization of the solenoid is started, the solenoid current increases and the original signal waveform also increases. Here, since there is no transistor 704 that invalidates the delay circuit, the delay signal waveform gradually lags behind the original signal waveform. However, when the difference between the original signal and the delay signal exceeds the forward voltage VF of the diode 708, the diode 708 turns on, charges the capacitor 702, and operates so that no more voltage difference occurs. In this way, the delay signal waveform is not largely separated from the original signal waveform despite the relatively large time constant of the delay circuit. In the vicinity of the bottom signal where the plunger operates, the rising speed of the solenoid current becomes slow, and the difference between the original signal and the delay signal decreases. When the bottom occurs, the time constant of the delay circuit is set to a relatively large value, so that the bottom signal does not excessively follow the change of the original signal, and the bottom detection signal is generated.

In the present embodiment, the only component to be added is the diode 708, and the cost is very low. Also, the first
Unlike the embodiment, it is not necessary to anticipate and set the signal voltage when the bottom signal is generated, so that it is possible to flexibly cope with the case where the type of the solenoid, the driving condition, and the like change. As can be understood from the above description, the diode 7
As the forward voltage VF of 08 is lower, the difference between the original signal and the delayed signal does not increase, and the detector circuit operates with higher sensitivity as the VF is lower. It is particularly effective in circuits with low operating voltage,
Schottky barrier diodes are suitable.

FIG. 5 shows a circuit diagram of a third embodiment of the present invention. It is provided with both the charging circuits of the first embodiment of FIG. 1 and the second embodiment of FIG. In the first embodiment, since the capacitor 703 is charged to a fixed voltage, if the charging voltage is set incorrectly, the bottom detection operation is not performed reliably. Therefore, it is necessary to set the characteristics and operating conditions of the solenoid to be used. On the other hand, in the second embodiment, if the forward voltage VF of the diode 708 is too large, the effect is not sufficient. Depending on the value of the resistor 5 and the hysteresis voltage of the comparator 701, using a Schottky diode for the diode 708 may not be sufficient. The third embodiment complements the problems of the first and second embodiments with each other. FIG. 6 shows an example of each operation.
Shown in

FIG. 6 shows a waveform when the value of the solenoid current is relatively large. For example, such a state occurs when the battery is new, or when the resistance value of the solenoid 3 is small. In FIG. 6, after the solenoid energization is started, it basically operates as shown in FIG. However, since the solenoid current has a larger value than usual, the signal rises quickly, and even if the capacitor 703 is precharged by the diode 705, the delayed signal waveform starts to be greatly delayed. However, as in the second embodiment, the diode 708 operates and the difference between the original signal and the delayed signal does not open beyond the VF of the diode 708. As described above, when the solenoid current is larger than expected, it can be handled by the diode 708. In this case, even if the VF of the diode 708 is relatively large, there is no problem because the change in current becomes large. Usually diode 705
The operation of the diode 708 is not necessary because the operation is sufficiently performed by the charging by the DC power supply.

Also, since the diode 708 acts as insurance, the output voltage of the diode 705 can be set relatively low, and bottom detection can be performed even with a solenoid that operates with a small solenoid current. Also, there are only two additional components for each of the resistor and the diode, which can be realized at low cost.

[0031]

As described above, according to the present invention, since the latching solenoid operation detection circuit including the CR delay circuit and the comparator is provided with charging means for charging the capacitor of the CR delay circuit under predetermined conditions, the microcomputer and the like are used. Without using a port, a detection circuit can be realized which is inexpensive, flexibly responds to various operating conditions, and prevents erroneous detection when the solenoid current value is small.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram showing the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is an operation waveform diagram showing the operation of the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is an operation waveform diagram showing the operation of the third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a conventional example.

FIG. 8 is an operation waveform diagram showing the operation of the conventional example.

FIG. 9 is an operation waveform diagram showing the operation of the problem to be solved by the present invention.

FIG. 10 is an operation waveform diagram showing the operation of the problem to be solved by the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... microcomputer, 2 ... battery, 3 ... solenoid, 4 ... solenoid energizing circuit, 5 ... detection resistance, 6 ... switch, 7 ... bottom detection circuit, 10 ... solenoid

Claims (9)

[Claims] A delay circuit for receiving a first signal proportional to a current flowing through a latching solenoid and for generating a second signal that is a delay waveform of the first signal; 2. A latching solenoid operation detection circuit comprising a comparator which compares the signals of No. 2 and outputs a third signal indicating the completion of the movement of the plunger in the latching solenoid, wherein the delay circuit is a CR filter circuit comprising a capacitor and a resistor, A latching solenoid operation detection circuit, comprising: charging means for charging the capacitor until the second signal reaches a predetermined value. 2. The latching solenoid operation detection circuit according to claim 1, wherein the predetermined value is a value which is lower than a predicted value of a first signal of a timing at which a plunger in the latching solenoid moves by a predetermined amount. An operation detection circuit for a latching solenoid. 3. The latching solenoid operation detection circuit according to claim 2, wherein said charging means comprises a voltage source and a first diode connecting said voltage source and said capacitor. Solenoid operation detection circuit. 4. A latching solenoid operation detection circuit according to claim 1, wherein said predetermined value is a value lower than said first signal by a predetermined amount. 5. A latching solenoid operation detection circuit according to claim 4, wherein said charging means comprises a second diode connected in parallel with said resistor. circuit. 6. The latching solenoid operation detection circuit according to claim 1, wherein the predetermined value is a value lower than a predicted value of a first signal of a timing at which a plunger in the latching solenoid moves by a predetermined amount; Alternatively, the latching solenoid operation detection circuit is a higher value of a value lower than the first signal by a predetermined amount. 7. A latching solenoid operation detection circuit according to claim 6, wherein said charging means comprises: a voltage source;
A latching solenoid operation detection circuit, comprising: a first diode connecting the voltage source to the capacitor; and a second diode connected in parallel with the resistor. 8. The latching solenoid operation detection circuit according to claim 3, wherein said voltage source is:
A latching solenoid operation detection circuit that outputs a voltage only while a latching solenoid is energized. 9. The latching solenoid operation detection circuit according to claim 5, wherein said second diode is a Schottky barrier diode. 9. The latching solenoid operation detection circuit according to claim 6, wherein said second diode is a Schottky barrier diode. .