JP2001014880A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which power consumption is reduced and operation is stabilized. SOLUTION: A memory cell array 1 is constituted by arranging a memory cell MC of a current pull-in type at an intersection part of a bit line BL and a word line WL. A row decoder 2 selecting a word line WL is an asynchronous type which is not clock-controlled, and a column decoder 3 is a synchronous type controlled by a clock ϕ11. The bit line BL is connected to a column selection gate 3b through a clamp circuit 20 consisting of NMOS transistors QN2 a gate of which is driven by bias voltage VB being lower than a power source. Bit line data are detected and amplified by a sense amplifier 5. A PMOS transistor QP being a bit line load is not connected directly, connected to a sense node SN, and connected to a bit line BL elected by a column selection gate 3b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using current draw type memory cells.

[0002]

2. Description of the Related Art FIG. 6 shows a main part of a conventional mask ROM. The memory cells MC forming the memory cell array 1 are written with data in which the magnitude of the threshold voltage corresponds to binary data by mask programming for performing selective channel ion implantation, selective contact formation, via formation, and the like. Has been. Therefore, the memory cell MC driven by the selected word line WL responds to the binary data.
The current is drawn or the current is not drawn.
Data is read by detecting the potential of the bit line BL that changes depending on whether or not the current is drawn.

A word line WL is selected by a row decoder 2 and a bit line BL is selected by a column decoder 3. The column decoder 3 includes a decoding unit 3a and a column selection gate 3b driven by the decoding unit 3a. The bit line selected by the column selection gate 3b is detected and amplified by the sense amplifier OP. In order to differentially detect bit line data, a reference bit line RBL connected to a reference memory cell RMC is provided. Reference bit line R
BL is selected at the same time as the bit line BL, and the operational amplifier O
Connected to P.

A diode-connected PMOS transistor QP is connected as a load to the bit line BL and the reference bit line RBL. At the time of data reading, the potential of the selected bit line is changed to the load PMOS transistor Q
It is determined by the balance between the charging ability by P and the current drawing ability of the memory cell. Row decoder 2 has its word line drive stage gate activated by clock φ1. The sense amplifier OP is activated by the clock φ2. These clocks φ1 and φ2 are timing clocks generated based on the system clock.

[0005]

As described above, the conventional R
In the OM, the row decoder 2 is of a synchronous type activated by a clock φ1. This is the memory cell array 1
This is to prevent a through current from occurring at the same time. That is, one of the outputs of the row decoder 2 is always at "H". Therefore, when the activation / inactivation control by the clock φ1 is not performed, one of the word lines is always in the selected state. At this time, when the selected memory cell MC is on, a current flows from the current source load transistor QP via the bit line BL. This through current can be suppressed by controlling the row decoder 2 by the clock φ1. However, as the capacity of the ROM increases, the row decoder 2
When the gate size of the word line driver increases, charging and discharging of these gates by the clock φ1 requires large power consumption.

Further, since the bit line load transistor QP is directly connected to the bit line BL, the column gate 3
A current also flows to the bit line BL not selected by b by driving the word line WL. This also causes an increase in power consumption of the ROM. Further, the conventional ROM has a configuration in which the bit line BL can rise to the power supply potential VCC due to the bit line load. As a result,
The operation of the memory cell becomes unstable because the current of the memory cell is large and the memory cell current is easily affected by the fluctuation of the power supply voltage and the process fluctuation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory device in which power consumption is reduced and operation is stabilized.

[0008]

According to the present invention, there is provided a semiconductor memory device including a memory cell array in which current-carrying memory cells are arranged at intersections of bit lines and word lines, and word lines of the memory cell array. , A synchronous column decoder for selecting a bit line of the memory cell array, a sense amplifier for detecting and amplifying data of a bit line selected by the column decoder, and a sense amplifier for the sense amplifier. A bit line load connected to a node; and a clamp circuit interposed between each column gate transistor of the column decoder and a corresponding bit line, for suppressing a rise in potential of the bit line. I do.

In the present invention, the row decoder is of an asynchronous type without clock control, and the column decoder is of a synchronous type with clock control. This eliminates the need for power consumption required for gate charging and discharging when the row decoder is clocked. Although the cam decoder is clock-controlled, the gate size of the column decoder is usually sufficiently smaller than that of the row decoder, and the power consumption here does not matter.

Conventionally, when a row decoder is always kept active as an asynchronous type, a through current in a memory cell array has been a problem. However, in the present invention, the bit line load is not directly connected to the bit line, but is connected to the sense node of the sense amplifier on the opposite side of the column decoder from the memory cell array side. For this reason, even if any one of the row decoders is always in the selected state, no current flows through the bits not selected by the column decoder. In addition, since the column decoder is clocked by using a synchronous type, there is no situation in which a bit line is always selected by one of the column decode outputs.
As described above, power consumption can be reduced.

Further, in the present invention, a clamp circuit is interposed between each bit line and the column decoder for suppressing a rise in the potential of the bit line. This eliminates an increase in current consumption and instability of operation due to the bit line rising to the power supply potential.

In the present invention, the bit line load is preferably constituted by a PMOS transistor having a gate and a drain connected to a sense node and a source connected to a power supply. The clamp circuit includes, for example, an NMOS transistor having a source connected to a bit line, a drain connected to a column gate transistor, and a gate supplied with a positive DC bias voltage lower than a power supply voltage.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a mask ROM according to an embodiment of the present invention. 1, a memory cell array 1 and a row decoder 2 and a column decoder 3 for respectively selecting a word line and a bit line thereof are provided. The address is taken in by the address buffer 4 and supplied to the row decoder 2 and the column decoder 3. The sense amplifier 5 detects and amplifies data on the bit line selected by the column decoder 3. The read data is sent to the data terminal Dou via the data buffer 6.
t.

FIG. 2 shows a specific configuration of a main part of FIG. The memory cell array 1 includes a plurality of bit lines BL (BL0, BL1,...) And word lines WL (WL0,
WL1,...) Are arranged to cross each other, and memory cells MC are arranged at the respective intersections. Memory cell MC
Is a MOS transistor to be mask-programmed in this embodiment. Specifically, the memory cell MC
Is, for example, binary data is fixed by setting a high threshold voltage state (for example, E type state) as data “0” and a low threshold voltage state (for example, D type state) as data “1”. To remember. Alternatively, a method of writing data by mask programming of contact formation and via formation may be used.

The memory cell array 1 has a reference word line R
A reference cell RMC driven by WL and outputting data to the reference bit line RBL is provided. Reference cell RM
C is designed to have a size and the like such that its current drawing capability is smaller than the “1” data state of the memory cell MC and larger than the “0” data state. As a result, the selected bit line BL is added to the reference bit line RBL.
Is generated between "0" and "1" data.

The bit line BL and the reference bit line RBL are selected by the column selection gate 3b of the column decoder 3 and connected to the sense node SN and the reference node RN of the operational amplifier OP forming the sense amplifier 5, respectively.
Between the column selection gate 3b, the bit line BL and the reference bit line RBL, a clamp circuit 20 for suppressing a rise in bit line potential to a certain level is provided. Specifically, the clamp circuit 20 is configured by an NMOS transistor QN2 inserted between each bit line BL and reference bit line RBL and the selection NMOS transistor QN11 of the column selection gate 3b. A positive bias voltage VB lower than the power supply voltage VCC is applied to the gate of the NMOS transistor QN2.

The PMOS transistor QP of the load to be connected to the bit line BL and the reference bit line RBL is not directly connected to these, and is provided outside the column select gate 3b, that is, on the sense amplifier 5 side.
N, connected to the reference node RN. The PMOS transistor QP has a gate and a drain commonly connected to the sense node SN and the reference node RN, and a source supplied with the power supply voltage VCC.

In this embodiment, the row decoder 2 is of an asynchronous type, and has word line drive stage gates G10, G
No clock is input to 11,. On the other hand, the column decoder 3 is of a synchronous type, and its decoding unit 3a has:
The column selection line drive stage gates G21, G22,.
Clock φ11 for activation. The sense amplifier 5 also has a clock φ for synchronously activating it.
12 enters.

The operation of reading data from the ROM according to this embodiment will now be described with reference to FIG. For example, it is assumed that the selected word line WL rises at time t1, and the column selection line CSL selected at time t2 rises later. Until the column selection line CSL rises, the sense node SN and the reference node RN are charged to VCC by the load PMOS transistor QP. Further, the bit line BL and the reference bit line RBL are
It is shown as being reset (precharged) to VSS.

When the selected column selection line CSL rises, the load PMOS transistor QP is connected to the selected bit line BL and connected to the memory cell MC selected by the word line WL. Thus, when the memory cell data is data "0", the potential of the bit line BL rises, and when the data is "1", the bit line potential does not rise due to current draw. In the reference bit line RBL,
It shows an intermediate change between a bit line potential change of “0” data and a bit line potential change of “1” data. Here, the rise in the potential of the bit line for the “0” data is limited by the clamping NMOS transistor QN2. That is, when the threshold voltage of the NMOS transistor QN2 is set to Vth and the bit line potential rises to VB-Vth, the NMOS transistor QN2 is turned off and does not further rise.

The sense node SN and the reference node RN are:
At the rise of the column selection line CSL, the bit line BL and the reference bit line RBL are once drawn and undershoot. The sense node SN connected to the "0" data bit line returns to VCC, and the sense node SN connected to the "1" data stabilizes at a lower potential on the bit line BL than the "0" data. The reference node RN is the sense node SN
5 shows an intermediate potential change between the potential changes in the case of “0” and “1”. Then, at time t3 when the potential difference between the sense node SN and the reference node RN reaches a certain level, the sense output SA
OUT is obtained. After the column selection line CSL becomes “L”, the bit line BL is
And the reference bit line RBL converges to VSS.

According to this embodiment, the row decoder 2
Since no clock is used, unnecessary power that has conventionally been consumed when clock-controlling the gates of many row decoders is eliminated. Since the row decoder is not clocked, one of the word lines is always in the selected state. However, in this embodiment, the bit line load is not directly connected to the bit line, and is applied only to the bit line selected by the column gate. A bit line load is connected. Therefore,
As long as the column gate is not turned on, current does not flow from the bit line load to the bit line, and unnecessary current consumption in the memory cell array is suppressed.

The charging potential of the bit line is suppressed to a level lower than the power supply voltage by a clamp circuit. As a result, the current in the memory cell is reduced, and the influence on the memory cell current due to the power supply voltage and the variation in the process is relatively reduced, so that a stable data reading operation can be performed.

The present invention is not limited to the above embodiment.
For example, the memory cell may be one that stores binary data depending on whether or not current is drawn. Therefore, an SRAM using a dual-port SRAM cell as shown in FIG.
Alternatively, the present invention can be similarly applied to a DRAM using a three-transistor DRAM cell as shown in FIG.

[0025]

As described above, in the semiconductor memory device according to the present invention, the bit line load is provided outside the column selection gate and selectively connected to the bit line, and the row decoder does not perform clock control. By controlling the clock of the column decoder, power consumption can be reduced. Further, a clamp circuit is provided between the bit line and the column selection gate to suppress a rise in the potential of the bit line, thereby stabilizing the operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a block configuration of a mask ROM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of a main part of the mask ROM of the embodiment.

FIG. 3 is a timing chart for explaining the operation of the mask ROM of the embodiment.

FIG. 4 shows a dual port S used in another embodiment.
FIG. 3 is a diagram illustrating a RAM cell.

FIG. 5 shows a three-transistor D used in another embodiment.
FIG. 3 is a diagram illustrating a RAM cell.

FIG. 6 is a diagram showing a configuration of a conventional mask ROM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... memory cell array, 2 ... row decoder, 3 ... column decoder, 4 ... address buffer, 5 ... sense amplifier,
6 data buffer, 20 clamp circuit, MC memory cell, RMC reference cell, QP PMOS transistor (bit line load).

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masayuki Koizumi F-term (reference) 5B003 AA05 AB03 AC07 AC08 AD02 AD05 5B015 HH04 JJ04 in the Toshiba Microelectronics Center, No. 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa JJ12 KA09 KA32 KA35 KB13 KB44 KB50 QQ03

Claims (3)

[Claims] 1. A memory cell array configured by arranging a current drawing type memory cell at an intersection of a bit line and a word line, an asynchronous row decoder for selecting a word line of the memory cell array, and the memory cell array A synchronous column decoder for selecting a bit line of the same; a sense amplifier for detecting and amplifying data of the bit line selected by the column decoder; a bit line load connected to a sense node of the sense amplifier; And a clamp circuit interposed between each of the column gate transistors and the corresponding bit line for suppressing a rise in the potential of the bit line. 2. The bit line load is a PMOS transistor having a gate and a drain connected to a sense node and a source connected to a power supply.
13. The semiconductor memory device according to claim 1. 3. The clamp circuit is an NMOS transistor having a source connected to a bit line, a drain connected to a column gate transistor, and a gate supplied with a positive DC bias voltage lower than a power supply voltage. The semiconductor memory device according to claim 1.