JP2001008214A - Video signal hierarchizing/encoding device and video signal hierarchizing/decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform highly efficient hierarchization and encoding of a video signal by providing only one motion detector by using a detected motion vector in encoding of a differential signal with high resolution, when a video signal with low resolution is encoded and including no piece of motion vector information in a second compressed stream. SOLUTION: The inputted video signal is outputted by converting it into the video signal with low resolution by a first resolution converter 101 and is recorded in an image memory 104 as a reference frame video signal by the motion detector 102. Motions in units of macro blocks are detected from a reference frame video signal and reproduced video signal of the reference frame and an encoded and decoded reproduced video signal of a reference frame. For example, when the inputted signal is defined as 1080p and the video signal with low resolution converted by the first resolution converter 101 is 720p, the need of reception of both streams is eliminated by imparting no MV to 1080p and imparting MV only to 720p, encoding of both 720p and 1080p is enabled by providing the motion detector 102 only for 720p and an advantageous effect is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a hierarchical coding system such as a spatial scalability profile which is a hierarchical coding in a spatial axis direction standardized by MPEG which is a standardization organization of a video signal compression system. .

[0002]

2. Description of the Related Art An encoding apparatus of a spatial scalability profile, which is hierarchical encoding in the spatial axis direction standardized by MPEG, which is a conventional video signal hierarchical encoding apparatus, is a conventional example.

A conventional video signal hierarchical coding apparatus and a conventional video signal hierarchical decoding apparatus will be described below with reference to FIGS.

First, a conventional video signal hierarchical coding apparatus will be described with reference to FIG. In FIG. 7, 1001
Is a first resolution converter, 1002 is a motion detector, 100
3 is an image memory, 1004 is a motion compensator, 1005 is D
CT unit, 1006 is a quantizer, 1007 is an inverse quantizer,
1008 is an IDCT device, 1009 is a motion compensator, 101
0 is a variable length encoder, 1011 is a second resolution converter,
1012 is a motion detector, 1013 is an image memory, 101
4 is a motion compensator, 1015 is a DCT device, 1016 is a quantizer, 1017 is an inverse quantizer, 1018 is an IDCT device,
1019 is a motion compensator and 1020 is a variable length encoder.

The feature of this video signal hierarchical coding apparatus is as follows.
A first compressed stream and a second compressed stream are to be generated. The reason why the two types of compressed streams are generated is to enable a decoder sold in the past or a decoder with low performance to decode a video signal. That is, a compressed stream that can be decoded even by a decoder having a low capability such that a decoder having no ability to decode a high-resolution video signal can decode a compressed stream generated by the variable-length encoder 1010. To generate two compressed streams in order to output.

An input video signal is supplied to a first resolution converter 10.
01 is converted into a video signal having a lower resolution than the input video signal.

[0007] The motion detector 1002 records the video signal output from the first resolution converter 1001 in the image memory 1003. The motion detector 1002 compares the coded frame with the video signal of the reference frame recorded in the image memory 1003. A macroblock unit (16 pixels × 16 pixels in a screen in a luminance signal) is used by using a reproduced video signal of a coded and decoded reference frame.
(A block of 16 lines) is detected.

[0008] The motion compensator 1004 outputs a difference signal between the video signal of the coded frame and the reproduced video signal of the reference frame detected by the motion detector 1002 in macroblock units.

The DCT unit 1005 includes a motion compensator 1004
Is subjected to DCT for each block (block of 8 pixels × 8 lines in the screen) and output.

[0010] The quantizer 1006 quantizes the DCT coefficient and outputs it.

The inverse quantizer 1007 includes a quantizer 1006
Inversely quantizes the coefficient quantized by and outputs the result.

The IDCT unit 1008 includes an inverse quantizer 100
7 is subjected to inverse DCT and output.

The motion compensator 1009 is an IDCT unit 100
8 and the reproduced video signal of the reference frame motion-compensated by the motion compensator 1004 are added to generate a reproduced video signal, which is stored in the image memory 1003.

The variable length encoder 1010 includes a quantizer 10
Variable-length coding is performed on a predetermined flag including an output 06 and a motion vector, and then output.

The second resolution converter 1011 converts the resolution of the reproduced video signal output from the motion compensator 1009 to the same resolution as that of the input video signal, and stores it in the image memory 1013.

A motion detector 1012 records an input video signal in an image memory 1013, and further includes a coded frame, a video signal of a reference frame recorded in the image memory 1013, and a video signal of a reference frame already coded and decoded. The motion of each macro block is detected using the reproduced video signal and a reference frame which is a video signal at the same time in the low resolution signal output from the second resolution converter 1011.

The motion compensator 1014 outputs a difference signal between the video signal of the coded frame and the video signal of the reference frame detected by the motion detector 1012 in macroblock units.

The DCT unit 1015 includes a motion compensator 1019.
Are subjected to DCT for each block and output.

The quantizer 1016 quantizes the DCT coefficient and outputs the result.

The inverse quantizer 1017 includes a quantizer 1016
Inversely quantizes the coefficient quantized by and outputs the result.

The IDCT unit 1018 includes an inverse quantizer 101
7 is subjected to inverse DCT and output.

The motion compensator 1019 is an IDCT unit 101
8 and the reproduced video signal of the reference frame motion-compensated by the motion compensator 1014 are added to generate a reproduced video signal, which is stored in the image memory 1013.

The variable length encoder 1020 includes a quantizer 10
A predetermined flag including the output of 16 and a motion vector is subjected to variable-length coding and output.

Next, a video signal hierarchical decoding apparatus will be described with reference to FIG. In FIG. 8, reference numeral 1021 denotes a variable length decoder, 1022 denotes an inverse quantizer, and 1023 denotes an IDC.
T unit, 1024 is a motion compensator, 1025 is an image memory,
1026 is a second resolution converter, 1027 is a variable length decoder, 1028 is an inverse quantizer, 1029 is an IDCT unit,
1030 is a motion compensator, 1031 is an image memory.

The variable length decoder 1021 to which the first compressed stream has been input performs a predetermined decoding and outputs a motion vector and a decoded signal. The inverse quantizer 1022 inversely quantizes the decoded signal at a predetermined quantization step and outputs a DCT coefficient. The IDCT unit 1023 converts the DCT coefficient into IDC
T. The motion compensator 1024 adds the output of the IDCT unit 1023 and the video signal of the reference frame specified by the motion vector to generate a reproduced video signal, and
025.

The second resolution converter 1026 converts the resolution of the reproduced video signal to a predetermined resolution and converts the resolution into a predetermined resolution.
1 is stored.

The variable length decoder 1027 to which the second compressed stream has been input performs a predetermined decoding and outputs a motion vector and a decoded signal. The inverse quantizer 1028 inversely quantizes the decoded signal at a predetermined quantization step and outputs a DCT coefficient. The IDCT unit 1029 converts the DCT coefficient into IDC
T. The motion compensator 1030 adds the output of the IDCT unit 1024 and the video signal of the reference frame specified by the motion vector to generate a reproduced video signal, and
031.

[0028]

However, in the conventional video signal hierarchical coding apparatus, two motion detectors (1) are used.
002, 1012), the encoding device is complicated, and the first compressed stream, the second compressed stream, and the second compressed stream can be decoded if only the first compressed stream is received. Have a motion vector. For this reason, there are problems that the redundancy of the two compressed streams is high, and that the distortion is crossed out because the coding unit on the screen is different between the input video signal and the low-resolution video signal.

[0029]

A video signal hierarchical coding apparatus according to a first aspect of the present invention uses a motion vector detected in a first high efficiency coding of a low resolution second video signal. , A difference signal between a first video signal generated from a decoded video signal of the first video signal and a second video signal and a third video signal having the same resolution as that of the first video signal is obtained by highly efficient encoding using motion compensation. A second high-efficiency encoding means for outputting a second compressed stream.
In the video signal hierarchical coding apparatus according to the second invention of the present invention, the number of samples in the horizontal direction in the frame from the high resolution first video signal which is the input video signal to the first video signal is N2. / N1 and the number of lines in the vertical direction is L2 / L1 (N
A first resolution conversion means for generating a low-resolution second video signal of (1, N2, L1, L2 is a natural number); a second video signal having motion compensation and M × M (M is a natural number) orthogonal; First high-efficiency encoding means for outputting a high-efficiency encoded first compressed stream using transformation, and a first video generated from a decoded video signal of the first video signal and the second video signal The difference signal between the signal and the third video signal having the same resolution is subjected to high efficiency coding using motion compensation and orthogonal transformation of (M × N1 / N2) × (M × L1 / L2) (M is a natural number). And a second high-efficiency encoding means for outputting a second compressed stream. The video signal hierarchical encoding apparatus according to the third invention of the present invention is characterized in that The first video signal of the resolution is compared with the first video signal, and the horizontal sampling within the frame is performed. A first video signal for generating a low-resolution second video signal in which the number of lines is N2 / N1 and the number of lines in the vertical direction is L2 / L1 (N1, N2, L1, and L2 are natural numbers)
And the second video signal is subjected to motion compensation and M ×
First high-efficiency encoding means for outputting a first compression stream which has been subjected to high-efficiency encoding using M (M is a natural number) orthogonal transform, and decoded video signals of the first video signal and the second video signal Motion compensation using a motion vector detected in a first high-efficiency encoding of a low-resolution second video signal as a difference signal between the first video signal generated from the first video signal and the third video signal having the same resolution. And (M × N1 / N2) × (M × L1 / L
2) It is characterized by comprising a second high-efficiency encoding means for outputting a high-efficiency encoded second compressed stream using (M is a natural number) orthogonal transform. According to a fourth aspect of the present invention, there is provided a video signal hierarchical decoding apparatus according to any one of claims 1, 3 and 4, wherein the first and second compressed streams are input. , Decoding a motion vector from the first compressed stream, decoding the second compressed stream using the motion vector, and outputting a decoded signal of the differential signal.
High-efficiency encoding means, and a decoded video signal of the second video signal obtained by decoding the first compressed stream into a third video signal having the same resolution as that of the first video signal. And adding means for generating a decoded video signal of the first video signal by adding
A video signal hierarchical decoding device according to a fifth aspect of the present invention is the video signal hierarchical decoding device according to claims 1, 3 and 4, wherein the video signal hierarchical decoding device decodes the first compressed stream. A third video signal having the same resolution as the first video signal is generated from the decoded video signal of the second video signal, and a motion vector decoded from the first compressed stream and the second compressed stream are input; The second compressed stream is decoded using the motion vector in the first compressed stream, a decoded signal of the difference signal is output, and the decoded video signal of the third video signal and the decoded signal of the difference signal are added. A video signal hierarchical decoding apparatus according to a sixth aspect of the present invention is characterized by comprising an adding means for generating a decoded video signal of the video signal. An apparatus, wherein the first First high-efficiency decoding means for decoding the compressed stream using M × M (M is a natural number) orthogonal transform and outputting a decoded video signal of a second video signal; and a decoded video signal of the second video signal And a second resolution conversion means for generating a third video signal having the same resolution as the first video signal from the first video signal, and converting the second compressed stream to (M × N1 / N2) × (M ×
(L1 / L2) orthogonal second transform, and outputs the decoded signal of the differential signal.
And an adder for adding the decoded video signal and the decoded signal of the difference signal to generate a decoded video signal of the first video signal.

[0030]

(Embodiment 1) An embodiment of the first invention of the present invention will be described below with reference to FIG.

In FIG. 1, 101 is a first resolution converter, 102 is a motion detector, 103 is a motion compensator, 104
Is an image memory, 105 is a DCT unit, 106 is a quantizer,
107 is an inverse quantizer, 108 is an IDCT unit, 109 is a motion compensator, 110 is a variable length encoder, 111 is a second resolution converter, 112 is a difference signal generator, 113 is a motion vector converter, 114 Is an image memory, 115 is a motion compensator, 116 is a DCT device, 117 is a quantizer, 118 is an inverse quantizer, 119 is an IDCT device, 120 is a motion compensator,
121 is a variable length encoder.

The input video signal is supplied to the first resolution converter 10
1 converts the input video signal into a lower resolution video signal.

The motion detector 102 records the video signal output from the resolution converter 101 in the image memory 104, and encodes the encoded frame and the video signal of the reference frame recorded in the image memory 104. The motion of each macro block (a block of 16 pixels × 16 lines in the screen in the luminance signal) is detected from the decoded reproduced video signal of the reference frame.

The motion compensator 103 outputs a difference signal between the video signal of the coded frame and the reproduced video signal of the reference frame detected by the motion detector 102 in macroblock units.

The DCT unit 105 DCTs the difference signal output from the motion compensator 103 for each block (block of 8 pixels × 8 lines in the screen) and outputs the result.

The quantizer 106 quantizes the DCT coefficient and outputs the result.

The inverse quantizer 107 inversely quantizes the coefficient quantized by the quantizer 106 and outputs the result.

The IDCT unit 108 performs an inverse DCT on the output of the inverse quantizer 107 and outputs the result.

The motion compensator 109 generates a reproduced video signal by adding the output of the IDCT unit 108 and the reproduced video signal of the reference frame motion-compensated by the motion compensator 103, and stores the reproduced video signal in the image memory 104.

The variable-length coder 110 includes a quantizer 106
And a predetermined flag including a motion vector is variable-length coded and output.

The second resolution converter 111 converts the resolution of the reproduced video signal output from the motion compensator 109 and outputs it at the same resolution as the input video signal.

The difference signal generator 112 generates and outputs a difference signal from the input video signal and the output of the second resolution converter 111.

The motion vector converter 113 uses the motion vector output from the motion detector 102 to convert the reference image for the difference signal into a coded frame and a reference frame in the image memory 114 which has already been coded and decoded. Are output in units of macroblocks from the reproduced difference signal.

The motion compensator 115 outputs the difference signal between the coded frame and the signal from the image memory 114 in macroblock units.

The DCT unit 116 subjects the difference signal of the output of the motion compensator 115 to DCT for each block and outputs the result.

The quantizer 117 quantizes the DCT coefficient and outputs it.

The inverse quantizer 118 inversely quantizes the coefficient quantized by the quantizer 117 and outputs the result.

The IDCT unit 119 performs an inverse DCT on the output of the inverse quantizer 118 and outputs the result.

The motion compensator 120 generates a reproduction difference signal by adding the output of the IDCT unit 119 and the reproduction difference signal of the reference frame motion-compensated by the motion compensator 115, and stores the reproduction difference signal in the image memory 114.

The variable length encoder 121 has a quantizer 117
And a predetermined flag that does not include a motion vector is variable-length coded and output.

As an example, consider a case where the input video signal is 1080p and the low-resolution video signal converted from the input video signal by the first resolution converter 101 is 720p, and MV is not added to 1080p. , 720p
MV is added only to. In this way, it is not necessary to receive both streams,
If there is a motion detector only for 0p, 720p and 1
080p can be encoded.

When the input video signal is a 1080p video signal and the low-resolution video signal is a 720p video signal, the motion vector converter 113 converts the motion vector output from the motion detector 102 into three horizontal and vertical motion vectors. / 2 times. The reason for increasing by 3/2 is that the sampling ratio of the 720p video signal and the 1080p video signal is 2: 3 in both the horizontal and vertical directions.

An example of the first compressed stream corresponds to an MPEG elementary video stream. The syntax of the second compressed stream is the same as that of the elementary video stream in MPEG, but the content is a component of the high-resolution video signal not included in the first compressed stream (high-resolution video signal). And a differential signal of a signal obtained by decoding the first compressed stream and converting the resolution.

Although the first resolution converter 101 and the second resolution converter 111 have an inverse conversion relationship, the characteristics of the filter used can be changed. The same is
The input video signal format of the first resolution converter and the second
The output video signal format of the resolution converter, and
The output video signal format of the first resolution converter and the second
Is the input video signal format of the resolution converter.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to FIG.

In FIG. 2, the elements having the same numbers as those in FIG. 201 is a motion detector, 202 is a DCT unit, and 203 is an IDCT unit.

The input video signal is supplied to the first resolution converter 10
1 converts the input video signal into a lower resolution video signal. Here, for the sake of simplicity, it is assumed that the resolution is converted to 解像度 in both the horizontal and vertical directions.

The motion detector 102 records the video signal output from the resolution converter 101 in the image memory 104, and encodes the encoded frame and the video signal of the reference frame recorded in the image memory 104. The motion of each macro block (a block of 16 pixels × 16 lines in the screen in the luminance signal) is detected from the decoded reproduced video signal of the reference frame.

The motion compensator 103 outputs a difference signal between the video signal of the coded frame and the reproduced video signal of the reference frame detected by the motion detector 102 in macroblock units.

The DCT unit 105 performs DCT on the difference signal output from the motion compensator 103 for each block (8 pixels × 8 lines in a screen) and outputs the result.

The quantizer 106 quantizes the DCT coefficient and outputs it.

The inverse quantizer 107 inversely quantizes the coefficient quantized by the quantizer 106 and outputs the result.

The IDCT unit 108 performs an inverse DCT on the output of the inverse quantizer 107 and outputs the result.

The motion compensator 109 generates a reproduced video signal by adding the output of the IDCT unit 108 and the reproduced video signal of the reference frame motion-compensated by the motion compensator 103, and stores the reproduced video signal in the image memory 104.

The variable length coder 110 includes a quantizer 106
And a predetermined flag including a motion vector is variable-length coded and output.

The second resolution converter 111 converts the resolution of the reproduced video signal output from the motion compensator 109 to the same resolution as the input video signal and outputs the same.

The difference signal generator 112 generates and outputs a difference signal from the input video signal and the output of the second resolution converter 111.

The motion detector 201 records the video signal of the encoded frame of the input video signal and the difference signal in the image memory 114, and calculates the encoded frame and the video signal of the reference frame recorded in the image memory 104. A motion is detected in units of macro blocks (blocks of 32 pixels × 32 lines in a screen in a luminance signal).

The motion compensator 115 outputs the difference signal between the coded frame and the signal from the image memory 114 on a macroblock basis.

The DCT unit 202 performs DCT on the difference signal output from the motion compensator 115 for each block (a block of 16 pixels × 16 lines in the screen) and outputs the result.

The quantizer 117 quantizes the DCT coefficient and outputs it.

The inverse quantizer 118 inversely quantizes the coefficient quantized by the quantizer 117 and outputs the result.

The IDCT unit 203 performs an inverse DCT on the output of the inverse quantizer 118 and outputs the result.

The motion compensator 120 adds the output of the IDCT unit 203 and the reproduction difference signal of the reference frame motion-compensated by the motion compensator 115 to generate a reproduction difference signal, and stores it in the image memory 114.

The variable length encoder 121 has a quantizer 117
And a predetermined flag including a motion vector is variable-length coded and output.

The horizontal and vertical resolution conversion ratios are both 1
The ratio of / 2 may be an arbitrary ratio independently of horizontal and vertical. In this case, the horizontal and vertical ratios are N2 / N1 and N2 / N1, respectively.
L2 / L1 (N1, N2, L1, L2 are natural numbers)
DCT performed by DCT unit 105 and IDCT unit 108
And its inverse transform need not be in units of 8 pixels × 8 lines, and in this case M pixels × M lines
The DCT performed by the T unit 202 and the IDCT unit 203 and the inverse transform thereof are (M × N1 / N2) pixels × (M × L1 / L).
2) A line, and the size of the macroblock in this case is a set of an integer multiple of M pixels × M lines in the screen in the luminance signal in the first high-efficiency encoding means.
In the high-efficiency encoding means, a set of (M × N1 / N2) pixels × (M × L1 / L2) lines in the screen in the luminance signal may be an integral multiple.

As an example, if the input video signal is 1080
If the p-video signal is a 720p video signal and the low-resolution video signal is a 720p video signal, N1 = 3, N2 = 2, L1 = 3, and L2 = 2, and each of the DCT unit 105 and the IDCT unit 108 performs Assuming that 8 × 8 DCT and its inverse transform are performed, what is performed in each of DCT unit 202 and IDCT unit 203 is 12 × 12 DCT and its inverse transform.

(Embodiment 3) The third embodiment of the present invention will be described below with reference to FIG.

In FIG. 3, components having the same numbers as those in FIGS.

The input video signal is supplied to the first resolution converter 10
1 converts the input video signal into a lower resolution video signal. Here, for the sake of simplicity, it is assumed that the resolution is converted to 解像度 in both the horizontal and vertical directions.

The motion detector 102 records the video signal output from the resolution converter 101 in the image memory 104, and encodes the encoded frame and the video signal of the reference frame recorded in the image memory 104. The motion of each macro block (a block of 16 pixels × 16 lines in the screen in the luminance signal) is detected from the decoded reproduced video signal of the reference frame.

The motion compensator 103 outputs a difference signal between the video signal of the coded frame and the reproduced video signal of the reference frame detected by the motion detector 102 in macroblock units.

The DCT unit 105 performs DCT on the difference signal output from the motion compensator 103 for each block (a block of 8 pixels × 8 lines in the screen) and outputs the result.

The quantizer 106 quantizes the DCT coefficient and outputs it.

The inverse quantizer 107 inversely quantizes the coefficient quantized by the quantizer 106 and outputs the result.

The IDCT unit 108 performs an inverse DCT on the output of the inverse quantizer 107 and outputs the result.

The motion compensator 109 generates a reproduced video signal by adding the output of the IDCT unit 108 and the reproduced video signal of the reference frame motion-compensated by the motion compensator 103, and stores the reproduced video signal in the image memory 104.

The variable length coder 110 is used to
And a predetermined flag including a motion vector is variable-length coded and output.

The second resolution converter 111 converts the resolution of the reproduced video signal output from the motion compensator 109 and outputs it at the same resolution as the input video signal.

The difference signal generator 112 generates and outputs a difference signal from the input video signal and the output of the second resolution converter 111.

The motion vector converter 113 reproduces the reference image for the difference signal by using the motion vector output from the motion detector 102 by doubling it in both the horizontal and vertical directions. From the difference signal, a macro block unit (32 pixels × 3 in the screen in the luminance signal)
2 blocks).

The motion compensator 115 outputs the difference signal between the coded frame and the signal from the image memory 114 on a macroblock basis.

The DCT unit 202 performs DCT on the difference signal output from the motion compensator 115 for each block (a block of 16 pixels × 16 lines in the screen) and outputs the result.

The quantizer 117 quantizes the DCT coefficient and outputs it.

The inverse quantizer 118 inversely quantizes the coefficient quantized by the quantizer 117 and outputs the result.

The IDCT unit 203 performs an inverse DCT on the output of the inverse quantizer 118 and outputs the result.

The motion compensator 120 adds the output of the IDCT unit 203 and the reproduction difference signal of the reference frame motion-compensated by the motion compensator 115 to generate a reproduction difference signal, and stores it in the image memory 114.

The variable length encoder 121 has a quantizer 117
And a predetermined flag that does not include a motion vector is variable-length coded and output.

Note that both the horizontal and vertical resolution conversion ratios are 1
The ratio of / 2 may be an arbitrary ratio independently of horizontal and vertical. In this case, the horizontal and vertical ratios are N2 / N1 and N2 / N1, respectively.
L2 / L1 (N1, N2, L1, L2 are natural numbers)
DCT performed by DCT unit 105 and IDCT unit 108
And its inverse transform need not be in units of 8 pixels × 8 lines, and in this case M pixels × M lines
The DCT performed by the T unit 202 and the IDCT unit 203 and the inverse transform thereof are (M × N1 / N2) pixels × (M × L1 / L).
2) A line, and the size of the macroblock in this case is a set of an integer multiple of M pixels × M lines in the screen in the luminance signal in the first high-efficiency encoding means.
In the high-efficiency encoding means, a set of (M × N1 / N2) pixels × (M × L1 / L2) lines in the screen in the luminance signal may be an integral multiple.

Also, as an example, if the input video signal is 1080
If the video signal is a p-video signal and the low-resolution video signal is a 720p video signal, the motion vector converter 113 uses the motion vector output from the motion detector 102 by multiplying it by 3/2 both horizontally and vertically, and uses N1. = 3, N2 = 2, L1 = 3, L
If 2 = 2 and the DCT unit 105 and the IDCT unit 108 perform 8 × 8 DCT and its inverse transform, respectively, the DCT unit 202 and the IDCT unit 203 perform 12 DCT of × 12 and its inverse transform.

(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to FIG.

In FIG. 4, reference numeral 401 denotes a variable length decoder;
402 is an inverse quantizer, 403 is an IDCT unit, 404 is a motion compensator, 405 is an image memory, 406 is a second resolution converter, 407 is a variable length decoder, 408 is an inverse quantizer, and 409 is an IDCT. Unit, 410 is a motion compensator, 411
Is an image memory, 412 is a motion vector decoder, 413
Is an adder.

The variable length decoder 401 to which the first compressed stream has been input performs a predetermined decoding and outputs a motion vector and a decoded signal. The inverse quantizer 402 inversely quantizes the decoded signal in a predetermined quantization step and outputs a DCT coefficient. The IDCT unit 403 performs IDCT on the DCT coefficient. The motion compensator 404 generates a reproduced video signal by adding the output of the IDCT unit 403 and the reproduced video signal of the reference frame specified by the motion vector, and generates a reproduced video signal.
To memorize.

The second resolution converter 406 converts the resolution of the reproduced video signal and outputs it.

The variable length decoder 407 to which the second compressed stream is input performs a predetermined decoding and outputs a decoded signal. The inverse quantizer 408 inversely quantizes the decoded signal at a predetermined quantization step and outputs a DCT coefficient. IDCT
The unit 409 performs IDCT on the DCT coefficient. The motion vector decoder 412 decodes the motion vector from the first compressed stream and outputs a motion vector for the second compressed stream by a predetermined conversion. The motion compensator 410 calculates I
The output of the DCT unit 409 and the reproduced difference signal of the reference frame specified by the motion vector output from the motion vector decoder 412 are added to generate a reproduced difference signal, which is stored in the image memory 411.

An adder 413 adds the reproduced difference signal and the reproduced video signal output from the second resolution converter 406 to generate a reproduced video signal of the first video signal.

Note that the horizontal / vertical ratios are respectively N2 / N
1, L2 / L1 (N1, N2, L1, and L2 are natural numbers), and the inverse transform of the DCT performed by the IDCT unit 403 is M
× MDCT, the DCT performed by the IDCT unit 209
The inverse transform of CT is (M × N1 / N2) × (M × L1 / L
2).

As an example, if the input video signal is 1080
When the low-resolution video signal is a 720p video signal and the low-resolution video signal is a 720p video signal, the motion vector decoder 412 converts the motion vector in the first compressed stream into three horizontal and vertical motion vectors.
/ 2 times, N1 = 3, N2 = 2, L1 = 3, L2 =
2 and the operation performed by the IDCT unit 403 is 8 × 8
And the inverse transform thereof, the IDCT unit 40
What is performed at 9 can be a 12 × 12 DCT and its inverse transform.

(Embodiment 5) A fifth embodiment of the present invention will be described below with reference to FIG.

In FIG. 5, those having the same numbers as those in FIG. 4 perform the same operations, and thus the description thereof is omitted. Reference numeral 501 denotes a motion vector converter.

The variable length decoder 401 to which the first compressed stream is input performs a predetermined decoding and outputs a motion vector and a decoded signal. The inverse quantizer 402 inversely quantizes the decoded signal in a predetermined quantization step and outputs a DCT coefficient. The IDCT unit 403 performs IDCT on the DCT coefficient. The motion compensator 404 generates a reproduced video signal by adding the output of the IDCT unit 403 and the reproduced video signal of the reference frame specified by the motion vector, and generates a reproduced video signal.
To memorize.

The second resolution converter 406 converts the resolution of the reproduced video signal and outputs it.

The variable length decoder 407, to which the second compressed stream has been input, performs a predetermined decoding and outputs a decoded signal. The inverse quantizer 408 inversely quantizes the decoded signal at a predetermined quantization step and outputs a DCT coefficient. IDCT
The unit 409 performs IDCT on the DCT coefficient. The motion vector converter 501 outputs a motion vector for the second compressed stream by performing a predetermined conversion on the motion vector output from the variable length decoder 401. The motion compensator 410 has an ID
The output of the CT unit 409 and the reproduction difference signal of the reference frame specified by the motion vector output from the motion vector converter 501 are added to generate a reproduction difference signal, and store the signal in the image memory 411.

An adder 413 adds the reproduced difference signal and the reproduced video signal output from the second resolution converter 406 to generate a reproduced video signal of the first video signal.

Note that the horizontal and vertical ratios are respectively N2 / N
1, L2 / L1 (N1, N2, L1, and L2 are natural numbers), and the inverse transform of the DCT performed by the IDCT unit 403 is M
× MDCT, D performed by the IDCT unit 409
The inverse transform of CT is (M × N1 / N2) × (M × L1 / L
2).

As an example, if the input video signal is 1080
If the p-video signal is a low-resolution video signal and the low-resolution video signal is a 720p video signal, the motion vector converter 501 uses the motion vector output from the variable-length decoder 401 by multiplying it by 3/2 both horizontally and vertically. , N1 = 3, N2 = 2, L1 =
3, L2 = 2, and the IDCT unit 403 performs 8 × 8 DCT and its inverse transform,
What is performed by the CT unit 409 can be a 12 × 12 DCT and its inverse transform.

(Embodiment 6) The sixth embodiment of the present invention will be described below with reference to FIG.

In FIG. 6, those having the same numbers as those in FIG. 4 perform the same operations, and therefore the description will be omitted. 601 is a variable length decoder and 602 is an IDCT unit.

The variable length decoder 401 to which the first compressed stream is input performs a predetermined decoding and outputs a motion vector and a decoded signal. The inverse quantizer 402 inversely quantizes the decoded signal in a predetermined quantization step and outputs a DCT coefficient. The IDCT unit 403 converts the DCT coefficient into 8 × 8 DC
Inverse of T The motion compensator 404 is the IDCT unit 40
3 and the video signal of the reference frame specified by the motion vector are added to generate a reproduced video signal, which is stored in the image memory 405.

[0120] The second resolution converter 406 converts the resolution of the reproduced video signal and outputs it. Here, for the sake of simplicity, assume that the resolution is doubled in both the horizontal and vertical directions.

The variable length decoder 601 to which the second compressed stream has been input performs a predetermined decoding and outputs a motion vector and a decoded signal. The inverse quantizer 408 inversely quantizes the decoded signal at a predetermined quantization step and outputs a DCT coefficient. The IDCT unit 602 calculates the DCT coefficient as 16 × 16.
Performs inverse transform of DCT. The motion compensator 410 uses the IDCT
The output of the decoder 409 and the playback difference signal of the reference frame specified by the motion vector output from the variable length decoder 601 are added to generate a playback difference signal, and the image memory 411
To memorize.

An adder 413 adds the reproduced difference signal and the reproduced video signal output from the second resolution converter 406 to generate a reproduced signal of the first video signal.

Note that both the horizontal and vertical resolution conversion ratios are 1
The ratio of / 2 may be an arbitrary ratio independently of horizontal and vertical. In this case, the horizontal and vertical ratios are N2 / N1 and N2 / N1, respectively.
L2 / L1 (N1, N2, L1, L2 are natural numbers)
The inverse transform of DCT performed by the IDCT unit 403 is 8 ×
It is not necessary to use 8 units. In this case, if M × M DCT is used, the inverse transform of DCT performed by the IDCT unit 409 becomes (M × N1 / N2) × (M × L1 / L2).

As an example, if the input video signal is 1080
If the low-resolution video signal is a 720p video signal, N1 = 3, N2 = 2, L1 = 3, L2 = 2, and the IDCT unit 403 performs 8 × 8 D
Assuming that CT and its inverse transform are performed, what is performed by the IDCT unit 409 is a 12 × 12 DCT and its inverse transform.

[0125]

The video signal hierarchical coding apparatus according to the first invention of the present invention uses a motion vector detected when coding a low-resolution video signal for coding a high-resolution difference signal. By having only one motion detector and not including motion vector information in the second compressed stream, video signal hierarchical coding can be performed more efficiently than in the past, and the second The video signal layered coding apparatus of the present invention uses a quadrature transformation that matches a resolution ratio of a low-resolution video signal to encode a high-resolution difference signal, so that a high-resolution video signal and a low-resolution video signal are displayed on a screen. , The compression distortion can be prevented from crossing, and the video signal hierarchical coding can be performed with high image quality. The video signal hierarchical coding apparatus according to the third invention of the present invention Is a low-resolution video signal. Is used to encode a high-resolution differential signal, so that it has only one motion detector and does not include motion vector information in the second compressed stream. Also, by using an orthogonal transform that matches the resolution ratio with the low-resolution video signal to encode the difference signal, the compression unit is matched with the coding unit of the high-resolution video signal and the low-resolution video signal on the screen. Prevents crossover, so that high-quality video signal hierarchical coding can be performed more efficiently than before.
The video signal hierarchical decoding apparatus according to the fourth aspect of the present invention includes the motion vector decoder, thereby achieving the first aspect of the present invention.
It is possible to decode the compressed stream encoded by the video signal hierarchical coding apparatus of the invention or the video signal hierarchical coding apparatus of the third invention, and the video signal hierarchical coding of the fifth invention of the present invention. The decoding device has a motion vector converter, and can convert a compressed stream encoded by the video signal hierarchical coding device of the first invention of the present invention or the video signal hierarchical coding device of the third invention. The video signal hierarchical decoding apparatus according to the sixth aspect of the present invention includes an IDCT unit 602, and can be decoded by the video signal hierarchical encoding apparatus according to the second aspect of the present invention. The decoded compressed stream can be decoded.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal hierarchical coding apparatus according to a first embodiment of the present invention;

FIG. 2 is a block diagram of a video signal hierarchical coding apparatus according to a second invention of the present invention;

FIG. 3 is a block diagram of a video signal hierarchical coding apparatus according to a third invention of the present invention;

FIG. 4 is a block diagram of a video signal hierarchical decoding apparatus according to a fourth invention of the present invention;

FIG. 5 is a block diagram of a video signal hierarchical decoding apparatus according to a fifth invention of the present invention;

FIG. 6 is a block diagram of a video signal hierarchical decoding apparatus according to a sixth invention of the present invention;

FIG. 7 is a block diagram of a conventional video signal hierarchical coding apparatus.

FIG. 8 is a block diagram of a conventional video signal hierarchical decoding apparatus.

[Explanation of symbols]

101, 1001 First resolution converter 102, 201, 1002, 1012 Motion detector 103, 109, 115, 120, 404, 410, 1
004, 1009, 1014, 1019, 1024, 1
030 Motion compensator 104, 114, 405, 411, 1003, 101
3, 1025, 1031 Image memory 105, 116, 202, 1005, 1015 DCT
Units 106, 117, 1006, 1016 Quantizers 107, 118, 402, 408, 1007, 101
7, 1022, 1028 inverse quantizers 108, 119, 203, 403, 409, 602, 1
008, 1018, 1023, 1029 IDCT unit 110, 121, 1010, 1020 Variable length encoder 111, 406, 1011, 1026 Second resolution converter 112 Difference signal generator 113, 501 Motion vector converter 401, 407, 601, 1021, 1027 Variable length decoder 412 Motion vector decoder 413 Adder

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK03 MA00 MA23 MA32 MC11 ME01 NN02 NN28 TA12 TA21 TA36 TA63 TB07 TB17 TC12 TD13 UA02 UA05 5J064 AA01 BA09 BA13 BA16 BB01 BB14 BC01 BC02 BC08 BC16 BD01

Claims (7)

[Claims] 1. A first resolution conversion means for generating a low-resolution second video signal from a high-resolution first video signal which is an input video signal, and a high-resolution second video signal using motion compensation. A first high-efficiency encoding unit that outputs a first compression stream that has been efficiency-encoded; and a third high-efficiency encoding unit that generates a third video signal having the same resolution as the first video signal from a decoded video signal of the second video signal. Resolution conversion means, a difference signal generation means for generating a difference signal between the first video signal and the third video signal, and a difference signal using the motion vector detected in the first high-efficiency encoding. A video signal hierarchical coding device comprising: a second high-efficiency encoding unit that outputs a second compressed stream that has been subjected to high-efficiency encoding using motion compensation. 2. The number of samples in the horizontal direction in the frame is N2 / N1 and the number of lines in the vertical direction is L2 / N, as compared with the first video signal from the high resolution first video signal which is the input video signal. First resolution conversion means for generating a low-resolution second video signal which is L1 (N1, N2, L1, and L2 are natural numbers); motion compensation of the second video signal and M × M (M is a natural number) A first high-efficiency encoding means for outputting a high-efficiency encoded first compressed stream using the orthogonal transform of the second video signal; a third video signal having the same resolution as the first video signal from the decoded video signal of the second video signal. A second resolution converting means for generating a video signal of the following; a differential signal generating means for generating a differential signal between the first video signal and the third video signal; ) × (M × L
Video signal hierarchical coding, characterized by comprising a second high-efficiency coding means for outputting a high-efficiency coded second compressed stream using (1 / L2) (M is a natural number) orthogonal transform. apparatus. 3. The number of samples in the horizontal direction in the frame is N2 / N1 and the number of lines in the vertical direction is L2 / N, as compared with the first video signal from the high resolution first video signal as the input video signal. First resolution conversion means for generating a low-resolution second video signal which is L1 (N1, N2, L1, L2 are natural numbers); motion compensation of the second video signal and M × M (M is a natural number) A first high-efficiency encoding means for outputting a high-efficiency encoded first compressed stream using the orthogonal transform of the second video signal; a third video signal having the same resolution as the first video signal from the decoded video signal of the second video signal. Second resolution converting means for generating a video signal of the following, differential signal generating means for generating a differential signal between the first video signal and the third video signal, and a motion vector detected in the first high-efficiency encoding Is used for motion compensation of the difference signal and (M × N1 / N2) ×
A video signal hierarchical coding apparatus comprising: a second high-efficiency coding unit that outputs a second compressed stream that has been subjected to high-efficiency coding using (M × L1 / L2) orthogonal transform. 4. The video signal hierarchical coding apparatus according to claim 2, wherein a minimum unit of the motion compensation is a block of 2M × 2M. 5. A video signal hierarchical decoding apparatus according to claim 1, wherein the first compressed stream is decoded and a first decoded video signal of a second video signal is output. High-efficiency decoding means, second resolution conversion means for generating a third video signal having the same resolution as the first video signal from the decoded video signal of the second video signal, Second high-efficiency encoding that receives a second compressed stream as an input, decodes a motion vector from the first compressed stream, decodes the second compressed stream using the motion vector, and outputs a decoded signal of a difference signal Means for adding the third video signal and the decoded signal of the difference signal to generate a decoded video signal of the first video signal. 6. A video signal hierarchical decoding apparatus according to claim 1, further comprising: decoding a first compressed stream and outputting a motion vector and a decoded video signal of a second video signal. First high-efficiency decoding means, a second resolution conversion means for generating a third video signal having the same resolution as the first video signal from a decoded video signal of the second video signal, and a first compression A second high-level decoder that receives a motion vector decoded from the stream and the second compressed stream as input, decodes the second compressed stream using the motion vector in the first compressed stream, and outputs a decoded signal of a difference signal A video signal comprising: an efficiency encoding unit; and an addition unit configured to add a decoded video signal of the third video signal and a decoded signal of the difference signal to generate a decoded video signal of the first video signal. Hierarchical decryption Apparatus. 7. The video signal hierarchical decoding apparatus according to claim 2, wherein the first compressed stream is decoded using an M × M (M is a natural number) orthogonal transform, and the decoded video of the second video signal is decoded. A first high-efficiency decoding unit that outputs a signal, a second resolution conversion unit that generates a third video signal having the same resolution as the first video signal from a decoded video signal of the second video signal, 2 compressed stream is (M × N1 / N2) × (M × L1
/ L2) a second high-efficiency encoding means for decoding using the orthogonal transform of (L2) and outputting a decoded signal of the differential signal; and a first video signal obtained by adding the third video signal and the decoded signal of the differential signal. A video signal hierarchical decoding apparatus comprising an adding means for generating a decoded video signal of (1).