JP2001004715A - Operation adjusting and controlling device for electronic circuit and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To constitute an operation adjusting and controlling device which controls the driving data given to a circuit that adjusts the operating characteristic of an electronic circuit at a lower cost. SOLUTION: A control circuit 9, a storage circuit 10, a data value deciding circuit 11, and a data outputting circuit 12 are formed on the same Si substrate 21, and driving data used for adjusting the voltage of a power source for control generated and outputted by means of an operational amplifier 2 to a prescribed value is prestored in the storage circuit 10. The timing generator of the control circuit 9 reads out the driving data from the storage circuit 10 when the operational amplifier 2 is operated, and outputs the data to an adjustment circuit 7 through the data outputting circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation adjustment control device for outputting drive data to an adjustment circuit for adjusting the operation characteristics of an electronic circuit to predetermined characteristics, and a semiconductor integrated circuit device obtained by integrating these devices.

[0002]

2. Description of the Related Art For example, in an electronic circuit such as an amplifier circuit or a constant voltage circuit, the characteristics of each circuit element constituting the electronic circuit fluctuate due to individual manufacturing variations. Thus, the characteristics of the electronic circuit also vary. Therefore, the operation characteristics are checked in an inspection process after the electronic circuit is manufactured, and the circuit constants are adjusted by a variable resistor or the like so that the characteristics are constant.

When the electronic circuit is configured as an operation adjustment control device for an electronic circuit, the above adjustment work is not easy. For example, when a power supply circuit for generating and supplying a control power supply to a microcomputer or the like is configured as an integrated circuit device, the power supply circuit is operated after the completion of the circuit device, and an output voltage is detected. Is adjusted by laser trimming or fuse trimming of the thin film resistance element constituting the power supply circuit so that the value falls within a predetermined range. However, such an adjustment method is cumbersome and troublesome, and
Since the area of the resistance element and the circuit for adjustment becomes large, there is a problem that the whole circuit area becomes large accordingly.

[0004]

For example, Japanese Patent Application Laid-Open No. 9-330135 discloses an adjusting circuit for adjusting the characteristics of an electronic circuit in accordance with given driving data. Drive data obtained by this is stored in an EEPROM, and when an electronic circuit operates in a field, a CPU reads the drive data from the EEPROM and outputs the data to an adjustment circuit to perform correction. It has been disclosed.

[0005] However, in the above prior art, the EEP
Since the ROM is external to the semiconductor integrated circuit on which the CPU is mounted, the CPU has to execute the above series of adjustment operations by a program. Therefore, it is necessary to incorporate the program module as a part of the control program (user program) of the CPU, which requires a cost for creating the program module and a memory for storing the program. There was a problem. Further, C
It takes time for the PU to perform the adjustment operation.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an operation adjustment control device for performing control for supplying drive data to an adjustment circuit and a semiconductor integrated circuit device in which these devices are integrated. It consists in cost.

[0007]

According to a first aspect of the present invention, a data output circuit, a nonvolatile storage circuit, and a control circuit are formed on the same semiconductor substrate, and the storage circuit is provided in the storage circuit. The drive data for adjusting the operation characteristics of the electronic circuit to predetermined characteristics is stored in advance on the basis of, for example, characteristics obtained by actually operating the electronic circuit after completion. When the control circuit reads the drive data from the storage circuit during the operation of the electronic circuit, the control circuit performs an operation of outputting the drive data to the adjustment circuit via the data output circuit.

That is, the operating characteristics after the completion of the electronic circuit can be adjusted to be substantially constant based on the drive data stored in the storage circuit.
By forming the nonvolatile storage circuit on the same semiconductor substrate as the control circuit, the control circuit can be configured to execute processing such as access to the storage circuit by hardware. Therefore, if the above components are configured as an integrated circuit device, there is no need to create a program for adjusting the operation of the electronic circuit and store it in the program memory, and the control circuit operates automatically to perform the adjustment process. Since the execution is performed, the operation adjustment control device can be configured at low cost.

According to the electronic circuit operation adjustment control device of the second aspect, the control circuit performs an operation of reading drive data from the storage circuit and outputting the read data to the adjustment circuit at regular intervals.
That is, when the operation of reading the drive data and setting the data in the data output circuit is performed only once in the initial processing or the like, the data value held in the data output circuit changes when external noise or the like is applied. And
There is a possibility that the corrected operating characteristics will be shifted.

Therefore, the operation of setting the drive data in the data output circuit is preferably performed a plurality of times during the operation of the electronic circuit. On the other hand, when the access frequency of the control circuit to the nonvolatile storage circuit increases, More charge stress is applied to the storage circuit. Therefore, the operation of reading and setting the drive data is performed at regular intervals, so that even if the value of the drive data temporarily changes due to noise or the like, it is corrected at regular intervals. Of the storage circuit can be prolonged by reducing the charge stress by limiting the frequency of access to the storage circuit to some extent.

According to the third aspect of the present invention, the control circuit performs the control operation in synchronization with the clock signal output from the CR oscillation circuit. By obtaining the clock signal, the configuration of the control circuit can be simplified.

According to a fourth aspect of the present invention, the data output circuit, the storage circuit, and the control circuit are formed by a MOS transistor process. In that case, a portion that controls writing and reading of data to and from the storage circuit is also configured by the MOS transistor. Then, by forming the gate insulating film of the memory circuit together with the gate insulating film of the MOS transistor, the memory circuit can be formed in a smaller number of steps (in addition,
See Japanese Patent Application No. 10-328560 for details.

Further, for example, when the control circuit includes a CR oscillation circuit, or when the electronic circuit includes a capacitor, the control gate and the floating gate of the storage circuit may be replaced with the control gate and the floating gate of the capacitor. By forming the memory device together with the lower electrode and the upper electrode, the entire device including the memory circuit can be formed with a smaller number of steps.

According to the operation adjustment control device for an electronic circuit of the present invention, the storage circuit stores three or more sets of the same drive data, and the control circuit reads out the plurality of sets of drive data from the storage circuit. And output them to the data value determination circuit. Then, the data value determination circuit compares the plurality of sets of data on a bit-by-bit basis and outputs the data value that occupies the majority to the data output circuit.

That is, when the drive data stored in the storage circuit is read by the control circuit, even if a partial error occurs in the read data value due to external noise or the like, The data value determination circuit selects and outputs the data value that occupies a larger number in each bit of a plurality of sets of data, so that it is possible to minimize the output of erroneous drive data to the adjustment circuit, thereby improving reliability. Can be further improved.

According to the operation adjustment control device for an electronic circuit of the present invention, the storage circuit transmits a plurality of sets of data to a common data bus provided for each bit, at a different timing for each set. Therefore, the data bus width is not required to be plural times to read a plurality of sets of data, and an increase in space on the semiconductor substrate can be suppressed.

According to the semiconductor integrated circuit device of the present invention, the operation adjustment control device of the electronic circuit can perform the adjustment operation independently of the control program of the computer block. This makes it unnecessary to execute the adjustment operation, and is preferable without imposing any restrictions on the capacity of the program memory or the operation of the computer block itself.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an ECU (Electronic Control Unit) for controlling an automobile engine will be described below with reference to the drawings.
FIG. 1 is a functional block diagram showing the entire electrical configuration. The ECU (semiconductor integrated circuit device) 1 is formed by a MOS transistor process. The operational amplifier (electronic circuit) 2 constitutes a constant voltage circuit which generates a control power supply to be supplied to a microcomputer or the like constituting the ECU from a power supply of about 14 V supplied from a battery (not shown) and outputs the control power supply from an output terminal 2c. ing.

The power of the battery is supplied to the input terminal 3. A series circuit of the resistor 4, the resistor array unit 5, and the resistor 6 is connected between the input terminal 3 and the ground, and these constitute an adjustment circuit 7. The resistor array unit 5 includes 16 resistors 5 a having a smaller resistance value than the resistors 4 and 6, connected in series, and a common connection point of each resistor 5 a and a common connection point of the resistors 5 a and 6. Are commonly connected to a non-inverting input terminal of the operational amplifier 2 via a switch 5b constituted by, for example, an analog switch.

The inverting input terminal of the operational amplifier 2 is connected to the ground. The input part of the operational amplifier 2 has two P-channel MOSs each having a different threshold voltage.
It is composed of transistors 2a and 2b, and outputs a constant voltage to an output terminal 2c using the threshold voltage difference between the two as a reference voltage.

The 16 switches 5b in the resistance array section 5 are controlled by the data value of each bit provided from a 16-bit data bus of an operation adjustment control device (hereinafter, simply referred to as a control device) 8. If the data value of the bit to be changed is "0", the switch 5b is turned off, and if the data value is "1", the switch 5b is turned off.
N. The data value is
As will be described later, 4-bit data is encoded, and one of the bits whose data value is "1" is one.

The divided potential applied to the non-inverting input terminal of the operational amplifier 2 changes depending on which position of the switch 5b in the resistance array section 5 is turned on. The operational amplifier 2 amplifies the divided potential at a predetermined amplification factor and outputs a control power supply, so that the control power supply voltage can be adjusted by turning on which switch 5b.

The control device 8 includes a control circuit 9, a storage circuit 1
0, a data value determination circuit 11, a data output circuit 12, and the like. Further, an external inspection device 14 is connected to the control device 8 via an interface (I / F) unit 13. The interface unit 13 is also provided with an output voltage from the operational amplifier 2, and the detection level of the output voltage can be output to the inspection device 14 side. The inspection device 14 is used to adjust the operation characteristics of the operational amplifier 2 in a line inspection process after the ECU 1 is manufactured.

Further, the ECU 1 is provided with a processing circuit block 40 composed of a computer block and other circuit blocks. This processing circuit block 40
For example, it can be said to be a portion including circuit blocks such as a computer block 4, a power-on reset circuit 6, a temperature sensor 12, a multiplexer 14, and an A / D converter 16 shown in FIG. 1 of Japanese Patent Application Laid-Open No. 9-330135. Also,
In the computer block, it can be said that it includes a CPU, a program memory, a data memory, and an I / O block.

FIG. 2 shows a detailed electrical configuration of the control device 8. The control circuit 9 includes a CR oscillation circuit 15 and a timing generator 16. CR
The oscillation circuit 15 includes a capacitor (capacitor), a resistor, an operational amplifier, and the like.
A clock signal CLK of about z is output, and the clock signal is given to the timing generator 16.

FIG. 3 is a timing chart showing the operation of the timing generator 16. The timing generator 16 reduces the number of input pulses of the clock signal CLK to 3
By counting with a bit counter, monopulse timing signals CNT_A to CNT_D are output at regular intervals according to the count value. That is,
The count value of the counter circulates from "1 to 8 (0 to 7)", and the output timing of each timing signal with respect to the count value is as follows.

The timing signals CNT_A to CNT_C output from the timing generator 16 are supplied to the storage circuit 10 and are provided at a flip-flop (F / F) 11 arranged at the input of the data value determination circuit 11.
a to 11c are respectively output as latch signals. The timing signals actually applied to the flip-flops 11a to 11c are slightly delayed from the timing signals CNT_A to CNT_C applied to the storage circuit 10 in consideration of appropriate latch timing of data.

The timing signal CNT_D is supplied to the switch 1 disposed at the output of the data value determination circuit 11.
1d is provided as a control signal, and is output as a latch signal to a correction register 12a constituting the data output circuit 12. Note that the timing signal actually supplied to the correction register 12a is also slightly delayed from the timing signal CNT_D supplied to the switch 11d for the same reason as described above.

The CR oscillation circuit 15 generates a clock for determining the operation timing of the computer block in the processing circuit block 40. This is preferable in performing the adjustment operation.

The storage circuit 10 has twelve memory cells 17 configured as a two-layer gate type EPROM by a MOS transistor process (however, only three are shown in FIG. 2). The drive data output to the resistance array unit 5 is 4 bits as described above, but the storage circuit 10 stores three sets of the same data in the storage circuit 10 for the sake of reliability. Note that the storage circuit 1
Although a control signal for writing the data is separately provided to 0, the portion is not shown.

The three sets of memory cells 17a to 17c are:
The data is output to the common data bus 19 via the data reading switches 18a to 18c.
The switches 18a to 18c are actually configured by P-channel MOS transistors or the like, and the opening and closing thereof are controlled by timing signals CNT_A to CNT_C, respectively.

The data bus 19 is connected to the flip-flop 11
The data output terminals of the flip-flops 11a to 11c are connected to the input terminals of the data value determination circuit 11, respectively. The output terminal of the data value determination circuit 11 is connected to the switch 1
It is connected to the input terminal of the correction register 12a via a switch 11d having the same configuration as 8a to 18c.
The 4-bit data output from the correction register 12a is supplied to the decode circuit 12b and decoded, and one of the 16 output signals S0 to S15 becomes high level and is applied to each switch 5b of the resistance array unit 5. Each is output.

A control signal from the inspection device 14 is input to the decoding circuit 12b via the interface unit 13. The decoding circuit 12b
When a 4-bit control signal from the inspection device 14 is supplied, the control signal is decoded and output instead of the drive data supplied from the correction register 12a.

FIG. 4 is a truth table of the data value decision circuit 11, and FIG. 5 shows a detailed configuration of the data value decision circuit 11. As shown in FIG. 5, the data value determination circuit 11 includes three two-input AND gates 20a, 20a.
0b and 20c and a three-input OR gate 20d to which output signals from AND gates 20a to 20c are applied. That is, as is apparent from the truth table shown in FIG. 4, if any two bits of the three sets of data A, B, and C are "1", the output data D is set to "1". , The data value that occupies a larger number is selected as a correct value and is output to the data output circuit 12.

In FIG. 2, the configurations of the storage circuit 10 and the data value determination circuit 11 are specifically shown only for one bit (three sets) of drive data, but the other three bits are also shown. It is configured similarly.

As described above, the control device 8 operates based on the operation timings from the CR oscillation circuit 15 and the timing generator 16.
0 operates independently of the control program of the computer block at 0. Therefore, since it is not necessary to control the control device 8 by the control program, the control program can be designed for the computer block without considering the adjustment operation by the control device 8, which is preferable. Further, the operation of the computer block is not complicated because it is not necessary to execute the adjustment operation, which is preferable.

FIGS. 6 and 7 are schematic cross-sectional views showing a process for forming the ECU 1 with a focus on a memory cell 17 constituting the storage circuit 10. FIG. The details are described in Japanese Patent Application No. 10-328560, and here, the forming process will be schematically described.

The ECU 1 is formed by a MOS transistor process, and as described above, the switches 18a to 18c used in each section also use MOS transistors. Further, since a large number of capacitors are used in the CR oscillation circuit 15 and a circuit portion around a power supply connected to the output terminal of the operational amplifier 2 and the like, although not specifically shown, the memory cell 17 is formed. , Those M
This is performed simultaneously with the formation of the OS transistor and the capacitor.

First, a P-well 21a and an N-well 21b are formed on a Si substrate (semiconductor substrate) 21, and then a field oxide film 22 is formed by a LOCOS oxidation method.
Each element region such as M, capacitor and MOS transistor is separated (see FIG. 6A). Next, the Si substrate 21
After a dummy oxide film 23 is formed thereon, a first-layer polysilicon film 24 is grown on the entire surface of the wafer (FIG. 6B).
reference).

Subsequently, after removing the dummy oxide film 23, a photoresist (not shown) having a predetermined area opened is disposed on the polysilicon film 24, and the polysilicon film 24 is patterned using the photoresist as a mask. . Thus, the control gate 25 is formed in the EPROM area and the lower electrode 26 is formed in the capacitor area. Then, the control gate 25 and the lower electrode 2
6 is oxidized to form a gate insulating film (insulating film) on these surfaces.
27 are formed.

A first gate film (gate insulating film) 28 is formed on the Si substrate 21 in the EPROM region by thermal oxidation.
a, and a gate oxide film 28b is formed on the Si substrate 21 in the MOS transistor region (FIG. 6).
(C)). Here, the thermal oxidation process for forming the first gate film 28a and the gate oxide film 28b can be shared.

Next, after a second polysilicon film 29 is formed on the entire surface of the wafer including the first gate film 28a and the gate oxide film 28b (see FIG. 7A), the polysilicon film is formed by photoetching. 29 is patterned and E
A floating gate 30 is formed in the PROM area, an upper electrode 31 is formed in the capacitor area, a gate 32 is formed in the MOS transistor area, and a polysilicon resistor 33 is formed between the capacitor area and the EPROM area. afterwards,
Floating gate 30 and upper electrode 3 by thermal oxidation
1, a protective oxide film 34 is formed on the surfaces of the gate 32 and the polysilicon resistor 33 (see FIG. 7B).

Subsequently, after an interlayer insulating film 35 is formed on the entire surface of the wafer by the CVD method, a process for flattening the interlayer insulating film 35 is performed. Then, contact holes 35a, 35b, 35 are formed in interlayer insulating film 35 by photoetching.
After forming c, the electric wiring 36 is patterned. As a result, the electrical wirings 36a, 36b, 36c are electrically connected to the floating gate 30, the upper electrode 31, and the like via the contact holes 35a, 35b, 35c.

Thereafter, by covering the entire surface of the wafer with the protective film 37, the ECU 1 including the storage circuit 10 including the memory cells 17 and other circuits is formed (see FIG. 7C). In this embodiment, since the surface of the memory cell 17 is covered with the protective film 37 or the like, the memory cell 17 is substantially an OTPROM (One Time Programmable R).
OM).

Next, the operation of this embodiment will be described. <Inspection Process> When the ECU 1 is formed as described above, the inspection device 14 is connected to the control device 8 via the interface unit 13 in the inspection process. Then, the same voltage of about 14 V as the battery power supply is applied to the input terminal 3, and the operational amplifier 2 generates a control power supply and
output to c.

The operator gives a control signal to the decoding circuit 12b while monitoring the output voltage of the operational amplifier 2 displayed via the interface unit 13 by the inspection device 14, and supplies a control power supply voltage output from the operational amplifier 2. Switch 5b of the resistance array unit 5 is switched so that the predetermined value becomes a predetermined value (for example, 5 V).

Here, for example, the twelfth
It is assumed that the control power supply voltage output from the operational amplifier 2 becomes a predetermined value when the second switch 5b is turned on. Twelfth
The drive data for turning on the switch 5b is
It is "1011" in binary. Next, the operator causes the inspection device 14 to write data “1011” into the storage circuit 10.

In the drive data, three sets of the same data value are written in the memory cells 17a to 17c per bit.
1 "is output, and each data value is output to the write data bus for each bit of the storage circuit 10, and the memory cells 17a to 17b of each bit are stored inside the storage circuit 10.
The same data value is written every 17c.

<Field> When drive data for adjustment is written in the storage circuit 10,
The ECU 1 is shipped to the field. And ECU1
When the power is turned on and the device is actually operated, the timing generator 16 outputs the clock signal CLK as shown in FIG.
In synchronization with the timing signals CNT_A to CNT_D.

In the fourth clock, the timing signal CN
When T_A is output, the switch 18a turns ON,
The data bus 19 of each of the bits 3 to 0 of the storage circuit 10 has
The data value stored in memory cell 17a is output. Then, the flip-flop 11a of the data value determination circuit 11 latches the data output to the data bus 19.

When the timing signal CNT_B is output at the fifth clock, the switch 18b is turned on.
And the data bus 1 of each bit 3 to 0 of the storage circuit 10
9, the data value stored in the memory cell 17b is output, and the flip-flop 11b is connected to the data bus 19b.
Latch the data output to. When the timing signal CNT_C is output at the sixth clock, the data value stored in the memory cell 17c is output and latched by the flip-flop 11c.

As described above, each flip-flop 1
When the data A to C read from the memory cells 17a to 17c are latched in 1a to 11c, the data value determination circuit 11 outputs the value of the data D according to the truth table shown in FIG. When the timing signal CNT_D is output at the seventh clock, the switch 11d is turned on, and the data D is output to the correction register 12a and latched.

The data D is "1" in the decode circuit 12b.
When "011" is given, the decode circuit 12b decodes the data "1011" and sets the output terminal S12 to a high level, whereby the twelfth switch 5b in the resistance array unit 5 is turned on, and the operational amplifier 2 is turned off. The power supply voltage of the battery is connected to the inverting input terminal by the resistors 4 and 12.
Since the potential divided by the resistors 5a, 5a, and 6 is applied, the control power supply voltage is output as the predetermined value 5V by the operational amplifier 2 in the same manner as in the case where the voltage is adjusted in the inspection process. You.

The above operation is performed by the clock signal CL.
Since the eight cycles of K are repeated as one unit, the drive data set in the correction register 12a is 62.5 μm.
It is reset and refreshed every S × 8 = 500 μS.

As described above, according to the present embodiment, the control circuit 9, the storage circuit 10, the data value determination circuit 11, and the data output circuit 12 are formed on the same Si substrate 21, and the storage circuit 1
In 0, drive data for adjusting the voltage of the control power supply generated and output by the operational amplifier 2 to a predetermined value is stored in advance. The control circuit 9 includes a CR oscillation circuit 15 and a timing generator 16 that operates in synchronization with a clock signal CLK output from the CR oscillation circuit 15, and stores drive data when the operational amplifier 2 operates.
And output it to the adjustment circuit 7 via the data output circuit 12.

Therefore, the operating characteristics after the operational amplifier 2 is formed can be adjusted to be substantially constant based on the drive data stored in the storage circuit 10. Then, there is no need to create a program for adjusting the operation of the operational amplifier 2 and store it in the program memory, and the adjustment processing is executed by the automatic operation of the timing generator 16 constituted by hardware. The control device 8 can be configured at low cost.

The timing generator 16 reads the drive data from the storage circuit 10 and outputs it to the adjustment circuit 7 every eight cycles of the clock signal CLK output from the CR oscillation circuit 15. That is, when the operation of setting the drive data is performed only once in the initial processing or the like, the data value held in the data output circuit 12 changes when noise or the like is applied from the outside, and the data value is corrected. There is a possibility that the operating characteristics may shift.

For this reason, it is preferable that the operation of setting the drive data be performed a plurality of times during the operation of the operational amplifier 2.
On the other hand, if the frequency of access of the control circuit 9 to the storage circuit 10 increases, more charge stress will be applied to the storage circuit 10. Therefore, by performing the operation of reading and setting the drive data at regular intervals,
Even if the value of the drive data changes temporarily due to noise or the like, it is corrected at regular intervals to improve the reliability of adjustment, and the frequency of access to the storage circuit 10 is restricted to some extent to reduce charge stress. By doing so, the life of the storage circuit 10 can be extended.

Further, the timing generator 16 calculates C
Clock signal CLK output by R oscillation circuit 15
Since the control operation is performed in synchronization with the control circuit 9, the configuration of the control circuit 9 can be simplified by obtaining a clock signal from the CR oscillation circuit 15 having a simple configuration.

Further, according to the present embodiment, the ECU 1
The memory circuit 10 is formed by the S transistor process.
A portion for controlling the writing and reading of data inside the memory device is also constituted by a MOS transistor. Then, by forming the first gate film 28a of the storage circuit 10 together with the gate oxide film 28b of the MOS transistor, the storage circuit 10 can be formed in a smaller number of steps.

The CR oscillation circuit 15 and the operational amplifier 2
Since the output side and the like include a capacitor, the control gate 25 and the floating gate 30 of the storage circuit 10 can be formed together with the lower electrode 26 and the upper electrode 31 of the capacitor. Further, it is not necessary to perform photoetching for separating the floating gate 30 after the formation of the first polysilicon film 24, and the threshold value Vt of the MOS transistor and the threshold value Vt of the memory cell 17 are reduced. Can be shared with the impurity implantation process for adjusting the impurity concentration.

In addition, since the steps of forming the source and drain in the EPROM region and the MOS transistor region can be shared, the number of steps performed only for forming the memory cell 17 as the EPROM is reduced. The whole ECU 1 can be formed with a small number of steps.

According to the present embodiment, three sets of the same drive data are stored in the storage circuit 10, and the timing generator 16 stores the three sets of drive data in the storage circuit 1.
When read from 0 and output to the data value determination circuit 11,
The data value determination circuit 11 compares the three sets of data for each bit, and outputs the data value that occupies the larger number to the data output circuit 12.

That is, when the drive data stored in the storage circuit 10 is read, even if a partial error occurs in the read data value due to external noise or the like, the data value is not changed. Since the decision circuit 11 selects and outputs the data value that occupies the majority in the three sets of data, it is possible to minimize the output of erroneous drive data to the adjustment circuit 7 and further improve the reliability. be able to.

The storage circuit 10 stores three sets of data in a common data bus 19 provided for each bit.
Are output at different timings for each set, so that the data bus width does not need to be tripled to read three sets of data, and an increase in space on the Si substrate 21 can be suppressed.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. The storage circuit may store four or more sets of data, and the data value determination circuit may output a data value that occupies the majority of the four or more sets of data. Further, the data value determination circuit may be provided as needed. The adjustment circuit may be constituted only by the resistance array unit 5. The output data bus of the storage circuit does not necessarily need to be a common data bus, and a bus for a plurality of sets of data may be provided and data may be simultaneously output on these buses.

In place of the CR oscillation circuit 15, an oscillation circuit using a crystal oscillator may be used. The storage circuit 10 may be provided with a window for erasing ultraviolet rays so that drive data once written can be erased. In the storage circuit, Japanese Patent Application Hei 1
An EPROM formed by a general manufacturing process is not limited to the EPROM described in JP-A-328560.
A PROM may be used. Further, the present invention is not limited to the EPROM, and an EEPROM or a flash ROM may be used. The electronic circuit is not limited to a constant voltage circuit using the operational amplifier 2, but may be any circuit that needs to be adjusted in an analog manner. In addition, the semiconductor integrated circuit device also includes the ECU 1
It is not necessary to limit to.

[Brief description of the drawings]

FIG. 1 is an embodiment when the present invention is applied to an ECU, and is a functional block diagram showing an overall electrical configuration.

FIG. 2 is a diagram showing a detailed electrical configuration of a control device.

FIG. 3 is a timing chart showing the operation of a control circuit.

FIG. 4 is a diagram showing a truth table of a data value determination circuit;

FIG. 5 is a diagram showing a detailed configuration of a data value determination circuit;

FIG. 6 is a schematic cross-sectional view showing a process for forming an ECU, focusing on a memory cell part forming a storage circuit (part 1);

FIG. 7 is a diagram corresponding to FIG. 6 (part 2);

[Explanation of symbols]

1 is an ECU (semiconductor integrated circuit device), 2 is an operational amplifier (electronic circuit), 7 is an adjustment circuit, 8 is an operation adjustment control device,
9 is a control circuit, 10 is a storage circuit, 11 is a data value determination circuit, 12 is a data output circuit, 15 is a CR oscillation circuit, 16
Is a timing generator, 17 is a memory cell, 19 is a data bus, 21 is a Si substrate (semiconductor substrate), 22 is a field oxide film, 25 is a control gate, 26 is a lower electrode, 27 is a gate insulating film (insulating film), 28a Is the first
A gate film (gate insulating film); 28b, a gate oxide film;
0 is a floating gate, 31 is an upper electrode, 34 is an interlayer insulating film, 35a to 35c are contact holes, 36a
36c is an electric wiring, 40 is a processing circuit block (computer block).

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shinichi Noda 1-1-1, Showa-cho, Kariya-shi, Aichi F-Term in Denso Co., Ltd. (Reference) 2G032 AA08 AD08 AE11 5J092 AA01 CA87 CA92 FA16 HA10 HA25 HA38 KA00 KA01 KA32 KA33 KA36 QA02 SA07 TA01 TA06 9A001 BB01 BB03 BB04 BB05 EE05 HH34 JJ49 KK31 KK37 LL02 LL05

Claims (7)

[Claims] 1. An operation adjustment control device for outputting drive data to an adjustment circuit for adjusting an operation characteristic of an electronic circuit, wherein when the drive data is provided, the data is latched, decoded, and output. An output circuit; a nonvolatile storage circuit in which drive data for adjusting the operation characteristics to predetermined characteristics is stored in advance; and, when the electronic circuit is operating, the drive data is read from the storage circuit to output the data. A control circuit that executes an operation of outputting to the adjustment circuit via a circuit by hardware, wherein the data output circuit, the storage circuit, and the control circuit are formed on the same semiconductor substrate. Operation adjustment control device for electronic circuits. 2. The operation adjustment control device for an electronic circuit according to claim 1, wherein the control circuit performs an operation of reading the drive data from the storage circuit and outputting the read data to the adjustment circuit at regular intervals. . 3. The operation adjustment of an electronic circuit according to claim 1, wherein the control circuit is configured to perform a control operation in synchronization with a clock signal output by a CR oscillation circuit. Control device. 4. The data output circuit, the storage circuit, and the control circuit are formed by a MOS transistor process. The storage circuit includes a field oxide film having an opening in a predetermined region; A gate insulating film exposed from the opening of the oxide film; a control gate formed on the field oxide film; an insulating film formed on the control gate; and an insulating film formed on the control gate via the insulating film. A floating gate extending from the control gate to the gate insulating film, an interlayer insulating film formed to cover the floating gate and the control gate, and formed on the interlayer insulating film. A contact hole communicating with the control gate; Through Kutohoru provided with electric wiring and electrically connected to the control gate, the control gate and floating gate,
4. The operation adjustment control of an electronic circuit according to claim 1, wherein the gate insulating film is formed together with a lower electrode and an upper electrode of a capacitor, and the gate insulating film is formed together with a gate insulating film of a MOS transistor. apparatus. 5. The memory circuit stores three or more sets of the same drive data. The plurality of sets are formed on the semiconductor substrate, and when the plurality of sets of data are provided, the plurality of sets of data are transferred. A data value determination circuit that outputs a data value that occupies the majority compared to each bit to the data output circuit, wherein the control circuit reads the plurality of sets of drive data from the storage circuit, The operation adjustment control device for an electronic circuit according to claim 1, wherein the plurality of sets of drive data are output to a data value determination circuit. 6. The storage circuit is configured to be able to output the plurality of sets of data to a common data bus provided for each bit at a different timing for each set. The operation adjustment control device for an electronic circuit according to claim 5, wherein 7. An electronic circuit, an adjustment circuit for adjusting an operation characteristic of the electronic circuit, an operation adjustment control device for the electronic circuit according to claim 1, a CPU, a program memory, a data memory, A computer block including an I / O block, wherein the operation adjustment control device is synchronized with a timing generator operated by a clock signal output from an oscillation circuit. A semiconductor integrated circuit device that operates independently of a control program in the computer block.