JP2001004704A - Device and method for testing integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an integrated circuit testing machine having a vector condition branching function and another integrated circuit testing machine having no vector condition branching function of a plurality of integrated circuit testing machines, function as one integrated circuit testing device by synchronously operating the testing machines. SOLUTION: A slave 12 having no condition branching function transmits a second control signal indicating the start of a test to a master 11, after transmitting a first control signal indicating the position of a test vector in execution to a control signal receiving circuit 7 by a fixed number of times through a control signal transmitting circuit 6. The master 11 performs test vector address synchronization to the slave 12 upon receiving the first control signal, and adjusts the starting timing of an actual test program at both the master 11 and slave 12 upon receiving the second control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit test apparatus and a test method, and more particularly to an integrated circuit test apparatus and a test method for synchronizing a plurality of integrated circuit testers and functioning as one integrated circuit test apparatus.

[0002]

2. Description of the Related Art A typical technique for synchronizing a plurality of integrated circuit testers to function as one integrated circuit test apparatus is disclosed in Japanese Patent Application No. Hei 10-362617 (Document 1). It is shown.

Referring to FIG. 14, which shows a block diagram of a conventional integrated circuit test apparatus described in Document 1, a conventional integrated circuit test apparatus 100 generally includes an integrated circuit as a master 110.
And a group called a slave 120, and the slave 120 is operated in synchronization with the master 110.

[0004] The master 110 comprises a control system 80,
It includes a test pin 9, a master clock output circuit 40, and a control signal transmission circuit 61.

[0005] Slave 120 includes a control system 80,
It includes a test pin 9, an external synchronous clock input circuit 50, a control signal receiving circuit 71, and a control signal transmitting circuit 62.

[0006] Thus, the vector conditional branch function provided in each of the master 110 and the slave 120,
Each of the master 110 and the slave 120 is a set of control signal transmitting circuits 61 and 62 and a control signal receiving circuit 7.
By having 1 and 72, synchronization between the phase of the test vector and the execution address is realized.

FIG. 14 is a flowchart showing test vectors in the master and slave at this time.
With reference to FIG. 16 and FIG. 16, the operation of the conventional integrated circuit test apparatus will be described. First, the master 110 transmits a trigger signal to the slave 120 via the control signal transmission circuit 61, and in the wait (standby) period 5, enter. After a fixed wait period 5, slave 1
20 is received. After a certain wait period 6, it is determined whether the trigger reception has succeeded. If the trigger is successfully received, a fixed wait period of 7
After that, start the actual test. If the trigger reception has not been successful, the process returns to the trigger signal transmission, and the processing up to the above determination is repeated (step P11).

On the other hand, slave 120 receives a trigger signal sent from master 110 via control signal receiving circuit 71. After a certain wait period 8, it is determined whether the trigger reception is successful. If the trigger is successfully received, a trigger signal is transmitted to the master 110 via the control signal transmission circuit 62. After a certain wait period 9, the actual test is started. If the trigger reception has not been successful, the process returns to the trigger signal reception, and the processing up to the above determination is repeated (step P12).

[0009]

The above-described conventional integrated circuit test apparatus and test method require a vector conditional branch function for both the master and the slave, and therefore use an integrated circuit tester having no vector conditional branch function. There is a problem that you can not.

A main object of the present invention is to provide an integrated circuit tester having a vector conditional branching function when a plurality of integrated circuit testers are operated synchronously to function as one integrated circuit test apparatus. An object of the present invention is to provide a synchronous circuit configuration and a synchronous method for synchronously operating an integrated circuit tester having no vector conditional branch function.

[0011]

According to a first aspect of the present invention, there is provided an integrated circuit test apparatus in which first and second integrated circuit testers functioning independently are defined as a master and a slave, respectively, and are operated in cooperation with each other. An integrated circuit test apparatus functioning as one integrated circuit tester, wherein the master receives reference clock signal transmitting means for transmitting a reference clock signal to the slave, and receives a state control signal transmitted from the slave. State control signal receiving means, and an execution procedure changing means for changing the execution procedure of the test program at any time in accordance with the state of the received state control signal, wherein the slave comprises the reference clock signal transmission means and A reference clock signal electrically connected to receive the reference clock signal sent from the master; Communication means, a synchronization control means for performing a synchronous operation on the master by the reference clock signal, and electrically connected to the state control signal receiving means, and transmits the state control signal to the master. And a state control signal transmitting means for transmitting.

In an integrated circuit test apparatus according to a second aspect of the present invention, the first and second integrated circuit testers, which function independently, are defined as a master and a slave, respectively, and cooperate with each other to operate as one integrated circuit tester. In the integrated circuit test apparatus to be functioned, the slave is provided with a reference clock signal receiving means for receiving a reference clock signal sent from the master, and a slave for performing a synchronous operation on the master by the reference clock signal. A synchronization control unit, a state control signal receiving unit for receiving a state control signal sent from the master, and a state control signal receiving unit for changing the execution procedure of the test program as needed in accordance with the state of the received state control signal. Execution procedure changing means, wherein the master is electrically connected to the reference clock signal receiving means, A reference clock signal transmitting means for transmitting the reference clock signal to the slave, and a state for transmitting the state control signal to the slave, the state being electrically connected to the state control signal receiving means. Control signal transmission means, wherein the reference clock signal transmission means can control transmission and stop of the test program independently of execution of the test program in the master.

According to a third aspect of the present invention, there is provided an integrated circuit test apparatus which is one of three or more integrated circuit test machines functioning independently.
In an integrated circuit test apparatus which defines a table as a master and the others as slaves and cooperates with each other and functions as one integrated circuit tester, each of the slaves receives a reference clock signal sent from the master. Means for performing a synchronous operation on the master by the reference clock signal, and a state control signal for receiving a state control signal sent from the master Means, and an execution procedure changing means for changing the execution procedure of the test program at any time in accordance with the state of the received state control signal, wherein the master is electrically connected to the reference clock signal receiving means. Reference clock signal transmitting means for transmitting the reference clock signal to the slave, Serial state control signal receiving means is electrically connected to, and a state control signal transmitting means for transmitting the state control signal to the slave,
The reference clock signal transmitting means can control transmission and stop of the test program independently of execution of the test program in the master.

According to a fourth aspect of the present invention, there is provided a method for testing an integrated circuit, wherein one of two or more integrated circuit testers each functioning independently is defined as a master and the others are defined as slaves. In the integrated circuit test apparatus functioning as one integrated circuit tester, the slave performs a first number of tests for determining whether a state control signal is transmitted from the master at a predetermined timing. When the judgment is true, the process proceeds to the second step after the first number of test rates from the beginning of the repetition step, and when the judgment is false, The first step is repeated, and in the second step, the slave transmits the state control signal at a predetermined timing from the master. The step for determining whether or not the test rate is repeated with a second number of test rates as a cycle, and when the determination is true, the second number of test rates are repeated from the beginning of the second step. In the actual integrated circuit test step, if the determination is false, repeat the second step, the master,
First, a first state control signal is transmitted from the state control signal transmitting means to the slave at a predetermined timing, and the first state control signal is transmitted to the first slave at a cycle of the second number of test rates.
Is repeated several times or more, and then, at a predetermined timing, the slave receives the second
And this is executed only once with the first number of test rates as a cycle, and then proceeds to the actual integrated circuit test step, where the first and second numbers are relatively prime. And the second in the slave
In the step, when the slave attempts to receive the second state control signal, the first and second state control are performed in advance so as not to receive the first state control signal transmitted from the master by mistake. By defining the transmission timing of each signal, the test of the integrated circuit is performed after the timing of the test operation in all the integrated circuit testers is matched.

[0015]

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG.
The integrated circuit test apparatus 1 of the present embodiment, which is shown together with the integrated circuit 3 to be tested, is realized as one integrated circuit test apparatus by operating two integrated circuit test machines in cooperation with each other. The two integrated circuit testers are called master 11 and slave 12, respectively, to distinguish them.

The master 11 has a master clock output circuit 4 for outputting a master clock necessary for synchronously operating the slaves 12, and a control signal receiving circuit 7 for receiving a control signal sent from the slaves 12. Further, the master 11 responds to the state of the signal input to the control signal receiving circuit 7 during the execution of the test vector,
It has a conditional branch function for changing the execution order of test vectors.

The slave 12 includes an external synchronous clock input circuit 5 and a control signal transmitting circuit 6. The slave 12 does not need to have a conditional branch function for changing the execution order of the test vectors in accordance with an external signal, but is not required to repeatedly execute a predetermined number of times for a specific test vector address section. Need to have a loop function.

The master 11 and the slave 12 are:
A control system 8 for controlling the entire apparatus and a plurality of test pins 9 are provided. The test pins 9 are electrically connected to the integrated circuit 3 via the test board 2.

The master clock output circuit 4 outputs a master clock and supplies it to the external synchronous clock input circuit 5 of the slave 12. As a result, the slave 12 operates externally synchronously with the master clock.

The control signal transmitting circuit 6 of the slave 12 outputs a control signal and supplies it to the control signal receiving circuit 7 of the master 11.

Next, the operation of the test vector address synchronization according to the present embodiment will be described with reference to FIG. 1 and FIGS. 2 and 3, which are flowcharts showing the test vector configuration processing of the master 11 and the slave 12.

The external synchronization operation of the slave 12 with respect to the master 11 and the adjustment of the phase of the test rate between the master 11 and the slave 12 are described in the literature 1 or the like which describes a conventional integrated circuit test apparatus. It is assumed that has already been completed.

First, in step S11, the master 11 attempts to receive the reference signal transmitted from the slave 12 by the control signal receiving circuit 7, and then waits for a certain wait period 1. If the reference signal reception fails,
The reception and the standby of the reference signal are repeated again. The reception cycle of the reference signal is defined as N1 test rate.

It is to be noted that only when the test vector addresses of the master 11 and the slave 12 in the integrated circuit 3 match, the master 11
The master 11 adjusts the reception timing of the reference signal and the slave 12 adjusts the transmission timing of the reference signal so as to succeed in receiving the reference signal transmitted from.

On the other hand, the slave 12 transmits a reference signal from the control signal transmitting circuit 6 in step S12, and thereafter waits for a predetermined wait period 3. The period of the reference signal transmission at this time is defined as N2 test rate. The transmission cycle of the reference signal is N2. The slave 12 repeats this operation N3 times. Next, slave 12 immediately proceeds to step S
After executing step 22 and repeating the transmission and standby of the reference signal N3 times, a test start signal is transmitted from the control signal transmitting circuit 6, and after waiting for a predetermined wait period 4, the actual test process is started. At this time, the period from immediately after the slave 12 finishes transmitting and waiting for the reference signal to the time when the actual test is performed is set to the N1 test rate.

Here, N2 is selected such that N1 and N2 are relatively prime. N3 is set to be equal to or more than N1.

When the master 11 succeeds in receiving the reference signal transmitted from the slave 12, the master 11 starts executing step S 21 and attempts to receive the test start signal transmitted from the slave 12 by using the control signal transmitting circuit 6. After that, it waits for a certain wait period 2. If the reception of the test start signal has failed, the reception and the standby of the test start signal are repeated again. At this time, the reception cycle of the test start signal is N
Adjust to 2 test rates.

At this time, when the slave 12 transmits the test start signal, the master 11 can correctly receive the test start signal, and the master 11 attempts to receive the test start signal while the slave 12 is transmitting the reference signal. In this case, the master 11 does not mistakenly recognize the reference signal transmitted from the slave 12 as the test start signal.
And the transmission timing of the test start signal in the slave 12 are adjusted.

When the master 11 has successfully received the test start signal in step S12, the master 11 starts the actual test processing. At this time, the period from the beginning of the repetition period for receiving the test start signal to the start of the actual test is adjusted to be the N2 test rate.

The wait period 1 and the wait period 2 in the master 11 are set to be sufficiently longer than the period from when the reference signal and the test start signal are received to when the conditional branch is actually enabled.

Next, the process of executing a test vector in the master 11 and the slave 12 will be described with reference to FIGS. 4 and 5, which are examples of test vector configurations in the master 11 and the slave 12. However, as long as the steps S11, S12, S21, S22 can be realized, a free test vector configuration other than these test vector configurations is possible.

Hereinafter, the description will be made with reference to the time in the integrated circuit to be actually tested.

The master 11 receives the test vector address AD
Assuming that the branch in DM3 is executed unconditionally, the number of test rates N1 from test vector addresses ADDM1 to ADDM3 in master 11 is assumed.
And test vector address ADD in slave 12
Since the test rate numbers N2 from S1 to ADDS3 are relatively prime, all the test vector addresses executed from the test vector addresses ADDM1 to ADDM3 of the master 11 are set so that the slave 12 transmits the reference signal in the ADDS2 to N1. 1 time between each repetition
Test vector address ADDS1 of slave 12 each time
Executed at the same time. That is, the master 11 and the slave 12 are configured such that the slave 12
While the section from M1 to ADDM3 is looped N1 times, there is always one case where the test vector addresses ADDM1 and ADDS1 of the master 11 and slave 12 are simultaneously executed.

The actual test vectors are stored in slave 12 at test vector addresses ADDS1 to ADDS3.
Is adjusted so as to loop the section up to N3 times, that is, N1 times or more. During this time, the test vector addresses in the master 11 and the slave 12 always match at least once, and at this time, the master 11 The loop can be exited by the conditional branch at the test vector address ADDM3.

The master 11 has a test vector address AD
When the master 11 exits the loop from DM1 to ADDM3 by n1 times less than N1, the master 11 executes the section from the test vector addresses ADDM4 to ADDM6. Slave 12 has a test vector address AD
Since the section from DS1 to ADDS3 is fixed and executed only N3 times, the master 11
Even after the control is shifted to DDM4 and thereafter, the loop from the test vector addresses ADDS1 to ADDS2 is continuously executed only (N3-n2) times.

By the way, the master 11 is
When the test vector address ADDM1 of the slave 12 and the test vector address ADDS1 of the slave 12 are simultaneously executed, the test vector address ADDM4 is executed after the test vector address ADDM3. However, the master 11 has the test vector addresses ADDM1 to ADDM3.
The slave 12 needs the test vector addresses ADDS1 to ADDS1 while
Since N2 rate until DS3, master 11
Is executing the test vector address ADDM4, the slave 12 is executing the test vector address advanced from the test vector address ADDS1 by the (N1-N2) test rate.

At this time, the number of test rates from the test vector addresses ADDM4 to ADDM6 in the master 11 and the number of test rates from the test vector addresses ADDS1 to ADDS3 in the slave 12 are both N2. For this reason, while the slave 12 repeatedly executes the section from the test vector addresses ADDS1 to ADDS3, the test vector address ADDM4 of the master 11 and the test vector address ADDS1 of the slave 12 are always executed simultaneously. That is, the test vector address ADDM4 of the master 11
Is always executed simultaneously with the test vector address advanced from the test vector address ADDS1 of the slave 12 by the (N1-N2) test rate.

The slave 12 has a test vector address A
After executing the loop from DDS1 to ADDS3 only N3 times, control is transferred to the test vector address ADDS4. At this time, the test vector address A of the master 11
The test vector address of the slave 12 that is executed simultaneously with the DDM 4 is (N
1-N2) The test vector is advanced by the test rate.

Since the test vector address to be executed simultaneously by the master 11 and the slave 12 can be determined in advance, the test vector of the slave 12 is set so that the master 11 can receive the test start signal at the test vector address ADDM5. Can preliminarily adjust the test vector address ADDS5 for transmitting the test start signal.

At this time, the master 11 receives the test start signal from the slave 12 and
The process exits from the loop in the section from the test vector address ADDM4 to the test vector address ADDM6 by the conditional branch in the DDM6, and transfers control to the test vector address ADDM7.

At the same time, the slave 12 unconditionally changes the test vector address ADDS6 to the test vector address ADDS6.
Transfer control to DS7.

Test vector address AD of master 11
The test vector address of the slave 12 to be executed simultaneously with the DM4 is a test vector address advanced from the ADDS4 by the (N1-N2) test rate. Slave 12
At the time from the test vector address to the execution of the test vector address ADDS6, {N1- (N
1−N2)｝ = N2 There is a period of only the test rate. On the other hand, in the master 11, the area from the test vector address ADDM4 to the test vector address ADDM6 is the N2 test rate. Therefore, the test vector address ADDM7 of the master 11 and the test vector address ADDS7 of the slave 12 are executed simultaneously.

By the way, when N1 <N2, (N1-N
2) is a negative value. In this case, the test vector address advanced by the (N1-N2) test rate is (N2
-N1) Assume that the test vector address is as far back as the test rate. Master 11 and Slave 1
2, the test vector addresses ADDM7 and ADDM7
Since the test vector for actually testing the integrated circuit is arranged after DS7, the master 11 and the slave 12 can perform the test with the correct combination of the test vector addresses after this. .

It is not necessary that the test vector addresses are actually arranged consecutively, and they may be partially discontinuous. However, the configuration is such that only the relationship of the number of test rates in each test vector address section is maintained.

[0045]

FIG. 6 is a block diagram showing an embodiment of the present embodiment, in which constituent elements common to those in FIG. Board 2
The integrated circuit test apparatus 1 according to the present embodiment, which is shown together with a microprocessor LSI (hereinafter, microprocessor) 31 to be tested, operates two integrated circuit test machines (LSI testers) in cooperation with each other as described above. The two integrated circuit testers are called master 11 and slave 12, respectively, and are distinguished from each other.

The integrated circuit testing apparatus of this embodiment is for testing a microprocessor 31 using 294 terminals at the time of testing, and has 256 and 128 bidirectional buses as master 11 and slave 12, respectively. An LSI tester having test pins 9 is used. The master 11 and the slave 12 cannot test the microprocessor 31 alone due to the limitation of the number of test pins provided in each.

The master 11 has 256 test pins 9
Is used as the master clock output circuit 4 and one is used as the control signal receiving circuit 7.
Further, the master 11 has a conditional branch function of detecting a state of an external signal at a specific test vector address at a specific test pin during execution of a test vector, and changing the next test vector address to be executed in response thereto. . In this embodiment, the LSI tester used as the master 11 is:
From the test vector address programmed to detect the state of the external signal to the actual execution of the conditional branch,
It requires a wait period of 88 test rates.

On the other hand, the slave 12 has an external synchronization control function of executing a test vector in synchronization with a clock signal applied to a specific test pin 9, and controls one of the 128 test pins 9. External synchronous clock input circuit 5
Use as

The control signal transmitting circuit 6 of the slave 12 and the control signal receiving circuit 7 of the master 11 are electrically connected, and the transmission delay time between them is 40 nsec.

The microprocessor 31 which is the LSI to be tested needs to use 294 terminals connected to the test pins 9 for performing the test. 2 of these
Forty are connected to the test pins 9 of the master 11 and 54 are connected to the test pins 9 of the slave 12. These connections are realized via the test board 2.

A coaxial cable 1 is connected between each test pin of the master 11 and the slave 12 and the microprocessor 31.
0 and their transmission delay times are 10
nsec.

The master clock output circuit 4 and the external synchronous clock input circuit 5 are electrically connected.

The start timing of each test rate executed by each of the master 11 and the slave 12 is adjusted in advance on the test board 2 so as to match.

The microprocessor 31 has a test rate 3
Tested at 0 nsec.

First, the contents of the test vectors in the master 11 and the slave 12 will be described.

Before the actual microprocessor 31 test, the master 11 and the slave 12
The test vector address synchronization is executed according to the flowchart shown in FIG. The test vector configurations of the master 11 and slave 12 at this time are shown in FIGS.

The master 11 has a test vector address A
Execution of the test vector is started from M0.

The master 11 has a test vector address A
At M2, an attempt is made to receive a reference signal transmitted from the slave 12. When the signal transmitted at the test vector address AS1 of the slave 12 reaches the master 11 when the test vector addresses of the master 11 and the slave 12 are in agreement with each other, based on the time on the test board 2, This is because the master 11 is executing the test vector address AM2.

The master 11 has a test vector address A
In M100, if the reception of the reference signal at the test vector address AM2 has failed, a conditional branch is made to the test vector address AM0. Test vector address A
If the reception result in M2 succeeds, the test vector address AM101 and subsequent steps are executed as they are. Note that there are 98 test rates between the attempt to receive the reference signal at the test vector address AM2 and the actual execution of the conditional branch at the test vector address AM100. At this time, the restriction of 88 test rates required until the conditional branch is avoided. ing.

The master 11 has a test vector address A
At M104, an attempt is made to receive a test start signal from slave 12.

The master 11 has a test vector address A
In M200, if the reception of the test start signal at the test vector address AM104 has failed, a conditional branch is made to the test vector address AM101. If the test start signal at the test vector address AM104 has been successfully received, the control is directly transferred to the test vector address A201. After the test vector address A201, a test vector for actually testing the microprocessor is arranged. The test vector address A
There are 99 test rates between the attempt to receive the reference signal in M104 and the actual conditional branch at the test vector address AM200. In this case, too, the restriction of 88 test rates required until the conditional branch is avoided. I have.

The slave 12 has a test vector address A
Execution is started from S0.

The slave 12 has a test vector address A
In S1, a reference signal is transmitted to the master 11. Thereafter, at the test vector address AS99,
Branch to the test vector address AS0. However, test vector address AS at test vector address A99
The branch to 0 is performed only 101 times, and the slave 12 sets the test vector address between AS0 to AS99 as 101.
Test vector address AS1
Execute 00 and later.

The slave 12 has a test vector address A
In S102, a test start signal is transmitted to the master 11. Then the test vector address AS199
After a wait period, the test vector address A
Execute S200 and subsequent steps. After the AS 200, test vectors for actually testing the microprocessor are arranged.

In this test vector, the master 11 has 101 test rates from the test vector addresses AM0 to AM100, and the test vector address AM1
There are 100 test rates from 01 to AM200.

In slave 12, test vector addresses AS0 to AS99 have 100 test rates, and test vector addresses AS100 to AS1.
Up to 99 there are 100 test rates.

Next, the actual process of executing test vector address synchronization will be described.

First, prior to execution of the test vector of the slave 12, the test vector of the master 11 is executed from the test vector address AM0. At this time, Slave 1
2. Output of the master clock to the second device starts.

Immediately after the master 11 starts executing the test vector, since the slave 12 has not executed the test vector, the slave 11 does not transmit the reference signal, and the master 11 receives the reference signal at the test vector address AM2. Always fail. Therefore, the test vector address AM1
00, the test vector address A
Branch to M0.

After the master 11 starts executing the test vector and starts outputting the master clock, the test vector of the slave 12 is changed to the test vector address AS.
Execute from 0.

Since the test vectors of the master 11 and the slave 12 start execution at different times, the master 11 and the slave 11 immediately start the test vector of the slave 12 with reference to the time at the terminal of the microprocessor 31. The slave 12 may be executing different test vector addresses.

Referring to FIG. 9, this figure shows the slave 1
Immediately after the start of the test vector No. 2, the test vector addresses executed by the master 11 and the slave 12 are shifted by 8 test rates.

First, immediately after the start of execution of the slave 12 test vector, the test vector address A of the slave 12
The test vector address of the master executing at the same time as S0 is AM8.

The slave 12 has a test vector address A
In S1, a reference signal is transmitted to the master 11.
When the reference signal reaches the master 11, the master 11
Is executing the test vector address AM10, and cannot receive the reference signal at the test vector address AM2 of the master 11. Therefore, the master 11 makes a conditional branch to the test vector address AM0 at the test vector address AM100 due to the failure in receiving the reference signal. On the other hand, the slave 12 branches to the test vector address AS0 after executing up to the test vector address AS99.

In the slave 12, when the test vector address AS0 is executed for the second time, the master 11 executes the test vector address AM7 and the slave 1 executes the test vector address AM7.
Compared with immediately after the start of the execution of the test vector No. 2, the deviation of the test vector address executed by each of the master 11 and the slave 12 is reduced by one test rate.
That is, the slave 12 sets the test vector address AS0
Each time the process from A99 to A99 is executed, the master 1
The deviation of the test vector address between 1 and slave 12 is 1
The test rate decreases by one. Therefore, when the slave 12 executes the ninth test vector address AS0, the master 11 also executes the test vector address AM0, and the deviation of the test vector address between the master 11 and the slave 12 becomes zero. Has become.

Referring to FIG. 10, this figure shows the relationship between the test vector addresses executed by master 11 and slave 12 when slave 12 executes the ninth test vector address AS0.

In this state, when the reference signal transmitted by the slave 12 at the test vector address AS1 reaches the master 11, the master 11 executes the test vector address AM2 and can receive the reference signal from the slave 12. .

Therefore, in the test vector address AM100, the master 11 executes the test vector address AM101 and thereafter. At the same time, the slave 12 executes the test vector address AS99. However, since the number of repetitions between the test vector addresses AS0 and A99 has not reached 100, control is transferred to the test vector address AS0. The slave 12 then performs the processing from the test vector addresses AS0 to AS99 to 92
Execute it twice.

Here, when the master 11 is executing the test vector address AM101, the slave 12 is simultaneously executing the test vector address AS1.

Thereafter, the master 11 tries to receive a test start signal from the slave 12 at the test vector address AM103. On the other hand, slave 12 executes test vector addresses AS0 to AS100.
Considering the transmission delay time from the slave 12 to the master, in order for the test start signal to arrive at the test vector address AM103 of the master 11, the slave 1
In 2, it is necessary to output a valid signal at the test vector address AS2.

However, since the slave 12 does not output a signal to the master 11 at the test vector address AS2, while the slave 12 is executing the test vector addresses AS0 to A99, the master 11 holds the test vector address AM103. Therefore, reception of the test start signal always fails. The reference signal output from the slave 12 at the test vector address AS1 reaches the master 11 at the test vector address AM102 of the master 11, but the master 11 transmits the test vector address A1.
In 02, no attempt is made to receive any signal transmitted from the slave 12, so that the reference signal is not erroneously recognized as the test start signal.

Thereafter, the master 11 executes up to the test vector address AM200. Here, when the reception of the test start signal fails, the master 11 branches to the test vector address AM101.

The slave 12 has a test vector address A
The process branches to the test vector address AS0 until the process between S0 and AS100 is repeated 100 times.
Therefore, when the master 11 executes the test vector address AM101 for the second time, the slave 12 executes the test vector address AS0, but the combination of the test vector addresses is such that the master 11 executes the test vector address 101 for the first time. Same as when executed. That is, when the master 11 has the test vector address A
While M101 to AM200 are being executed and the slave 12 is executing the test vector addresses AS0 to AS99, the combination of the test vector addresses executed by the master 11 and the slave 12 does not change. Therefore, during this period, the master 11 always fails to receive the test start signal from the slave 12 and does not erroneously recognize the reference signal transmitted from the slave 12 as the test start signal.

Referring to FIG. 11, after the slave 12 executes the test vector address A99 100 times, each test of the master 11 and the slave 12 in a state where the test vector address to be executed next is moved to the AS100. This shows how the vector is executed. At this time, the master 11 is executing the test vector address AM101.

After that, the slave 12 transmits a test start signal to the master 11 at the test vector address AS102. When the test start signal reaches the master 11, the master 11 sends the test vector address AM1
03, the master succeeds in receiving the test start signal from the slave for the first time.

The master 11 has a test vector address A
Due to the successful reception of the test start signal in M103,
In the test vector address AM200, the next test vector address to be executed is AM201. When the master 11 is executing the test vector address AM200, the slave 12 is simultaneously executing the test vector address AS200, and thereafter, the slave 11 transfers the test vector address to be executed next to the AS 201.
That is, at this time, the master 11 and the slave 12 simultaneously transmit the test vector addresses AM201 and AS201.
Start running.

After the test vector addresses AM 201 and AS 201 of the master 11 and the slave 12, test vectors for actually testing the microprocessor 31 are respectively arranged. The microprocessor 31 is tested by the combination of the vectors.

In this embodiment, the master clock output circuit 4, the external synchronous clock input circuit 5, the control signal transmission circuit 6, and the control signal reception circuit 7
Although the test pins 9 of the I tester are diverted, some or all of them may be realized as other independent dedicated circuits.

Next, a second embodiment of the present invention will be described with reference to FIG. 12 in which constituent elements common to those in FIG. The difference between the integrated circuit test apparatus 1A of the present embodiment and the integrated circuit test apparatus 1 of the first embodiment is that the master 1
1A, instead of the master clock output circuit 4, a master clock output circuit 4A configured to control the output and stop of the master clock independently of the execution and stop of the test vector in the master 11, and a control signal receiving circuit 7 , And the slave 12A includes a control signal receiving circuit 7 instead of the control signal transmitting circuit 6.

In this embodiment, since the master 11 can start outputting the master clock prior to the execution of the test vector, it is possible for the master 11 to start executing the test vector of the slave 12 before executing the test vector. It becomes possible. Therefore, in this embodiment, the roles of the master 11 and the slave 12 in the test vector in the first embodiment can be exchanged with each other.

That is, an integrated circuit tester having no conditional branch function is used as the master 11A, and the slave 1
As 2A, an integrated circuit tester having a conditional branch function can be used. Accordingly, the control signal transmitting circuit 6 and the control signal receiving circuit 7 also
The configuration is interchanged between 1A and slave 12A.

In this embodiment, the test of the integrated circuit 3 is performed by the same step S as in the first embodiment of the present invention, except that the test vector start order of each of the master 11A and the slave 12A is reversed. Can be.

Next, a third embodiment of the present invention will be described with reference to FIG.
Referring to FIG. 13 which is similarly denoted by a block with common reference characters / numbers attached to the same components as those of FIG. 13, the integrated circuit test apparatus 1B of the present embodiment shown in FIG. The difference from the integrated circuit test apparatus 1A of this embodiment is that the number of integrated circuit test machines to be slaves 12A is expanded to M, and slaves 12A1, slaves 12A2,..., Slaves 12Am,. It is to have. In the present embodiment, each slave 12Ai (i
1 to M) are connected to the control signal transmission circuit 6 of the master 11A.

Here, the test vector address ADDSx in the m-th slave 12Am is denoted as ADDSxm.

In the present embodiment, slave 12 Am
Test vector addresses ADDS1m to ADDS3m
All test rates up to N1. Test vector address ADDM1 to ADDM of master 11A
The test rate numbers N2 and N1 up to 3 are all chosen to be relatively prime.

The master 11A receives the test vector address A
During the execution of N2 times from DDM1 to ADDM3, all the slaves 12Ai succeed in receiving the reference signal from the master 11A. Therefore, when the master 11A executes the test vector address ADDM4 after executing the test vector address ADDM1 to ADDM3 N2 times, all the slaves 12Ai perform the test vector address ADM.
The same test vector address is executed from the DDS4 by (N1-N2).

Therefore, by performing the subsequent step S in the same manner as in the second embodiment, test vectors for actually testing the integrated circuit 3 are arranged in the master 11A and the M slaves 12A. The execution of the test vector addresses ADDM7 and ADDS7m can be started simultaneously, and the integrated circuit can be tested with the correct combination of test vector addresses.

Although the embodiments of the present invention have been described above, it is apparent that the present invention is not limited to the above embodiments, and that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. It is.

[0099]

As described above, according to the integrated circuit test apparatus and the test method of the present invention, the master can transmit the reference clock signal to the slave, receive the state control signal from the slave, and read the state of the state control signal. An execution procedure changing means for changing the execution procedure of the test program at any time in response to the above, wherein the slave comprises a reference clock signal reception means, a synchronization control means, and a state control signal transmission means; When the integrated circuit testers are connected to each other and operated in cooperation with each other to be used as one integrated circuit tester, some of the integrated circuit testers do not need to have a conditional branch function, and furthermore, the control signal There is an effect that the number of lines can be configured only by the number equal to the number of slaves.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an integrated circuit test apparatus according to the present invention.

FIG. 2 is a flowchart illustrating an example of processing of a test program in a master according to the present embodiment.

FIG. 3 is a flowchart illustrating an example of processing of a test program in a slave according to the present embodiment.

FIG. 4 is a diagram showing an example of a configuration of a test program in a master of the present embodiment.

FIG. 5 is a diagram showing an example of a configuration of a test program in a slave according to the present embodiment.

FIG. 6 is a block diagram showing an example of the integrated circuit test device of the present embodiment.

FIG. 7 is a diagram illustrating an example of a configuration of a test program in a master according to the present embodiment.

FIG. 8 is a diagram illustrating an example of a configuration of a test program in a slave according to the present embodiment.

FIG. 9 is a diagram illustrating a relationship between test vector addresses immediately after the start of a test program in a master and a slave according to the present embodiment.

FIG. 10 is a diagram showing the relationship between the master and slave test vector addresses immediately after the slave of the present embodiment has completed the first step S.

FIG. 11 is a diagram showing the relationship between the master and slave test vector addresses immediately after the slave of the present embodiment completes the second step S.

FIG. 12 is a block diagram showing a second embodiment of the integrated circuit test apparatus of the present invention.

FIG. 13 is a block diagram showing a third embodiment of the integrated circuit test apparatus of the present invention.

FIG. 14 is a block diagram illustrating an example of a conventional integrated circuit test apparatus.

FIG. 15 is a flowchart illustrating an example of processing of a test program in a master of a conventional integrated circuit test apparatus.

FIG. 16 is a flowchart illustrating an example of processing of a test program in a slave of a conventional integrated circuit test apparatus.

[Explanation of symbols]

 1, 1A, 1B, 100 Integrated circuit test apparatus 2 Test board 3 Integrated circuit 4, 4A, 40 Master clock output circuit 5, 50 External synchronous clock input circuit 6, 61, 62 Control signal transmission circuit 7, 71, 72 Control signal Receiving circuit 8,80 Control system 9 Test pin 10 Coaxial cable 11,11A, 110 Master 12,12A, 120 Slave 31 Microprocessor

Claims (7)

[Claims] 1. An integrated circuit test apparatus in which first and second integrated circuit testers each functioning independently are defined as a master and a slave, and operate in cooperation with each other to function as one integrated circuit tester. A reference clock signal transmitting unit for transmitting a reference clock signal to the slave, a state control signal receiving unit for receiving a state control signal transmitted from the slave, Execution procedure changing means for changing the execution procedure of the test program at any time in accordance with the state, wherein the slave is electrically connected to the reference clock signal transmission means and is sent from the master. Reference clock signal receiving means for receiving the reference clock signal; and And synchronization control means for synchronizing operation with respect to terpolymer, the state control signal receiving means is electrically connected to,
An integrated circuit test apparatus comprising: a state control signal transmitting unit configured to transmit the state control signal to the master. 2. The master first starts a master test program, whereby the master sends a reference clock signal to the slave, and the master starts sending the reference clock signal to the slave. After the slave initiates a slave test program, the master determines whether a state control signal is transmitted from the slave at a predetermined timing.
Is repeated with a predetermined first number of test rates as a cycle. If the determination is true, the second procedure is performed after the first number of test rates from the beginning of the repetition step. When the state is false, the first step is repeated. In the second step, the master 1 determines whether or not the state control signal is transmitted from the slave at a predetermined timing. If the determination is true, the actual integrated circuit test step is performed after the second number of test rates from the beginning of the second step. When the determination is false, the second step is repeated, and the slave first performs state control on the master at a predetermined timing. A first state control signal is transmitted from the signal transmission means, and the first state control signal is repeated at least for the first several times with the second number of test rates as a cycle. Then, the state is transmitted to the master at a predetermined timing. A second state control signal is transmitted from the control signal transmitting means, and the second state control signal is transmitted for one cycle with the first number of test rates as a cycle.
The first number and the second number are in a prime relationship with each other, and in a second step in the master, the master When attempting to receive a state control signal, the transmission timing of each of the first and second state control signals is determined in advance so that the first state control signal transmitted from the slave is not erroneously received. The integrated circuit test apparatus according to claim 1, wherein: 3. An integrated circuit test apparatus in which first and second integrated circuit testers each functioning independently are defined as a master and a slave, respectively, and cooperate with each other to function as one integrated circuit tester. A slave receiving means for receiving a reference clock signal sent from the master; a synchronization control means for performing a synchronization operation on the master by the reference clock signal; State control signal receiving means for receiving the received state control signal, and execution procedure changing means for changing the execution procedure of the test program as needed in accordance with the state of the received state control signal, A master is electrically connected to the reference clock signal receiving means, and the master receives the reference clock signal with respect to the slave. A reference clock signal transmitting means for transmitting a click signal, the state control signal receiving means is electrically connected to,
State control signal transmitting means for transmitting the state control signal to the slave, the reference clock signal transmitting means, independently of the execution of the test program in the master, transmission and stop An integrated circuit test device characterized by being controllable. 4. The master first starts transmitting a reference clock signal to the slave before executing the master test program on the master before executing the slave test program on the slave. The slave starts execution of the slave test program prior to execution of the master test program on the master, and thereafter, the master starts execution of the master test program. First to determine whether or not to be transmitted at the specified timing
Is repeated with a first number of test rates as a cycle. If the determination is true, the process proceeds to the second step after the first number of test rates from the beginning of the repeating step, If false, the first step is repeated, and the slave determines whether the state control signal is transmitted from the master at a predetermined timing in the second step. The steps are repeated using a second number of test rates as a cycle. If the determination is true, the process proceeds to the actual integrated circuit test step after the second number of test rates from the beginning of the second step. If the determination is false, the second step is repeated, and the master first controls the slave at a predetermined timing. A first state control signal is transmitted from the signal transmitting means, and the first state control signal is repeated for a first number of times or more with a second number of test rates as a cycle. Then, the state control signal is transmitted to the slave at a predetermined timing. A second state control signal is transmitted from the transmitting means, and the second state control signal is transmitted for one cycle with the first number of test rates as a cycle.
The first number and the second number are in a disjoint relationship; and in the second step in the slave, the slave is the second The transmission timing of each of the first and second state control signals is determined in advance so as not to erroneously receive the first state control signal transmitted from the master when attempting to receive the state control signal. The integrated circuit test apparatus according to claim 3, wherein: 5. An integrated circuit functioning as one integrated circuit tester by defining one of three or more integrated circuit testers each functioning independently as a master and the other as a slave, and operating in cooperation with each other. In the test apparatus, each of the slaves may include a reference clock signal receiving unit configured to receive a reference clock signal transmitted from the master, and a synchronization control for performing a synchronization operation on the master using the reference clock signal. Means, state control signal receiving means for receiving a state control signal sent from the master, and execution procedure for changing the execution procedure of the test program as needed in accordance with the state of the received state control signal Changing means, wherein the master is electrically connected to the reference clock signal receiving means, Wherein the reference clock signal transmitting means for transmitting a reference clock signal, the state control signal receiving means is electrically connected to the hand,
State control signal transmitting means for transmitting the state control signal to the slave, the reference clock signal transmitting means, independently of the execution of the test program in the master, transmission and stop An integrated circuit test device characterized by being controllable. 6. A master first starts transmitting a reference clock signal to said slaves before executing a master test program on said masters prior to execution of a slave test program on all slaves. Next, the slave starts execution of the slave test program prior to execution of the master test program on the master, and then the master starts execution of the master test program, m (positive integer) ) -Th slave performs a first step for determining whether or not a state control signal is transmitted from the master at a predetermined timing.
If the determination is true, the second test rate after the m-th first test rate from the beginning of the repetition procedure
And if false, repeat the first step. In the second step, determine whether the master transmits the state control signal at a predetermined timing in the second step. Is repeated with a second number of test rates as a cycle, and if the determination is true, the actual integration after the second number test rate from the beginning of the second step The process proceeds to a circuit test step, and when the determination is false, the second step is repeated, and the master first transmits a state control signal to all the slaves at a predetermined timing. 1 and is the least common multiple of the m-th first number in all the slaves, with the second number of test rates as the period. A second state control signal is transmitted from the state control signal transmitting means to the slave at a predetermined timing at a predetermined timing, and the second state control signal is transmitted at a predetermined timing. As one
And then proceed to the actual integrated circuit test step, where the m-th first number and the second number are coprime in all slaves, and the second in the slaves In the step, when the slave attempts to receive the second state control signal, each of the first and second state control signals is set in advance so as not to receive the first state control signal transmitted from the master by mistake. 6. The integrated circuit test apparatus according to claim 5, wherein the transmission timing is determined. 7. An integrated circuit functioning as one integrated circuit tester by defining one of two or more integrated circuit testers functioning independently as a master and the other as a slave, and operating in cooperation with each other. In the test apparatus, the slave repeats a first step of determining whether a state control signal is transmitted from the master at a predetermined timing with a first number of test rates as a cycle, and the determination is true. If it is, the process proceeds to the second step after the first number of test rates from the beginning of the repetition step, and if false, the first step is repeated, and the slave is A step for determining whether the state control signal is transmitted from the master at a predetermined timing in the second step. If the determination is true, the actual integrated circuit test step is performed after the second number of test rates from the beginning of the second step. When the determination is false, the second step is repeated, and the master firstly transmits the first state control signal from the state control signal transmitting unit to the slave at a predetermined timing. And repeating this at least the first several times with the second number of test rates as a cycle. Next, the state control signal transmitting means transmits the second state to the slave at a predetermined timing. A control signal is transmitted, and the control signal is set to 1 for a cycle of the first number of test rates.
The first and second numbers are in a prime relationship with each other, and in the second step of the slave, the slave is the second When attempting to receive the state control signal, the transmission timing of each of the first and second state control signals is determined in advance so that the first state control signal transmitted from the master is not erroneously received. ,
An integrated circuit test method, wherein a test of an integrated circuit is performed after matching timings of test operations in all the integrated circuit test machines.