JP2000507774A - High-speed programmable logic architecture - Google Patents

Abstract

SUMMARY An architecture for a programmable logic device that can operate at a clock rate substantially faster than current programmable logic devices is described. Instead of using passive circuit elements to interconnect the programmable logic elements (20) and the input (12) and output (15) data buses, controllable active driver circuits (52, 53) are used. These circuits eliminate substantially all the resistance present in conventional passive connections.

Description

DETAILED DESCRIPTION OF THE INVENTION High-speed programmable logic architecture BACKGROUND OF THE INVENTION Regarding programmable logic, In particular, Using active driver circuits in an interconnect array; High-speed programmable logic architecture. What is a programmable logic device (PLD)? The user of the circuit uses software control to It is possible to customize the logic function performed by the circuit, It is a programmable integrated circuit. Formerly small, During, And the logic functions implemented by large-scale integrated circuits Currently, It can be implemented by a programmable logic device. PLD is Current, About 50 per integrated circuit, It has a capacity on the order of 000 gates. When a typical programmable logic device is supplied by an integrated circuit manufacturer, It cannot yet perform any specific functions. But, The user Similarly, typically in combination with software supplied by a programmable logic device manufacturer, Program the PLD, It is possible to perform a specific function or a function necessary for the user's application. Then PLD is As if a dedicated logic chip was used, It is possible to work with large systems designed by the user. With this functionality, The user Without leaving the time or expense of custom chips or gate arrays, It is possible to debug system logic. This functionality also Small production runs and hardware customizations can be tailored to very specific applications. In some PLDs, The logic can be changed "on-the-fly", This allows the PLD to While the system is running, At one point, they perform one function, Thereafter, another function can be performed. A typical PLD is Consists of an array of identical logic cells. This logic cell is Can be programmed individually, And optionally interconnected with each other to provide internal input and output signals; This allows for the implementation of very complex combinations of continuous logic functions. The program is By setting the state of a programmable element, such as a memory cell, Implemented in PLD. One type of programmable logic, known as a programmable logic array (PLA), is: A combination two-level AND / OR integrated circuit that can be programmed to implement product-sum logic. Such devices are: Typically, A series of AND gates having input terminals that can be programmably connected to the chip input signal; A series of OR gates that can be programmably connected to receive the output signal from the AND gate. Another type of programmable logic device is Known as Programmable Array Logic (PAL). PAL is Uses a fixed OR array and bidirectional input / output pins. The disadvantages of both PAL and PLA are: They are a lack of density that can be programmed. In other words, Arrays can perform many logic functions, The use of the array is not as complete as desired. further, The dimensions of the array It grows faster than its programming ability. The response to this assignment is It was a "macrocell" or logic block in a programmable logic device. Macro cells or logic blocks are It can perform many different functions, In addition, it is a subsection of logic that can be selectively interconnected to another macrocell or logic block. This allows The logic in a programmable logic device is Logic strips communicate with other strips, It is possible to assume a more granular structure, Also, It is possible to provide an overall more efficient use of the integrated circuit. here, Using the phrase "programmable logic device" Programmable array logic, Programmable logic array, Field programmable gate array, And other types of programmable logic devices. A notable disadvantage of all currently available programmable logic devices is that It is relatively slow. In all of the above programmable logic devices, Connection inside AND and OR arrays, And the connection to and from the macrocell, Erasable programmable read-only memory cells, Electrically erasable read-only memory cells, Static random access memory cells, fuse, Alternatively, this is performed using an antifuse or the like. In each of these cases, The interconnect approach is passive. That is, The state of the memory cell or fusible connection is By itself, Used to control any other device that makes or breaks a connection between two nodes. All of these connections The signal provided to the connection simply passes through the connection (or does not pass if the connection is open) Be passive. as a result, The overall speed of a programmable logic device is Limited by the reasons discussed below. Even the fastest prior art large field programmable gate arrays available at the moment, Operates at 50 mhz or slower. Some small transistor-transistor logic (TTL) devices are: It is possible to operate at speeds higher than 100 MHz. At the moment, No one produces large high-speed arrays. One of the main reasons for the relatively slow operating speed of prior art programmable logic devices is that The resistance present in the interconnect system. The interconnect system Programmable "wiring" With this wiring, Logic signals are propagated across integrated circuit chips. This propagation speed is The transfer gate used is an EPROM cell, SRAM cells, Whether formed as an antifuse or other, Limited by the series resistance of the transfer gate. as a result, Manufacturers of prior art programmable logic devices In the technical choice of transfer gate, There has been a choice between resistance and capacitance. As described above, In a typical prior art programmable logic device, The logic is Implemented in logic blocks that communicate with each other. Such a logic block is When combined with a transfer gate, Almost 1, Has an effective driving resistance of the order of 000 ohm plus the resistance of the driver circuit. For example, in antifuse technology as implemented by Actel Corporation, The effective driving resistance is Each connection is on the order of 50-500 ohms plus the resistance of the driver circuit. As described below, The technology of the system of the present invention The effective driving resistance is simply, This is the resistance of the driver circuit. SUMMARY OF THE INVENTION An architecture has been developed for a programmable logic device that can operate at substantially higher speeds than conventional programmable logic devices. In a preferred embodiment of the system of the present invention, Using the programmable logic techniques of the system and currently available silicon semiconductor technology, Speeds up to 500 mHz are feasible. In one embodiment of the present invention, A routing structure is provided for a programmable logic circuit including a logic cell that performs a logic function. The routing structure is Supply signals processed by the logic cells, An input line set extending substantially in a first direction; Receive the signal processed by the logic cell, An output line set extending substantially in the second direction. Where the input and output lines intersect, Programmably connect between a selected line of the output line set and a selected line of the input line set; Or by not connecting A signal present on the output line can be arranged on a desired line of the input lines, A junction area containing a controllable active driver circuit is established. Each of the controllable driver circuits is at least, An active state where the driver circuit duplicates the signal supplied to it, or A buffer circuit that can be made passive to provide high impedance between the input and the output. Typically, The controllable driver circuit is Each output line in the set can be connected to any desired line in the input line set. In another embodiment, The system of the present invention Includes a structure similar to the above structure, further, A controllable driver circuit set for selectively interconnecting desired ones of input and output lines to logic cells is provided. This allows The input signal present on the input line is Can be supplied to the appropriate node of the logic cell, Further, an output signal from the logic cell can be supplied to another desired logic cell or another circuit. In connection with the system of the present invention, The controllable driver circuit also It can be used in interface circuits between pins of an integrated circuit and a set of input and output lines. With controllable driver circuit, Allows the desired connection between the pins of the integrated circuit and the input and output buses, This allows Supply the desired signals present on the pins of the chip to the appropriate logic cells, Similarly, outputs from these logic cells can be applied to appropriate pins. By using an active circuit, such as the controllable driver circuit described herein, The programmable logic device of the system of the present invention comprises: It can operate substantially faster than conventional devices. Using the conventional technology 1993 semiconduct or technology, The upper limit of the clock speed at which a programmable logic device can operate is: 50 mHz. Programmable logic devices manufactured using the techniques of the present invention include: It can operate at speeds up to 500 mHz. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the overall layout of an integrated circuit using the programmable logic device architecture of the present invention. FIG. Supplying an input signal to the logic cell of the present invention, FIG. 4 is a schematic diagram showing a method of receiving an output signal from the logic cell. FIG. FIG. 2 is a schematic diagram illustrating one embodiment of a circuit for interconnecting input / output buses and integrated circuit input / output pins. FIG. FIG. 4 is a schematic diagram illustrating another embodiment of a circuit for interconnecting input / output buses and integrated circuit input / output pins. FIG. How the driver circuit works Along with techniques to reduce the number of interconnects between logic cells and input or output buses, Indicates whether it can be used on an input or output bus. FIG. 5 illustrates another technique for reducing the number of connections. FIG. The interconnection between the input and output buses is FIG. 2 is a schematic diagram of a circuit that can be used, for example, to provide at the locations where they intersect. FIG. Shows two unidirectional bus lines. FIG. Shows bus lines that can be unidirectional in either direction. FIG. 4 shows a bus line divided using a controllable driver circuit. FIG. It is a schematic diagram of a circuit of one logic cell. FIG. FIG. 2 is a detailed circuit schematic diagram of a preferred embodiment of a logic block used in FIG. 1. And FIG. 1, shown in block form in FIG. FIG. 2 is a block diagram of a small portion of the overall programmable logic device. Description of Specific Embodiment FIG. Manufactured according to a preferred embodiment of the present invention; FIG. 2 is a block diagram illustrating an overall layout of a high-speed programmable logic device. As shown in FIG. This device is A first set of routing channels 12 arranged in a generally east-west direction; A second set of routing channels 15 arranged in a substantially north-south direction; A series of logic cells 20 arranged inside a matrix of routing channels. In the conventional method of operation of a programmable logic device, The routing channel is Providing an input signal to a logic cell and receiving an output signal therefrom; Including conductor bus. often, The output signal from the logic cell is Used as an input signal to another logic cell. As we all know, Each logic cell is For the input signal supplied to the logic cell, Combined or continuous, Or both, Perform any desired operations. The specific logic functions performed by the logic cells are: It typically depends on its programmed state to be "loaded" into the cell using external circuitry. This state is Is defined using control bits from an external device, Multiplexer, flip flop, Set the gate and so on. In the general block diagram of FIG. The logic cell 20 Receiving an input signal from the bus 12, In addition, an output signal is supplied to the bus 15. The input signal is The signal is transmitted from the bus and supplied to the logic cell by the conductor 23. Also, The output signal obtained is It is supplied to output bus 15 using conductor 27. As described below, These conductors The input node of the logic cell is connected to the selected line on the input data bus 12; Or in the sense that it is disconnected As such, it may be programmable. not to mention, As mentioned above, The input data bus itself Output information from other logic cells may be carried as signals. The connection between the input data bus and the output data bus is These buses may be made at locations 30 where they cross each other. The bus is Although they are drawn to cross each other in the drawing of FIG. 1, In actual execution, They are formed on integrated circuits using different metal layers or other conductive materials, And unless the electrical connection between them is "programmed" They are electrically insulated from each other. The manner in which the conductors can be joined together at the intersection region 30 is Further described below. The advantages of the structure of the present invention are: That is, the present invention is modular. As shown inside the dashed line 40, In a preferred embodiment of the present invention, Essentially all of the integrated circuit area, Buses 12 and 15, Logic cell 20, And the interconnection of buses 23 and 27, Provide signals to logic cells, And is exhausted by the regular module 40 receiving signals from the logic cells. This modular structure Facilitates efficient layout of integrated circuits. As shown in the figure, In this way, The output of each logic cell is It extends over the entire vertical length of the chip layout. The output bus is Extends along only one side of the logic cell, Then stop at the edge of the chip. But, The input bus is "Wrap" around the integrated circuit. For example, Buses 12a and 12b Connected at the east or west end of the circuit. in this way, The input bus is It extends in a meandering manner across the entire surface of the circuit. In this way, A bus 12a is connected to the bus 12b at either the east or west edge of the chip; Then Bus 12b is coupled to bus 12c at an edge such as the opposite side. Input and output buses Preferably it is unidirectional. For example, In the implementation of emitter coupled logic (ECL), Alternatively, in the implementation of complementary MOS (CMOS), The bus is The shortest segment is one-way, By insulating the segments from each other as described below, Different segments of the common bus can be made bidirectional. Bus length, Input / output signal strength, And depending on other factors, It may be desirable to use a "repeater" inside the bus. These repeaters are It consists of a small amplifier to isolate the capacitance of the circuit, This reduces the signal propagation delay, Improve overall system speed. FIG. Between the logic cell 20 and its input bus 23, And a more detailed diagram of the interconnection system between the logic cell 20 and its output bus 27. Any desired number of inputs and outputs can be Provided to the logic cell, It is to be understood that they are provided from logic cells. The drawing in FIG. A general approach to the formation of these interconnects and the programmable control of the connections is shown. As shown in FIG. The input bus 12 Using controllable driver circuits 52 and 58, It has a series of conductors that can be selectively connected to the input node 41 of the logic cell. The drawing is Although each conductive line of bus 12 is shown as being separately connectable to input node 41, this is, It is for illustration purposes only. In a practical implementation of the circuit of the invention, As will become apparent in connection with the discussion of logic cell fabrication below, Each input node is It does not need to be connected to every line on the bus. In any case, In the drawing, Each bus line of the bus 12 They are separately connected via a driver circuit. The driver circuit is Operate under the control of an input signal provided to it on line 54; Serves as a programmable tri-state buffer. Line 54 is Coupled to a register or other means. Inside a register or other means, A program for controlling the entire programmable logic device is stored. This register, memory, A separate bit in a fuse or other means Used to control a corresponding one of the programmable connections of the drawing of FIG. The other bits are Used to control other programmable connections elsewhere in the programmable logic device. In this way, The control memory is Typically, The same number of programmable connections to be controlled, Has bits stored in memory. not to mention, The two configurations are mutually exclusive and one is Or only one, If always provided, The complementary state of a single bit can control the two configurations. Under control of the memory bits, The circuit 52a is Either active or high impedance state. If input 54a is available, The circuit 52a is The signal coupled to the input node 57a is repeated. In other words, If Logical 1 is on conductor 12a of bus 12, The input node 57a of the driver 52a is Logical 1. Assuming control line 54a is available, The output from the driver 52a is also logical 1. not to mention, The same condition, This is true if Logical 0 is present on conductor 12a. Each of the drivers 52 Works in the same way. On the contrary, If the control line 54 is not available, The driver circuit is Provides a high impedance state, In addition, it functions as an open circuit. In other words, Node 55 is It is completely disconnected from the bus 12. This allows The input node 41 is If the input node does not receive a signal from bus 12, It can be disconnected from the bus 12. In some embodiments of the present invention, Another driver circuit 58 is provided between node 55 and node 41. This additional circuit It can be used to help reduce the capacitive load on input node 41. Although not shown in FIG. 2, Each of the other input nodes to the logic cell 20 Similarly, it is coupled to input signal bus 12. The output signal bus 15 Using a similar technique, Coupled to logic cell 20. As shown in the figure, The logic cell is An output node 48 supplied to an arbitrary driver circuit 59 is provided. The circuit 59 is For the same reasons as circuit 58, That is, it is provided to reduce the capacitive load on the logic cell and the circuit requirements. For logic cells that have enough output drive power to drive large capacity, The driver circuit 59 is unnecessary. The output from circuit 59 is Each operating under program control using the information provided on the corresponding line 51; It is coupled to the input of driver circuit 53. Line 51 is A single shift register element, Memory cells, Or it may be connected to other storage units. The controllable driver circuit 53 includes: It functions in the same way as circuit 52. That is, The driver circuit 53 Drive the corresponding output bus lines with the signals provided at their input nodes, or Or provide a high impedance condition to the output bus. In the high impedance state, Signals provided by the logic cells are prevented from affecting the state of certain bus conductors. in this way, The overall output connection 27 (shown in FIG. 1) The opposite of input connection 23 (shown in FIG. 1). In another embodiment of the present invention, Circuit 52, 53, 58, And 59 are It can be replaced by a multiplexer. in this case, The control lines 51 and 54 are Supply control signal to select from multiplexer input line, Connect the appropriate one to the logic cell. FIG. 2 shows the routing structure of a preferred embodiment of the present programmable logic device in more detail. What is shown in FIG. The signal provided at the input / output pins of the integrated circuit is Supplied to the interconnecting input and output buses of the programmable logic device, Also, That is how it is received. As shown in FIG. Two example I / O pins 60 and 61 are: Similarly, via the circuit 62, Connected to input / output bus 12 or 15. In the drawing, The bus is shown extending north and south, The depicted circuit is Whether the bus is an input bus 12 or an output bus 15, It should be understood that the same function can be performed. further, Each input / output pad 60 is By simply repeating the structure shown in FIG. It is possible to couple to both input and output buses. in this way, The input connection 60 A driver circuit 62a, 62b, .. Can be connected to any one of the lines 12. This allows The input signal provided at pad 60 is It can be placed on a bus 12 that supplies any one of the logic cells of the integrated circuit. Similarly, An output driver circuit 64a, 64b, Etc. Signals provided on the bus can be transmitted from the bus to the output pads. As mentioned above, The depicted structure shows only the output bus, The connection to the input bus can be realized by repeating the entire structure of FIG. not to mention, Any number of input and output pins can be used as desired. FIG. FIG. 4 illustrates another approach to the interconnection between the input / output pads and the bus. As shown in FIG. Input buses 12a and 12b It extends in a meandering manner through the input / output pads 60 and 61. In contrast, Output buses 15a and 15b It passes vertically through I / O pads 60 and 61. I / O pad 60 Using the programmable driver 65a, It is possible to selectively connect to the output bus 15a. Also, I / O pads 60 and 61 To the bus 12a via the driver 65b; And it is also possible to selectively connect to the bus 12b via the driver 65c. In a similar way, Input / output pad 61 Can be connected to drive output bus 15b using driver 67a, And using the drivers 67b and 67c respectively It can be connected to receive signals from either bus line 12a or bus line 12b. In this configuration, The input acts like a cell output, Become a part of bus 15 which looks different, The input pad to the chip can then be considered as an output from an external source on the chip. FIG. 5 illustrates another aspect of the input and output buses of the system of the present invention. As shown in FIG. Bus 12, For example, the input bus It extends across the top of the figure. The input bus 12 It is coupled to logic cell 20 using the same technique as shown in FIG. But, For simplicity, The driver circuit in the local bus 23 between the input bus 12 and the logic cell 20 is not shown. These are deployed in the manner described above. Also, As an example, The input terminal 41 to the logic cell 20 It is shown that not all lines of the input bus 12 can be connected. It is desirable to provide a connection between each input line and each input node of each logic cell, In practice this is unnecessary. By simply deploying sets and subsets of connections between buses and logic cells, More efficient designs may be possible. For example, The logic cell 20a An input node 41a connectable to the bus lines 12a and 12c, And having an input node 41b connectable to bus lines 12b and 12n. On the contrary, The logic cell 20b An input node 41c connectable to the bus lines 12a and 12b, Node 4 1d It can be connected to the bus lines 12c and 12n. Therefore, If the logic function is performed using only the data on lines 12a and 12b as input signals to logic cell 20, Logic cell 20a can be used for this function (and can be selected by software for this task). By using the logic cell 20a, Cell input 41a can receive an input signal on line 12a; on the other hand, Input 41b can receive an input signal on line 12b. Another feature of the system of the present invention shown in FIG. The use of a controllable driver circuit in the bus line itself. If the bus line can extend across the entire chip surface without interruption, The output driver of the cell has a very high capacitive load. With this high capacity, The driver driving the input signal consumes extra power, The result is that the operation of the driver is undesirably slow. to solve this problem, Driver circuits 70 are provided at selected intervals along the bus line. Although shown in connection with the input bus 12, The same technique is used on output bus 15. In FIG. These driver circuits are It is shown as being arranged every two logic cells along the bus. The actual number of driver circuits in a particular design is space, speed, And flexibility. In the embodiment shown in FIG. Some driver circuits 70 are made programmable, Other circuits 71 are not programmable. The circuit 71 is provided in an always-on state. That is, Whatever signal is provided to the input node, the signal is reproduced at the output node. But, The circuit 70 is made programmable and controllable, The same circuit as the controllable driver circuit can be used. Each of the circuits 70 The circuit described above, For example, it is similar to the driver circuits 52 and 53 of FIG. Because the circuit can be in a high impedance state, It is possible to split the input bus (or output bus) into smaller "parts". For example, The function of the bus line 12a is If simply providing an input signal to node 41a of logic cell 20a, The driver circuit 70d can be turned off. This allows Whatever drive circuit drives the bus line 12a, There is no need to drive an extra capacitance of the bus line beyond the driver circuit 70d. further, The portion of the bus line 12a beyond the driver circuit 70d is used for other purposes. For example, it can be used to function as a "local" connection between two logic cells. FIG. 4 shows a further improved example of the routing structure of the system of the present invention. As shown in FIG. Some output nodes 41a from the logic cell 20 are: A dedicated connection to output bus line 15a may be provided. at the same time, Other connections from logic cells, For example, The output 41b is The controllable driver circuit 53 may be used to provide a controllable or programmable connection to the output bus line 15b. This eliminates unnecessary driver circuits, The design can be optimized to fit the provided logic function class. In a typical embodiment of the system of the invention, Some connections are As shown in node 41a, Attached without providing a driver circuit, on the other hand, Other connections are As shown at node 41b, A programmable connection may be used. FIG. FIG. 2 shows the bus interconnect area 30 shown in FIG. 1 in more detail. The figure shows Three output bus lines 15a, 15b, And 15n, And five input bus lines 12a, 12b, 12c, 12d, And 12n. With the programmable driver circuit as described above, Any output bus can be connected to any input bus. For example, Assume that it is desired to provide output information on bus line 15b to input bus 12d. To achieve this, Circuit 80b is programmed on, As a result, the state of the bus 15b is duplicated at the node 85. further, The circuit 83d is programmed on, As a result, the state of the node 85 is passed to the input bus 12d. All other programmable driver circuits 83 Programmed off in each high impedance state, Information at node 85 is not sent to any of the other bus lines. Also, As an example, The output bus line 15a is connected to the input bus line 12a, 12b, . . . , 12n. To accomplish this, circuit 80a may be programmed off with all circuits 82. Thus, the output bus 15a can be isolated from the input bus 12. In this way, the desired output bus can be coupled to the desired input bus. Figures 8a, 8b and 8c show an improved routing structure of the system of the present invention. In the above preferred embodiment of the system of the present invention, the bus is unidirectional. Thus, without other changes, the system needs to have a bus in each direction, even with maximum flexibility. For example, the input bus 12 needs to have some lines with driver circuits that allow eastbound signal propagation, and some lines with driver circuits that allow westbound signal propagation. . FIG. 8a shows one example having a bus line 12a for propagating signals to the right and a bus line 12b for propagating signals to the left. FIG. 8b illustrates a variation of the above technique in which a controllable driver circuit is used to segment bus line 12a into smaller areas, thereby allowing each portion of a line to be used in each direction. Show. As shown in FIG. 8b, several output buses 15a, 15b, 15c, and 15d intersect input bus 12a at junction locations 31, 32, 33, and. Each of these junction locations may use the connection structure shown in FIG. 7 to provide a possible interconnection between the output bus line 15 and the input bus line 12. However, unlike the structure of FIG. 8a, a pair of controllable driver circuits are provided between each junction. For example, drivers 92 and 93 are provided between the joints 31 and 32. By programming one of the driver circuits on and the other off, signals can be propagated between nodes 31 and 32 in either direction. FIG. 8c provides one example. In FIG. 8c, assume that the signal on line 15a is transmitted on input bus 12a in both the left and right directions. To accomplish this, circuits 91 and 92 are programmed on and circuits 90 and 93 are programmed off. This allows the signal on line 15a to be supplied to nodes 35 and 32. By way of example, the circuit 88 is programmed off so that the same bidirectional capability can be provided on the output line as well as the input line. Driver circuits 94, 95, 96, and 97 are all programmed off, thereby isolating node 32 from node 34. Of course, nodes can also be isolated by programming off only pairs 94 and 95 or 96 and 97. Circuit 98 is programmed on and circuit 99 is programmed off to allow the signal on output bus 15d to be provided to the right on input line 12a. FIG. 9 is a schematic diagram of a preferred embodiment of a logic cell used in the system of the present invention. As described above in connection with FIG. 1, a logic cell performs a logical operation on an input signal from an input bus, and the resulting output signal is used by another cell or by another integrated device by an integrated circuit. Used to be placed on the output bus as supplied to the As shown in FIG. 9, in this preferred embodiment, the logic cell 20 has up to 18 input signals 100, 101,. . . , 117, and may provide three output signals 140, 141, and 142 in response. Exclusive OR gate 119, AND gates 120, 121, and 122, and OR gate 128 may perform combinational logic. D-type flip-flop 133 provides the ability to perform continuous logic on input signals or output signals from combinational logic, depending on the state of multiplexer 132. In FIG. 9, each input signal is supplied through a polarity control (PC) circuit formed using an exclusive OR gate, as shown at the bottom right of the figure. A rectangular symbol with "PC" inside represents this polarity control connection and is used to simplify the drawing. The particular logic cell shown allows global or local clock selection, which allows the clock rate of the logic cell to be different from the clock rate of the entire integrated circuit. The programmable interconnect consumes no power in unused circuits and provides polarity control for all inputs. The particular logic cell shown implements a full adder with carry, a 2-bit comparator, or a four-input multiplexer, and is optimized to perform its function. Further, the logic can easily act as a single stage of a preloadable left and right shift register or as one stage of a 4-bit preloadable synchronous up / down counter. FIG. 10 is a detailed circuit diagram of a preferred embodiment of a logic block used in the programmable logic architecture of the present invention. The logic block generally corresponds to the preferred embodiment of the logic block 20 shown in block diagram form in FIG. Generally, the logic blocks, depending on the programming, are potentially coupled to receive up to 18 input signals at terminals along the left edge of the figure. In response, the logic block provides up to three output signals from terminals 143, 144, and 145 along the right edge of the figure. For purposes of illustration, the logic block may be considered to be divided into four sections as indicated by the dashed lines extending across FIG. The top two sections 146 and 147 provide a high level of functionality. This will be described later. Third section 148 provides multiplexing functions, and lower section 149 provides arithmetic and comparison functions. The adder in the lower section may provide carry to the upper section or compare the three bits to make it possible to detect if they are all the same. In the upper section 146, logic gates 151, 152, 153, and 156 provide AND-OR logic for node A. Multiplexers 170, 171 and 172 allow feedback from some of the gates in section 147. This allows some of the input signal going to section 147 to also be supplied to section 146. Multiplexer 155 provides a feedback multiplexer and, in combination with gate 156, can provide a latch function. The feedback path from flip-flop 157 provides a load function for a counter or shifter. The flip-flop itself provides a path for controlling the flow of data from the logic block to an external circuit. This provides a shift if the flip-flop is configured as a D-type flip-flop. When configured as a T-type flip-flop, it provides counting capability. The second section 147 of the logic block duplicates the function of the upper section and is connected to the upper section by node C via multiplexer 158 and AND gate 159. By programmably combining the top two sections of the logic block, the entire logic block may provide a 2-bit counter. This counter can be chained with other counts provided by other logic blocks to form a long counter. The connection at node C allows the upper unit to shift data to the lower unit. A third section 148 of the logic block, consisting primarily of multiplexer 160, can be programmed to provide a straight multiplexing function to the input signal subset. In the lower section 149 of the logic block, gates 161, 162, 163, 164, 165, 166, and 167 provide a full adder with a carry bit at node G. The sum appears at node H. Gates 161 and 162 allow for multiplexing, and gates 163, 168 and 167 allow for a 3-bit quantity comparison. Throughout FIG. 10, the small rectangle symbol labeled PC provides polarity control to the signal using the gate structure shown in the inset of FIG. Also, as shown, each multiplexer in the logic block is connected to be controlled by one or two control bits. These can be either logical 1 or logical 0, whereby one or two bit control signals are provided to the multiplexer, one of two input lines to the multiplexer, or one of four input lines. One choice becomes possible. The selected line is coupled to the output terminal of the multiplexer. With the logic block shown in FIG. 10, a logic function set can be configured relatively easily. Unlike the methods performed by other programmable logic device architectures, this architecture is optimized to provide a variety of functions, rather than providing overall full flexibility and functionality. By providing a relatively large logic block, fewer connections are required and overall operating speed is increased. In other architectures, many small logic blocks are deployed, which requires more interconnect between the blocks and lowers overall system speed. FIG. 11 is a block diagram illustrating a small portion of the overall programmable logic device chip shown in block form in FIG. Along the left edge of FIG. 11, a series of lines called "vertical channels" are shown. These lines are the input routing channels or buses 12 shown in the previous figures. Multiplexers 200 and 201 are coupled to the input bus and include circuitry that allows connection from routing channel 12 to the input of the logic block, as well as circuitry used to generate the input polarity control function described above. The logic blocks are shown to the right of multiplexers 200 and 201. The next three parts of the schematic, consisting of AND gates 202, 203 and 204, OR gate 205, and multiplexer 206, represent the AND-OR-multiplexer chain shown at the top of FIG. 10, which is a logic block diagram. Flip-flop 207 represents the flip-flops and circuits required to generate an output to drive one line on bus 15. The next four blocks 208, 209, 210, and 211 in the figure are one-way repeaters. Although only four are shown in the figure, it is clear that any desired number of repeaters can be used. These repeaters are repeaters that can be used to create gates 53, 62, 65, 67, 70, 71, 80, 82, 83, 84, or the like. By way of example, resistors 212 and 213 are shown coupled to repeaters 208 and 209, representing loads that these repeaters may drive in other circuit configurations. The resistors themselves are not manufactured on chip. Repeaters 210 and 211 drive the feedback path back to vertical channel 12. Thus, they represent supplying an output signal to the input bus, as shown by node 82 in FIG. Having described the preferred embodiment of the programmable logic of the system of the present invention, it will be understood that various modifications of the specific details and structure described above may be embodied. The scope of the invention is, therefore, indicated by the appended claims.

Claims (1)

[Claims]   1. A routing structure for a programmable logic circuit, comprising: The logic circuit includes a logic cell where a logic function is performed,   An input line set for supplying signals processed by the logic cells; A set of input lines, each input line extending substantially in a first direction;   An output line set for receiving signals processed by the logic cells, Each output line extends in a substantially second direction that is not parallel to the first direction, whereby An output line set, wherein the input line and the output line intersect at a junction area; Prepared,   Each of the junction regions includes a plurality of controllable driver circuits, the driver Each of the circuits includes a selected line of the output line set and the input line. Connected to the selected line of the Signal on the desired line of the input line set. Becomes possible,   Each of the controllable driver circuits includes at least the controllable driver. An active state in which a circuit replicates the supplied signal and the controllable driver The circuit can be placed in a passive state providing high impedance between input and output A routing structure comprising a buffer circuit.   2. Each output line of the output line set is controlled by a controllable driver circuit. , Which can be connected to a desired line of the input line set. A routing structure for the programmable logic circuit according to claim 1.   3. Coupling between the output line and the controllable driver circuit; Another controllable to amplify the signal of the input before feeding it to the controllable driver circuit 3. The programmable logic circuit according to claim 2, further comprising a simple driver circuit. Routing structure for   4. The controllable logic circuit of claim 1, wherein the controllable logic circuit is embodied on an integrated circuit. Routing structure for the on-board programmable logic circuit.   5. The input line set that supplies signals to the logic cells is 5. The method of claim 4, wherein the circuit extends in a meandering manner on a road and is located near the logic cell. A routing structure for the described programmable logic circuit.   6. The output line set for receiving a signal from the logic cell includes the output line set. The circuit extends in a meandering manner on an integrated circuit and is located near the logic cell. A routing structure for a programmable logic circuit according to claim 4.   7. Each of the buffer circuits responds to supplied control and input signals. In response, a programmable three-state circuit is provided for performing one of three operations. A routing structure for a programmable logic circuit according to claim 1.   8. The three operations provide a logical 1 and provide a logical zero And providing high impedance. Routing structure for programmable logic circuits.   9. Each has an input node and an output node, and is supplied to the input node. To supply an output signal obtained by performing a logic function to the output signal to the output node. Group of cells,   An input line set for supplying signals processed by the logic cell;   An output line set for receiving the signal processed by the logic cell;   A desired line among the input line and the output line is selected as the logic cell. A set of controllable driver circuits arranged to selectively interconnect with each other. ,   Each of the controllable driver circuits includes at least the controllable driver. An active state in which a circuit replicates the supplied signal and the controllable driver The circuit can be placed in a passive state providing high impedance between input and output Architecture for programmable logic circuits with variable buffer circuits Char.   10. Two conductors under program control in a programmable logic circuit A connection to connect, in three states: logical 1, logical zero, And a connection with the electronic circuit in one of a high impedance state.   11. Programmable control node for selecting said high impedance state 11. The programmable logic circuit according to claim 10, further comprising: Connection part to connect the conductors.   12. Input / output nodes in routing structures in programmable logic circuits An input / output circuit for connecting   At least one input / output pad;   An input line set for supplying signals to be processed by the logic cells;   An output line set for receiving signals processed by the logic cells;   A control located between the input / output pad and each line of the input line set A first set of possible driver circuits;   A control arranged between the input / output pad and each line of the output line set A second set of possible driver circuits;   An input / output circuit comprising:   13. Having logic cells that can be programmed to perform logic functions Having interconnect system for providing communication link between logic cells A method of increasing the operating speed of a ramable logic device, the passive switch Including using active controllable driver circuits in place of switch devices. How.