JP2000357757A - Semiconductor device and electronic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To select the most appropriate means of mounting electronic components for an electronic circuit device. SOLUTION: A semiconductor device 121 is provided with a package substrate 5, soldered to solder bumps 3 of a CSP-mounted semiconductor chip 4, and thereby integrated with the chip 4 is structured so that either a surface mounting means or a contact mounting means can be used selectively. The surface mounting means allows, for example, mounting of the semiconductor device 121 on a printed circuit board 12 of an electronic circuit device by means of solder bumps 9. By forming a recessed spherical contact 11 on the sidewall face of the package substrate 5 and installing a socket, for example, one having a train of contact pieces, suitable for the contact 11 on the circuit board 12, the contact mounting means can be also used selectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an electronic circuit device in which mounting means can be appropriately selected.

[0002]

2. Description of the Related Art Semiconductors, especially integrated circuits (abbreviated as LSI)
The progress of high integration is remarkable. At present, LSI has an integration degree of 256.
The trial production of M bits, 1 G bits, etc. has been completed, and further integration is being planned.

[0003] Such an improvement in the degree of integration requires 1L
The number of electronic circuits and circuit components per SI chip increases significantly. The number of terminals provided on a signal line provided in each of these electric circuits, a power supply line for supplying power to the circuit, a ground line for supplying a reference potential thereof, and the like also significantly increases.

In addition, the increase in the number of circuits means that the number of active elements constituting each circuit, such as transistors and diodes, and the number of passive elements such as resistors, capacitors, coils, etc., significantly increases within a certain area. Means. Checkpoints in key elements and circuits among these elements also increase.

[0005] Furthermore, the increase in the number of electronic circuits also increases the number of electrode pins in a limited semiconductor substrate area, and the pin interval is also reduced. The number of electrode pads has also increased significantly, and mounting accuracy is strictly required. In addition, the increase in the number of electrode pads for mounting also reduces the distance between the pads.

On the other hand, in such a highly integrated LSI chip, the mounting accuracy is limited by the manufacturing accuracy of the mainstream mounting technology so far.
CSP (CHIP SIZE PA) with solder balls
CKAGE) technology is expected to enter the practical period, and it is expected that mass production will start in 1999.

On the other hand, in the packaging method of the above-mentioned highly integrated LSI chip, in addition to the above-mentioned CSP as a semiconductor package for surface mounting, TSOP (THIN S
MALE OUT LINE PACKAGE) or TQ
FP (THIN QUADFLAT PACKAGE)
There was. These include a straight type and a gull wing type. Furthermore, there is SM (SMART MEDIA) as a semiconductor package for special use.

In the CSP, a rewiring layer is provided on one surface of a semiconductor chip, electrode pins are arranged on this layer, solder bumps are provided on the respective electrode pins, and the solder bumps are directly mounted on a printed circuit board. It has the feature that it can be mounted on a printed circuit board in the size of a semiconductor chip.

[0009] Further, the TSOP is such that a semiconductor chip is mounted on a lead frame or a film carrier tape, wired, housed in a flat package, and a number of leads are taken out from two opposing side walls of the flat package. .

The TQFP has a gull wing type in which a large number of leads are taken out from the four side walls of the flat package of the above TSOP, and each lead is bent at a middle portion at a right angle. Furthermore, SM is a typical example of a smart card, in which a semiconductor chip is bonded at a predetermined position on a contact terminal row to a device and a plastic substrate to which wiring is connected to the terminal row, and an electrode pad of this chip is attached. The column and wiring are wire-bonded and mounted on a package.

At the time of use, the device is inserted into the device from the outside of the device and is removably fitted and connected. The system is mounted with a dedicated connector (socket). Not the implementation used.

[0012]

However, these packages have the following problems. That is, C
SP mounting can be implemented in a chip size, so it can be compactly mounted and is ideal for high-density mounting.
The current flowing per unit time varies depending on the use of the SI circuit, and the thermal stress generated during operation depending on the type of the semiconductor chip concentrates on the solder bumps (balls), and cracks occur in the solder bumps, resulting in poor connection. There are cases. Further, in a personal computer or the like, various needs are required, for example, when there is a specification that a memory capacity is configured to be expandable by a user.

[0013] Furthermore, since a large number of solder balls are densely arranged on the bottom surface in the matrix direction on the manufacturing side, appropriate techniques for setting soldering conditions, repairability, inspectability, etc., and special equipment environment are required. There is a required problem. As the above soldering conditions, if the amount of solder in the soldering step is excessive, if the amount is too small, if the solder has no wettability, or if the package is misaligned, the results will be as follows.

As manufacturing conditions for avoiding this result, it is difficult to adjust the amount of solder, set the soldering temperature, and set other conditions such as the plating material for the soldering surface of the printed circuit board and the thickness of this plating.

Further, regarding the repairability of the above condition,
There are problems such as easiness of repair work and replacement work due to inspection failure when the SP package is mounted on a printed circuit board. Furthermore, there is a problem regarding the testability of the above conditions in terms of ease of testing such as connection confirmation and function confirmation of a soldered portion after mounting an LSI device packaged on a CSP package on a printed circuit board.

Further, in the CSP packaging, since the semiconductor chip is in an exposed state, there is a problem in a mechanism other than the LSI function, for example, external stress such as an impact may be concentrated on the solder bumps and broken.

Further, TSOP and the like have been the mainstream mounting method up to now, but when the semiconductor chip becomes highly integrated, the manufacturing limit is imposed in terms of the number of leads and the density, and furthermore, the package is not limited regardless of the size of the semiconductor chip. Since the size is the same and the leads protrude in two or four directions, the occupied area of the mounting substrate is large, the mounting density is poor, and the CSP mounting technology has reached the practical stage. .

Furthermore, since the SM mounting is for a special purpose, it is difficult to make a comparison, but since the terminal shape is flat, the fitting accuracy with the socket terminal is poor, and the contact area must be increased. There are issues that need to be addressed.

The present invention has been made in view of the above points, and has as its object to provide a semiconductor device which can be selected from two or more kinds of mounting means. That is, the mounting means can be selected according to the use, the use state, the use environment, and the like. An object is to enable a means for mounting an electronic component optimal for an electronic circuit device to be selected.

[0020]

According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor chip and terminals such as a signal line power line and a ground line of the semiconductor chip in predetermined positions. It is characterized by comprising an array of terminal rows and a plurality of types of mounting means provided in the terminal row.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; and a terminal row in which respective terminals such as a signal line power supply line and a ground line of the semiconductor chip are arranged at predetermined positions. And a surface mounting and contact mounting mechanism provided in the terminal row.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the contact mounting is a connector.

According to a fourth aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein the surface mounting is solder mounting.

According to a fifth aspect of the present invention, in the semiconductor device according to the first or second aspect, the semiconductor chip is one of a CSP package, a TSOP package, a TQFP package, and a smart media. It is characterized by two mounting means.

According to a sixth aspect of the present invention, in the semiconductor device according to the first and second aspects, at least one type of mounting means can be selected and implemented.

According to a seventh aspect of the present invention, there is provided a semiconductor device comprising: an electronic component; electrode terminals provided on the electronic component; and a mounting mechanism provided to select at least one of these electrode terminals. And characterized in that:

According to the present invention, a semiconductor device and an electronic circuit device can be mounted by a mounting method suitable for equipment, use, manufacture, and the like.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described in detail with reference to FIGS. An embodiment will be described in which a semiconductor device, for example, a memory device for storing a system of a personal computer is extended to a memory device for selecting and using a contact mounting such as a socket or a surface mounting such as bonding by soldering or the like. The surface mounting referred to in this specification refers to semi-permanent mounting, and refers to functions such as adhesive mounting, soldering, crimping, thermocompression bonding, and fixing. further,
Contact mounting refers to detachable mounting. That is, mounting by electrical contact, mounting by fitting, mounting through a socket, mounting by pressing, press-fitting, pressing, and the like.

FIG. 1 shows a semiconductor device of the present invention having a 256M capacity.
FIG. 3 is a cross-sectional view when an LSI chip having a bit DRAM configuration is mounted by CSP. That is, a known LSI manufacturing process such as a film forming process, an etching process, an exposure process, and a diffusion process is performed on a semiconductor wafer such as an N-type silicon wafer 1 to form a 256 Mbit electronic circuit such as a memory DRA.
Form M. CSP mounting is performed in a subsequent step.

That is, a redistribution layer 31 is formed on a silicon wafer 1 on which an LSI is formed by a well-known process.
The arrangement of the electrode pads such as the signal lines, the power supply lines, and the ground lines in the RAM circuit is rearranged into the arrangement of the electrode pads 2 designed in advance from the utilization surface. On each of the electrode pads 2, a surface mount, for example, a solder bump 3 is formed. There are various methods for forming the bumps 3. For example, first, a solder material is selected. A solder material having an X-Y direction thermal expansion coefficient value closest to the thermal expansion coefficient value of the silicon substrate 1 is selected.

This effect is caused by the temperature rise due to the heat generated inside the LSI in a practical state or the X-ray of the silicon substrate 1 and the electrode pad 2 to be joined due to the temperature rise during operation inside the electronic equipment.
If there is a large difference between the -Y direction thermal expansion coefficient value and the XY direction thermal expansion coefficient value of the solder bump 3, the amount of expansion due to the temperature received based on this difference will be different. In order to clear the problem that cracks easily occur in 2, it is desirable to select materials having thermal expansion coefficients close to each other. In this embodiment, for example, Ag-containing In-Pb solder is used.

The outline of the method of forming the bumps 3 by the solder will be described with reference to FIG. First, a barrier metal layer 32, for example, Ti-P
One of d-Au, Ti-Cu, Ti-W-Au, etc. is formed as shown in FIG. A resist film 33 is formed on the barrier metal layer 32, and the resist film 33 is exposed and developed using the arrangement of the electrode pads 2 as a mask. A mask of the resist film 33 leaving only the film 33 can be formed.

Using the remaining resist film 33 as a mask, the exposed barrier metal layer 32 is removed as shown in FIG. A resist film 34 is formed again as shown in FIG. 7F, and the resist film is similarly exposed and developed with the electrode pad pattern, and only the barrier metal layer 32 is exposed as shown in FIG.
A solder layer 35 is formed on the surface including the exposed layer (H)
It is formed as shown in the figure.

Here, in order to make the steps from FIG. (G) to FIG. (K) easy to understand in the figure, the process is shown by a regular cross-sectional representation in which the etched portion is removed and the unevenness is removed. Further, a resist film 36 is formed on the solder layer 35 as shown in FIG. This resist film 36 is also exposed by the above-mentioned exposure process, that is, exposed using the arrangement pattern of the electrode pads 2 as a mask, and developed (J), and the resist film 36 is left only on the electrode pattern 2 as shown in FIG. Form.

Using the resist film 36 as a mask, the exposed solder layer 35 is removed, for example, by metal plasma etching, and the resist films 36, 34 on the surface are further removed, for example, by plasma etching, thereby forming the barrier metal 32 as shown in FIG. Bumps 3 composed of a solder layer 35
To form The height of the bump 3 is, for example, 15 to 3
0 μm. When the solder bumps 3 protrude outward,
If they do not like it, they may be constituted by electrodes in which a plating layer is formed on the electrode pads 2.

Thereafter, the semiconductor wafer can be separated into each semiconductor chip 4 by scribing along the scribe line. The semiconductor device 4 in this state
Is as shown in FIG. That is, a semiconductor (LSI) chip 4 mounted with CSP can be obtained. FIG. 1 shows a state of the LSI chip 4 on which the CSP is mounted. The numbering of the chips 4 is given in the above-described manufacturing process for easy understanding.

In this embodiment, the following packages are further provided. That is, a surface mounting which is semi-permanent mounting, for example, solder mounting means, and a detachable contact mounting, for example, mounting means for fitting to a socket are provided. That is, a package substrate 5 having both functions is used.

That is, the insulator substrate is the silicon substrate 1,
A package board 5 made of a material, such as a ceramic, having an approximate thermal expansion coefficient in the XY direction, such as the electrode pads 2 and the solder bumps 3, is provided with a land-through 6 pattern formed by the pattern of the solder bumps 3. .
A conductor layer, for example, a copper film is formed on the inner wall surface of the land through 6 by, for example, electrolytic plating. The material of the package substrate 5 is preferably a glass epoxy resin substrate.

Lands 7 and 8 made of a conductor, for example, copper are provided on the front and back surfaces of the substrate 5 of each land through 6 thus formed while maintaining an electrical contact state with each land through 6. ing. The solder bumps 3 of the semiconductor chip 4 are soldered to one surface of the package substrate 5 to be integrated with the semiconductor chip 4. On each of the lands 8 on the other surface of the package substrate 5, a solder bump 9 is provided.

Further, the package including the space between the package substrate 5 and the semiconductor chip 4 is sealed with an epoxy resin 10, for example. The solder bump 9 is used for the semiconductor device 121.
If the protrusion is not appropriate, the protrusion of the solder bump 9 can be improved by employing a plated electrode.

Further, the package substrate 5 is also provided with a mounting mechanism using contacts. That is, a contact mechanism with a socket is provided on the side wall surface of the substrate 5 as a contact mechanism. In this embodiment, a concave spherical contactor 11 is provided on the side wall surface of the package substrate 5 with an uneven coupling contact and electrically connected to at least one of the lands 7 and 8.

That is, only the concave contactor portion is made of a conductor, for example, copper. This row of contactors is provided. Various modifications of the structure of the contactor 11 are possible. Thus, the semiconductor device 1
21 are constituted. Although the embodiment in which the contactor 11 is formed in a concave spherical shape has been described, conversely,
A projecting spherical surface may be formed on the package substrate 5. Of course, in this case, it goes without saying that the contact piece on the other side has a concave spherical shape.

Next, the counterpart mounting means of the semiconductor device 121 will be described. First, an embodiment of the socket 19 corresponding to the contact mechanism will be described. That is, if the package substrate 5 is rectangular, it is desirable that the insulator substrate, for example, the ceramic wiring substrate 12 be rectangular and have substantially the same size. At the peripheral edge of the square ceramic wiring circuit board 12, a row of terminals, for example, land throughs 13 is provided corresponding to the pattern of the row of contactors 11 formed on the side wall surface of the package board 5.

In this embodiment, it is located slightly outside the contactor position. The above ceramic wiring circuit board 12
May be either a single layer or a multilayer wiring board. In the case where a multilayer wiring board is employed, the contactor 11 is preferably formed on the side wall surface of the ceramic wiring circuit board 5 by, for example, performing interlayer connection using a via as a contact mounting means, and leading out through an inner layer wiring. Of course, the surface-mounted solder bumps 9 need to be formed via the land-throughs 6.

A conductor such as a copper film 14 is provided on the inner wall surface of such a land through 13 by, for example, an electrolytic plating method. Lands 1 are provided at both ends of the copper film 14.
5 and 16 are provided. On each land 15 on one surface of the substrate 12, a contact piece 17 fitted to each contactor 11 is fixedly provided. This contact piece 17
Is preferably a metal made of a conductor and having a spring property.

That is, it is desirable that the elastic mechanism behave in a direction in which the contact becomes stronger when it comes into contact with the contactor 11. On the free end side of the contact piece 17, the convex spherical contact portion 18 is provided to form a socket 19.

A side view of the concave spherical contactor 11 is as shown in FIG. FIG. 2 is a perspective view for explaining a state in which a conductor, for example, copper, of the concave spherical contactor 11 is formed on a side wall surface, for example, four wall surfaces of the rectangular package substrate 5. Of course, the two opposing terminals depend on the total number of terminals.
You may arrange on a wall surface. The illustration of the land through 6 and the land 7 is omitted.

The rows of the contactors 11 are arranged in a state designed in advance from the viewpoint of utilization. Although the embodiment in the contact mounting state has been described with reference to FIG. 1, when the embodiment of the surface mounting of the semiconductor device 121 shown in FIG. 1 is selected, for example, as shown in FIG.
Solder mounting. Can be replaced because it is soldered, but requires a specialized process of melting solder, does not require specialized knowledge, is practically different from contact mounting by insertion and removal operation, soldering mounting is relatively semi-permanent Belongs to the implementation. That is, the semiconductor device 121
The mounting by the solder bumps 9 formed on the surface of the package substrate 5 may be selected.

The semiconductor device 121 can be mounted on the land pattern 42 for mounting the semiconductor device 121 on the wiring formed on the printed circuit board 41 at the mounting position of the semiconductor device 121 by soldering. The land pattern 42 is provided in the pattern of the solder bump 9.

Each land pattern 42 has a circuit connected to a surface wiring, an interlayer wiring connected via vias, an inner layer wiring, a circuit guided to the back surface via the land through 43 and connected to the wiring on the back surface, and the like. It consists of. A conductor, for example, a copper film 44 is formed on the inner wall surface of the land through 43 by, for example, an electrolytic plating method, and conducts between the front and back surfaces of the substrate 41.

Lands 44 are provided on the free ends of the copper films 44, respectively. When the circuit board 41 is a multilayer wiring board, a connection to an internal wiring is further formed through an interlayer connection using a via.

In order to allow the user to add a memory in order to extend the system and functions of the personal computer, the socket 19 must be mounted on the printed circuit board of the personal computer.
Is provided and wired, so that it can be realized by the user mounting the semiconductor device 121 in contact as needed during use. When the manufacturer also selects the contact mounting, there is an effect that the user can easily replace the contact mounting and improve the function and the system.

That is, the surface mounting means and the contact mounting means can be selectively used for the semiconductor device 121 having the integrated package substrate 5 which is soldered to the solder bumps 3 of the CSP-mounted semiconductor chip 4. The semiconductor device 121 is configured as follows. This semiconductor device 1
The surface mounting means 21 can be mounted on the printed circuit board 12 of the electronic circuit device by, for example, the solder bumps 9.

In this embodiment, the surface mounting means is provided on the back surface side of the semiconductor chip 4, but the surface mounting means, for example, an electrode pad array may be provided on the opposite side of the semiconductor chip 4, that is, on the front side. good. Of course, surface mounting means may be provided on both the front and back surfaces of the semiconductor chip 4.

Further, the contact mounting is performed, for example, by providing a concave spherical contactor 11 on the side wall surface of the package substrate 5 and attaching a socket, for example, a socket having a row of contact pieces, to the circuit board 12 so as to fit the contactor 11. , And the contact mounting can be selectively used.

The phrase “selectively available” means that a plurality of mounting means may be selectively adopted. The advantage of this is that when thermal or physical stress is applied, as in CSP mounting, the current problem is that the solder concentrates on the soldered part and the solder is peeled off. By adopting the method together with the mounting, it is possible to avoid or largely improve the peeling of the solder when the stress distortion occurs.

In the above-described embodiment, an example has been described in which one type is provided for each of the surface mounting means and the socket mounting for the contact mounting, but a plurality of mounting means may be provided for each type. For example, if you select a contact implementation, you can use it to exchange and backup data and information between systems.

Next, another embodiment of the convex spherical contactor 18 that is compatible with the concave spherical contactor 11 shown in FIG. 2 will be described with reference to FIG. That is, the spherical surface of the convex spherical contactor 51 is configured to have a larger contact area with the inner wall surface of the concave spherical contactor 11 when making contact. In this convex spherical contactor 51, the pitch of each concave spherical contactor 11 is provided at the same pitch.

The connector 52 having such a convex spherical contactor 51 has a ring shape, for example, a square ring shape similar to the outer shape of the package substrate 5. This connector 52
Is attached to a printed circuit board on which a semiconductor device is mounted, for example. Therefore, the package board 5 having the LSI chip 4 is fitted and mounted on the connector 52 attached to the printed board. FIG. 5 is a plan view of this mounted state.

Next, an embodiment of lead connection of the package substrate 5 accommodating the semiconductor chip 4 to the contactor 11 will be described with reference to FIG. (A) In the figure, one LSI
FIG. 3 is a cross-sectional view showing an electrical connection state by a lead 61 between a row of electrode pads of a chip 4 and a row of concave spherical contactors 11 shown in FIG. 2 provided on a side wall surface of a package 53. FIG. 6B shows an embodiment in which rows of concave spherical contactors 11 provided on the side wall surface of the package substrate 53 are formed in two stages, and leads 61 are wired in the two rows of contactors 11.

FIG. 7C shows an embodiment in which when two LSI chips 4 are provided in one package substrate 53, two rows of contactors 11 are provided and wiring is performed by leads 61 respectively. . (D) Figure shows one package 5
3 shows an embodiment in which two LSI chips 4 are provided inside and a lead 61 is wired in a row of contactors 11 in one stage. That is, the lead 61 between the two LSI chips 4
Is wired to the contactor 11. The assembly structure of the semiconductor device 121 thus configured according to the embodiment will be described with reference to FIG.

That is, an upper lid 71 and a lower lid 72 made of glass epoxy resin made of an insulating material, for example, a material of a container constituting the package substrate 53 are provided. Package substrate 5
The concave spherical contactor 11 provided on the side wall surface of the third substrate 3 is made of a conductor, such as copper, and rows of the contactors 11 are arranged on the side wall surface of the package substrate 53 at a predetermined pitch.

Two LSI chips 4 are arranged in a container having such a configuration. These parts are integrated by bonding. An embodiment of an electrical connection method using the leads 61 between the LSI chip 4 having such a structure and the contactor 11 will be described with reference to FIG.

(A) shows a case where the contactor 11 is formed of a metal cup, and (B) and (C) show cases where the contactor 11 is formed by plating. (A) In the embodiment shown in FIG.
A projection 82 is provided on the top of the concave spherical metal cup 81, and the lead 61 is connected to the projection 82, for example, by soldering.

FIGS. 8B and 8C show the case where the concave spherical metal cup 83 is formed by plating. That is, in the case of FIG. 6B, a through hole 84 is provided at the top of the plated metal cup 83, conduction is provided by the plating layer 85 on the inner wall surface of the through hole 84, and connection with the lead 61 is made at the top. You may take it. (B) illustrates an example in which the connection with the lead 61 is made at the top via the through hole 84, but an electrical connection may be made at the end as shown in (C).

That is, in this example, the through hole 84 is provided in the peripheral portion 86 of the cup 83, and the peripheral portion 86 is electrically connected to the lead 61. In this case, (B)
There is an effect that processing is easier as compared with the method of taking at the top of the figure.

Next, another embodiment of the relationship between surface mounting and contact mounting will be described with reference to FIG. This mounting means can also be applied to the embodiments of FIGS. FIG. 9 (A)
Is an embodiment in which both surface mounting and contact mounting are provided. That is, the electrode pad structure provided on the package substrate 5 side and the contactor structure provided on the connector side are, of course, structures having the same potential coupling relationship with each other.

On one side, for example, electrode pads provided on the package substrate 5, for example, rows of concave spherical metal cups 91 having a relatively large radius are arranged at a predetermined pitch.
In each of the metal cups 91, a row of concave spherical metal cups 92 having a small radius are provided coaxially and spaced apart.

In this embodiment, the metal cup 9 having a small radius is used.
Reference numeral 2 denotes a cup for surface mounting, for example, used for solder mounting. At this time, the contactor 93 of the fitted connector 52 is, for example, a convex spherical solder bump. That is, after the fitting, the solder is heated to a solder melting temperature and soldered through a temperature lowering process. On the other hand, at the time of contact mounting, an electrical contact is obtained by sliding and fitting a convex spherical contactor fitted to the cup 91 having a large radius by the insertion operation of the semiconductor device 121.

(B) In the embodiment shown in FIG. (A), in the process described in the soldering mounting in FIG. (A), a metal guide also having a function of aligning and contacting the contactor 93 of the package substrate 52 with the cup 92 is used. Columnar electrode piece 9
4 is an embodiment provided. That is, this embodiment is configured such that each cup 92 of the package substrate 5 is aligned with the respective electrode pieces 94 of the connector 52, slid, stopped at a desired soldering position, and can be soldered. .

FIG. 9C is a plan view for explaining another embodiment of the arrangement pattern of the contactors 93 arranged on the connector 52 of FIG. That is, this is an embodiment in which the contactors 93 are arranged in two stages.

(D) is a cross-sectional view showing another embodiment in which the contactors 93 of (C) are arranged in a staggered manner.
(E) is a diagram showing another embodiment of (D).
That is, a combination of the configurations shown in FIGS. (B) and (D) also serves as an insertion guide for fitting to each contactor 93, and the columnar electrode pieces 94 are arranged in a staggered manner. Each contactor 93 is provided.

In the above embodiment, the mounting of the semiconductor device has been described. However, the present invention is not limited to the semiconductor device, and may be any type of mounting electronic components, such as a capacitor. The mounting of the capacitor will be described with reference to FIG. In this embodiment, a case where a pass capacitor connected for noise suppression is mounted will be described. Noise may be generated by the operation of the semiconductor device.

In order to suppress this noise, it is necessary to connect a pass capacitor 100, for example. By embodying the present invention, this capacitor can be built in or attached. That is, FIG. 7A shows an embodiment in which the capacitor 100 is housed in the package substrate 53. In this embodiment, the contactor 11 provided with the capacitor 100 on the side wall surface of the package substrate 53 includes:
This shows a state where the components are mounted by soldering.

FIG. 8B is a view for explaining an embodiment in which the capacitor 100 is connected to the outside of the package 58. The capacitor 100 has electrodes 101 connected to both ends. A configuration may be adopted in which the two-sided electrodes 101 and 102 are directly mounted on the circuit board 103 by soldering, and a connector is provided on the circuit board 103 and a contact is made by slidingly fitting the connector.

[0076]

As explained above, according to the present invention,
A desired mounting means can be selected by appropriately selecting a use, a use environment, a use state, and the like. Furthermore, since the maker side and the user side are configured so that the mounting means can be selected, there is the convenience that the usage range of the electronic device can be expanded as necessary. In particular, in a high-integration CSP-mounted LSI, it is preferable that a plurality of mounting means can be used at the same time in order to support a stress applied to a soldered portion.

[Brief description of the drawings]

FIG. 1 is a partially cutaway sectional view for describing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a perspective view for explaining an arrangement state of concave electrodes on a side wall surface of a package substrate of FIG. 1;

FIG. 3 is a partially cutaway sectional view for illustrating a manufacturing process of the semiconductor chip of FIG. 1;

FIG. 4 is a partially cutaway cross-sectional view showing a part of the embodiment for explaining another embodiment of FIG. 1 in an enlarged manner.

FIG. 5 is a plan view for explaining another embodiment of FIG. 1;

FIG. 6 is a plan view for explaining another embodiment of FIG. 5;

FIG. 7 is a cross-sectional view for explaining a package substrate assembling step of FIG. 6;

FIG. 8 is a cross-sectional view for explaining an embodiment of connection between the cup and the LSI chip in FIG. 6;

FIG. 9 is a view for explaining another embodiment of the surface mounting and the contact mounting of FIG. 1;

FIG. 10 is a diagram for explaining another embodiment of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon wafer 2 ... Electrode pad 3, 9 ... Bump 4 ... Semiconductor chip 5, 53 ... Package substrate 6, 13, 42 ... Land through 7, 8, 15, 16, 44 ... Land 10 , 12, 41, 103 ... circuit board 11 ... concave spherical contactor 14 ... copper film 17 ... contact piece 18, 51, 93 ... convex spherical contactor 19 ... socket 31 ... rewiring layer 32 ... ... Barrier metal layers 33, 34, 36 ... Resist layer 35 ... Solder layer 42 ... Land pattern 52 ... Connector 61 ... Leads 81, 83, 91, 92 ... Recessed spherical metal cup 82 ... Projection 84 ... Through hole 85... Plating layer 86... Peripheral part 94... Electrode piece 100.

Claims (7)

[Claims] 1. A semiconductor chip, a terminal row in which respective terminals such as a signal line power line and a ground line of the semiconductor chip are arranged at predetermined positions, and a plurality of types of mounting means provided in the terminal row. A semiconductor device comprising: 2. A semiconductor chip, a terminal row in which respective terminals such as a signal line power line and a ground line of the semiconductor chip are arranged in predetermined positions, and a surface mounting and contact mounting mechanism provided in the terminal row. And a semiconductor device comprising: 3. The semiconductor device according to claim 2, wherein the contact mounting is a connector. 4. The semiconductor device according to claim 2, wherein the surface mounting is solder mounting. 5. The semiconductor device according to claim 1, wherein the semiconductor chip is one of CSP mounting, TSOP mounting, TQFP mounting, and smart media mounting means. 6. The semiconductor device according to claim 1, wherein at least one type of mounting means can be selected and implemented. 7. An electronic circuit device comprising: an electronic component; electrode terminals provided on the electronic component; and a mounting mechanism provided to select at least one of the electrode terminals. .