JP2000357754A - Method for saliciding source line in flash memory having sti - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a salicide source line in a flash memory having a shallow trench isolation(STI) structure by forming a side wall of an insulator on a side surface where the source is exposed and forming a silicide layer in a region positioned lower than the insulated structure on a semiconductor substrate. SOLUTION: A nitride thin film 110 of 50-600 Å thick is formed on a structure. Then, the nitride oxide thin film 110 is etched to expose a region for an oxide trench 160. Next, a structure 70 for shallow trench isolation is formed by etching. Following the formation of an oxide side wall 130 and an oxide trench 160, blanket implantation of dopant species is performed to form a source line structure 24, and a patterned resist layer 120 is removed. Subsequently, any of metals reacts with a silicon region thereunder to form a silicide region. Any part of the metal that has not reacted is etched off to form a source-line silicided region 140.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to the field of electronic devices and, more particularly, to a method for manufacturing salicide source lines in a flash memory having a shallow trench isolation (STI) structure.

[0002]

2. Description of the Related Art Electronic devices such as televisions, telephones, radios, and computers are often manufactured using semiconductor components such as integrated circuits, memory chips, and the like. These semiconductor elements are typically made from various microelectronic devices formed on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a conductor, semiconductor, and insulator pattern formed on a semiconductor substrate.

[0003] The density of microelectronic devices on a semiconductor substrate can be increased by reducing the spacing between these semiconductor devices. By reducing the spacing, more microelectronic devices can be formed on the semiconductor substrate.
As a result, the computing power and speed of the semiconductor element can be greatly improved.

[0004] Flash memories, also known as flash EPROMs or flash EEPROMs, are formed of an array of memory cells, each cell having a floating gate transistor. Data can be written to each cell in the array, but erasure is done in blocks of cells. Each cell is a floating gate transistor having a source, a drain, a floating gate, and a control gate. The floating gate uses channel hot electrons for writing from the drain and Fowler-Nordheim tunneling for reading from the source. The source of each floating gate of each cell in a row of the array is connected to form a source line.

[0005] The floating gate transistors are electrically insulated from each other by an insulating structure. One type of insulation structure used is local oxidation of silicon (LOCO).
S) Structure. LOCOS structures are typically formed by thermally growing an oxide layer localized between cells, electrically insulating the cells. One problem with the LOCOS structure is that it contains areas where the structure does not work and wastes valuable space on the semiconductor substrate.

Another type of insulation structure used is shallow trench isolation (STI). STI structures are generally formed by etching trenches between cells, which are filled with a suitable dielectric material. The STI structure is smaller than the LOCOS structure, allowing the cells to be closer together and spaced apart, and increasing the density of cells in the array. However, the STI structure is often not used in the flash memory because it is difficult to form a source line connecting the cells in each row. The source line of a flash memory using the STI structure often has a higher resistance than the corresponding flash memory using the LOCOS structure. When the electric resistance increases, the operation performance of the memory decreases.

This application incorporates by reference the following patents / patent applications.

[0008]

Accordingly, there is a need for a low resistance source line for a flash memory using an STI structure, and a method of manufacturing the same. The present invention provides a salicide source line for a flash memory using an STI structure and a method of manufacturing the same. Salicide source lines form a low resistance path that substantially eliminates or reduces problems associated with conventional methods and systems.

The present invention and its advantages will be more fully understood from the following description based on the accompanying drawings. Note that the same parts are denoted by the same reference numerals throughout the drawings.

FIGS. 1-5 illustrate various aspects of manufacturing an electronic device and the source lines used in the electronic device. As described in detail below, the method of the present invention can be used to form a source line with low electrical resistance. The stepped sidewalls increase the dopant incorporated into the sidewalls during ion implantation, thereby lowering the resistance of lines incorporating stepped sidewall trenches.

FIG. 1 is a circuit diagram of an electronic device 8 that can incorporate the present invention, and is partially shown in block form. The electronic device 8 includes a word line decoder 22, a column decoder 28, a read / write / erase control circuit 32 for controlling the decoders 22 and 28, and a memory cell array 9. Memory cell array 9
Consists of a plurality of memory cells 10 arranged in rows and columns. Each memory cell array 9 includes a floating gate transistor 11, and each floating gate transistor 11 has a source 12, a drain 14, a floating gate 16, and a control gate 18.

Each control gate 18 of a cell 10 in a row
Are coupled to word lines 20 and each word line 20
Are coupled to a word line decoder 22. Each source 12 of cells 10 in a row is coupled to a source line 24. Each drain 14 of a cell 10 in a column
Are coupled to the drain / column line 26. Each source line 24 is coupled to a column decoder 28 by a column line 27, and each drain / column line 26 is connected to a column decoder 28.
Is joined to.

In a write or program mode, word line decoder 22 responds to a word line address signal on line 30 and a signal from read / write / erase control circuit 32 to control the gate of selected cell 10. A predetermined first programming voltage V _RW (approximately +12) on selected word line 20 coupled to
V). The column decoder 28 also provides a second signal on the selected drain / column line 26, and thus on the drain 14 of the selected cell 10.
To apply the programming voltage V _PP (about +5 to +10 V). Source line 24 is line 27
It is coupled to reference potential V _SS through. All unselected drain / column lines 26 are coupled to reference potential V _SS . These programming voltages cause high current conditions in the channel (from drain 14 to source 12) of the selected memory cell 10, creating channel hot electrons near the drain-channel junction and avalanche breakdown electrons. . These electrons are in the selected cell 1
0 is injected into the floating gate 16 across the gate oxide. The programming time is selected to be long enough to program the floating gate 16 with a negative program charge of about -2V to -6V with respect to the gate. In the case of the memory cell 10 manufactured according to one embodiment of the present invention,
Control gate 18, word line 20, and floating gate 1
The coupling coefficient between 6 is about 0.5. Thus, the programming voltage V _RW (eg, 12V) on the selected word line 20 including the selected control gate 18 will cause a voltage on the selected floating gate 16 of about +5 to + 6V.

During programming, the selected cell 10
Floating gates 16 are charged with channel hot electrons, which cause the source / drain paths under the floating gates 16 of the selected cell 10 to be non-conductive (read as "0" bits). The source-drain paths under the floating gates 16 of the unselected cells 10 remain conductive, and these cells 10 are read as "1" bits.

In the flash erase mode, column decoder 28 operates to leave all drain / column lines 26 floating. The word line decoder 22
It operates to connect all word lines 20 to the reference potential V _SS . The column decoder 28 is operable to apply a high positive voltage V _EE of + 15V to about + 10V to all the source lines 24. These erase voltages generate a Fowler-Nordheim tunneling current that transfers charge from the floating gate 16 and provides sufficient field strength to erase the memory cell 10 through the tunneling region between the floating gate 16 and the semiconductor body. Generated across.

In the read mode, word line decoder 22 responds to a word line address signal on line 30 and a signal from read / write / erase control circuit 32 to apply a predetermined signal to selected word line 20. applying a positive voltage V _CC (approximately + 5V), also operates to apply a low voltage (ground or V _SS) to the word line 20 which is not selected. The column decoder 28 operates to apply a predetermined positive voltage V _SEN to at least the selected drain / column line 26 and to apply a low voltage to the source line 24. Column decoder 28 also operates in response to the signal on address line 34 to connect the selected drain / column line 26 of the selected cell 10 to the data output terminal. The conduction or non-conduction state of the cell 10 coupled to the selected drain / column line 26 and the selected word line 20 is detected by a sense amplifier (not shown) coupled to the data output terminal. .
The read voltage applied to the memory array 9 is sufficient to determine the channel impedance for the selected cell 10, but hot carrier injection or Fowler-Nordheim tunneling, which disrupts the state of charge of the floating gate 16. Is not enough to cause

For convenience, the read, write, and erase voltages are shown in the following table. Table 1

FIGS. 2 and 3 show the structure of a part of the memory array 9 of FIG. That is, FIG. 2 is an enlarged plan view of a part of the memory array 9, and FIG. 3 is a perspective view of a part of the memory array 9 shown in FIG. As described above, the memory array 9 includes a plurality of memory cells 10 arranged in rows and columns.

As best shown in FIG. 3, each row of memory cells 10 is formed in a continuous stacked structure 50 including a plurality of memory cells 10. The floating gate transistor 11 in each memory cell 10 is formed on a semiconductor substrate 52 and is separated from each adjacent memory cell 10 in the continuous stack structure 50 by a shallow trench isolation structure 70. Semiconductor body 52 includes a source region 60 and a drain region 62 separated by a channel region 64. The floating gate transistor 11 is generally
A gate stack 54 is provided on the outer surface of a portion of the channel region 64.
And doping a portion of the source region 60 and a portion of the drain region 62 in contact with the gate stack 54 to form the source 12 and the drain 14, respectively.

The semiconductor substrate 52 can be comprised of a wafer formed from a single crystal silicon material. However, it will be appreciated that the semiconductor substrate 52 can be made of other suitable materials or layers without departing from the scope of the present invention. For example, semiconductor substrate 52 can include an epitaxial layer, a recrystallized semiconductor material, or any other semiconductor material.

The regions 60, 62, and 64 are substantially parallel and can extend the length of the memory array 9.
The channel 64 of the semiconductor substrate 52 is doped with an impurity to form a semiconductor region. The channel region 64 of the semiconductor body 52 can be doped with p-type or n-type impurities to change the operating characteristics of a microelectronic device (not shown) formed on the doped semiconductor body 52.

As best shown in FIG. 3, the floating gate transistor 11 in each continuous stack structure 50 in the memory array 9 has a shallow trench isolation (STI) structure 7.
0 electrically insulates each other. STI structure 70 is typically formed prior to forming gate stack 54 on semiconductor substrate 52. The STI structure 70 is
The trench 72 is formed in the semiconductor substrate 52 by etching. The trench 72 is generally
The depth is about 3 to 8.5 μm. The trench 72 is
Of the second side wall 76 and the second side wall 76. As will be described in greater detail below, sidewalls 74 and 76 can be made at an angle to vary the cross-sectional shape of trench 72.

The trench 72 is then filled with a trench dielectric material 78 to electrically insulate the active region of the semiconductor body 52 between the STI structures 70. Trench dielectric material 78
Can consist of silicon dioxide, silicon nitride, or a combination thereof. Trench dielectric material 78
Is typically etched back, followed by a deglazing process to clean the surface of the semiconductor body 52 before forming the gate stack 54. It will be appreciated that the trench dielectric material 78 can be comprised of any other suitable dielectric material without departing from the scope of the present invention.

Next, a continuous stack structure 50 is formed on the outer surfaces of the semiconductor substrate 52 and the filled trench 72. The continuous stack structure 50 includes a series of gate stacks 5 formed on the outer surface of the channel region 64 of the semiconductor substrate 52.
4 is formed. As best shown in FIG. 3, gate stack 54 comprises gate insulator 56, floating gate 16, gap dielectric 58, and control gate 18. Gate insulator 56 is formed on the outer surface of semiconductor body 52, and floating gate 16 is formed on the outer surface of gate insulator 56. Gap dielectric 58 is formed between floating gate 16 and control gate 18 and operates to electrically isolate floating gate 16 from control gate 18.

Gate insulator 56 is typically grown on the surface of semiconductor substrate 52. The gate insulator 56
It can be made of an oxide or nitride having a thickness of about 100 to 500 mm. It will be appreciated that gate insulator 56 can be made of other materials suitable for insulating semiconductor devices.

The floating gate 16 and the control gate 18 are conductive regions. Gates 16 and 18 are typically comprised of a polycrystalline silicon material (polysilicon) and are doped with impurities at that location to make the polysilicon conductive. The thickness of the gates 16 and 18 is typically on the order of 100 nm and 300 nm, respectively. It will be appreciated that gates 16 and 18 can be made of any other suitable conductive material without departing from the scope of the present invention.

The interstitial dielectric 58 may comprise a heterostructure formed by oxides, nitrides, or alternating layers of oxides and nitrides. The thickness of the gap dielectric 58 is
It is of the order of 20 to 40 nm. It will be appreciated that the interstitial dielectric 58 can be comprised of other materials suitable for insulating semiconductor devices.

As best shown in FIG. 2, the control gate 18 of each floating gate transistor 11 is electrically coupled to the control gate 18 of an adjacent floating gate transistor 11 in an adjacent continuous stack structure 50 to provide a continuous conductive path. Has formed. With respect to the memory array 9 described with reference to FIG.
Operates as the word line 20 of the.

In contrast, the floating gate 16 of each floating gate transistor 11 is not electrically coupled to the floating gate 16 of any other floating gate transistor 11. That is, the floating gate 16 of each floating gate transistor 11 is electrically insulated from all other floating gates 16. In one embodiment, the floating gates 16 in adjacent memory cells 10 are isolated by gaps 80. Gap 80 is typically a layer of conductive material (not shown) used to form floating gate 16.
Etched in.

The source 12 of the floating gate transistor 11
The drain 14 and the drain 14 are formed in portions of the source region 60 and the drain region 62 of the semiconductor substrate 52, respectively. The source 12 and the drain 14 are made of a semiconductor substrate 5 into which impurities are introduced to form a conductive region.
It consists of two parts. The drains 14 of each floating gate transistor 11 in a column are electrically coupled to each other by a plurality of drain contacts 82 to form a drain / column line 26 (not shown). drain·
Column lines 26 are typically formed on the outer surface of word lines 20. As will be described in detail below, the source 12 of each floating gate transistor 11 forms part of the source line 24 and is formed during the formation of the source line 24.

As best shown in FIG. 3, a portion of source line 24 forms source 12 of floating gate transistor 11. The source lines 24 connect the sources 12 to each other by continuous conductive regions formed in the semiconductor body 52 adjacent to the source regions 60. As best shown in FIG. 3, the source line 24 crosses the STI structure 70 in the source region 60 of the semiconductor body 52 below the STI structure 70. On the other hand, the STI structure 70 has the channel region 6 of the semiconductor substrate.
4 electrically insulate adjacent floating gate transistors 11.

The source line 24, and correspondingly the source 12 of each floating gate transistor 11, is typically manufactured after at least a portion of the gate stack 54 has been manufactured. Gate stack 54 is pattern masked (not shown) using conventional photolithographic techniques, leaving semiconductor body 52 proximate source region 60 exposed. The exposed areas of the semiconductor body 52 are then etched, and the trench dielectric material 78 in the exposed areas is removed. Trench dielectric material 78
Can be an anisotropic etching process. Anisotropic etching is
Can perform carbon-fluorine such as CF ₄ or CHF ₃ using a reactive ion etch (RIE) process using a gas based.

Semiconductor substrate 52 adjacent to source region 60
The portion (including the portion of the semiconductor body 52 forming the trench 72) is doped with impurities to make the region conductive. Next, the conductive region is subjected to a heat treatment to diffuse impurities into source region 60 of semiconductor substrate 52. The diffused conductive region is connected to each floating gate transistor 11.
Of the source 12 and the source line 24 are formed. Source region 60 of semiconductor body 52 is typically doped by an implantation process in which dopant ions are bombarded into semiconductor body 52.

FIGS. 4A to 4E are cross-sectional views (along line 100-100 in FIG. 2) of the semiconductor substrate 52 according to the present invention. These figures show the formation of a source line that is silicided to reduce the resistance. For the sake of clarity, the integrated circuit present on the substrate (as described above)
Other features are omitted. FIG. 4A shows a semiconductor substrate 5.
2 is a cross-sectional view (along line 100-100 of FIG. 2) showing a shallow trench isolation structure 70, a substrate 52, a polysilicon word line 20, and a gap dielectric 58. This structure is formed after etching and dopant doping and annealing of the stack to form the source and drain regions 60 and 62 of the cell.

As shown in FIG. 4B, in one embodiment of the present invention, a nitride thin film 110 having a thickness of about 50 to 600 ° is formed on the structure of FIG. 4A. In one embodiment of the present invention, the nitride thin film deposition process can be performed on standard semiconductor processing deposition equipment using the following range of processing conditions. Dichlorosilane _{60 - 100 sccm NH 3 700 -} 900 sccm Pressure 150 - 300 Torr Temperature 700 - 850 ° C deposition time 10 - 20 minutes a layer 120 of photoresist Following deposition of the nitride film 110 is formed, the standard photolithographic Patterned using graphic technology. This pattern is removed by the trench oxide 16 which is removed during the trench etching process.
The area within 0 is exposed.

FIG. 4C shows the state of FIG.
This is a structure formed following trench etching and source line implantation applied to the structure shown in FIG. The trench etching process is a two-step process in which the nitride thin film 110 is etched first, and then the shallow trench isolation structure 70 is etched. In one embodiment of the present invention, the two-step etching process comprises:
It can be performed on a standard semiconductor processing plasma etching facility using the following range of processing conditions. Step 1 (nitride etch) Argon _{150 - 180 sccm CHF 3 8 -} 15 sccm Pressure 18 - 30 millitorr frequency 500 watts cathode temperature 20 ° C etching time: 5 - 20 sec Step 2 (oxide etch) Argon 200 - 400 sccm CO _{150 - 300 sccm C 4 F 8} 5 - 15 sccm pressure 30 mTorr RF 1000 - 2000 watts cathode temperature 20 ° C etching time 20 - 80 seconds

The two-step etching described above can be performed in a standard plasma etching chamber. By this process, the nitride sidewall 130 and the oxide trench 160 shown in FIG. 4C are formed. Following formation of oxide trench 160, a blanket implant of a dopant species is performed to form source line structure 24. In one embodiment, the dopant species is arsenic, phosphorus, antimony alone, or a combination thereof. Following the blanket implant, the patterned resist layer 120 is removed using standard processing. In one embodiment of the present invention, a metal (preferably made of Ti, but may be made of tungsten, molybdenum, cobalt, nickel, platinum, or palladium) is formed on the structure. The silicide region is formed by performing a silicide formation step at a temperature of about 500 to 800 ° C. so that the metal reacts with any of the underlying silicon regions to form a silicide region. Any unreacted metal is then etched using a standard process. As a result of this process, a source line silicide region 140 shown in FIG. 4D is formed. This source line silicidation region 140 has a much lower resistance than the diffusion source line process.

FIG. 4D further illustrates the small silicide region 15 forming the word line 20.
0. These small areas are the result of photolithographic process tolerances and have no effect on device performance. In the case of an improved zero-tolerance photolithographic process, these silicide regions 150 in word line 20 would not be present.
Following the unreacted metal etching process, an optional second annealing step is performed at 600-1000 °
C can be performed. In another embodiment of the invention, the implant anneal step is performed after the photoresist removal step and before the silicide formation process. This injection anneal can be performed using a furnace process, a rapid thermal process, or a combination of both.
It can be performed at a temperature of about 500-1000 ° C.

Subsequent to silicide formation, a blanket etch of the nitride is performed to obtain the structure shown in FIG. This blanket etch results in additional nitride sidewalls 131 as shown. A necessary requirement for a blanket etch is a high nitride to silicide selectivity. In one embodiment of the present invention in which cobalt silicide is formed, blanket etching of the nitride can be performed on standard semiconductor processing plasma etching equipment using the following range of processing conditions. Argon 150-270 sccm CHF ₃ 15-50 sccm O ₂ 1-8 sccm High frequency 200-600 Watt Pressure 300-500 mTorr Gap 1.15 cm Etching time 10-60 seconds

FIG. 5 is a cross-sectional view (along line 101-101 of FIG. 2) of the substrate showing the silicide region 140 and source line 24 manufactured by the method of the present invention.

While the invention has been described with reference to certain embodiments, various changes and modifications will occur to those skilled in the art. The present invention is intended to cover these changes and modifications within the scope of the claims.

In connection with the above description, the following items are disclosed.

1. A method for forming an electronic device having conductive lines, comprising: a) providing a plurality of semiconductor devices each having a gate and a source; and a semiconductor substrate having at least one insulating structure; and b) on the semiconductor substrate. C) etching a portion of said insulator film and a portion of said insulating structure, thereby exposing a region of said semiconductor substrate under said insulating structure, said source comprising: Forming an insulator sidewall film on the exposed side surfaces of the semiconductor substrate; and d) forming a silicide on the region of the semiconductor substrate under the insulating structure. .

2. The insulating structure is shallow trench insulation or LOCOS.
The method described in.

3. The plurality of semiconductor devices are composed of flash memory cells. The method described in.

4. The insulator film is silicon nitride,
1. The film as described in 1. above, which is a film from the group consisting of silicon oxide, silicon oxynitride, and polymer. The method described in.

5. The insulator sidewall film is a film from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, and a polymer. The method described in.

6 The above-mentioned 1., wherein the silicide is formed of a metal from the group consisting of titanium, tungsten, molybdenum, cobalt, nickel, platinum, and palladium. The method described in.

7. A method of forming an integrated circuit memory, comprising: a) providing a semiconductor substrate having a plurality of flash memory cells, each of the flash memory cells having a top surface and a gate having a side surface adjacent to a source. Wherein the flash memory cell is in contact with a plurality of insulating structures, the method further comprises: b) forming an insulator film on the semiconductor substrate; c) a plurality of flash memory cells. Etching the insulator film forming an insulator sidewall film on the side surface contacting the upper source; and d) etching the insulating structure to form a semiconductor substrate under the insulating structure. Forming a source line by exposing regions; and e) implanting a dopant species into said source line. Method characterized by comprising the flop, the step of forming silicide on f) the source line, the.

8. 6. The insulating structure according to the above 7, wherein the insulating structure is formed using shallow trench insulation or LOCOS. The method described in.

9. The insulator film is silicon nitride,
6. The film according to the above 7, wherein the film is a film from the group consisting of silicon oxide, silicon oxynitride, and a polymer. The method described in.

10. The insulator sidewall film includes:
6. A film from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, and polymer. The method described in.

11. 6. The method according to the above 7, wherein the silicide is formed of a metal from the group consisting of titanium, tungsten, molybdenum, cobalt, nickel, platinum, and palladium. The method described in.

The conductive line (24) and the trench (7)
2) A method of forming a semiconductor element having a silicide region (140) traversing it. The method includes forming a nitride sidewall (130) to protect the stack during a silicidation process.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an electronic device including a memory cell array according to the present invention, a part of which is shown by blocks.

FIG. 2 is an enlarged plan view of a portion of the memory cells of the array of FIG. 1 according to the present invention.

FIG. 3 is a perspective view of a portion of the memory cell array of FIG. 2 according to the present invention.

4 (A) to 4 (E) are cross-sectional views of a semiconductor substrate showing formation of a silicidation source line along line 100-100 in FIG. 2, according to one embodiment of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor substrate showing a silicidation source line according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 8 electronic device 9 memory cell array 10 memory cell 11 floating gate transistor 12 source 14 drain 16 floating gate 18 control gate 20 word line 22 word line decoder 24 source line 26 drain / column line 27 column line 28 column decoder 30 word line address signal line 32 read / write / erase control circuit 34 address line 50 continuous stack structure 52 semiconductor substrate 54 gate stack 56 gate insulator 58 gap dielectric 60 source region 62 drain region 64 channel region 70 shallow trench insulation structure 72 trench 74 first side Wall 76 second sidewall 78 trench dielectric material 80 gap 82 drain contact 110 nitride thin film 120 photoresist layer 130; 31 nitride sidewall 140 source lines silicided region 150 smaller silicide regions 160 oxide trench

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Flydoon Merad, United States of America 75023 Plano Eagle Pass 5008 (72) Inventor Min Yang, United States of America 75082 Richardson Wendover Court 3309 (72) Inventor, Lancy Thun United States of America, Texas 75023 Plano Valleybrook Drive 5900

Claims (1)

[Claims] 1. A method of forming an electronic device having conductive lines, comprising: a) providing a plurality of semiconductor devices each having a gate and a source, and a semiconductor substrate having at least one insulating structure; b. C.) Forming an insulator film on the semiconductor substrate; and c) etching a portion of the insulator film and a portion of the insulating structure, thereby forming a region of the semiconductor substrate under the insulating structure. Exposing to form an insulator sidewall film on the exposed side surface of the source; and d) forming silicide on the region of the semiconductor substrate under the insulating structure. A method characterized by the following.