JP2000354205A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an output signal stable by adjusting a bias level with coupling of a reset pulse in an input signal from a charge transfer section to an optimum bias. SOLUTION: The solid-state image pickup device having a charge transfer section 1, an output section that is connected to the charge transfer section 1 and has a reset gate RG to which a reset pulse Pr is supplied, and an output amplifier that receives an input signal from this output section, is provided with a dummy signal processing section that generates a signal to adjust a bias component generated through coupling of the reset pulse Pr in the input signal supplied from this output section to the output amplifier, and adjusts this bias component to supply the signal generated by this dummy signal processing section to the output amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a so-called floating diffusion amplifier for converting a signal charge from a charge transfer section constituted by a CCD into an output voltage.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional CCD solid-state image pickup device, particularly an output circuit thereof, includes a floating diffusion FD, which is separated from an output gate OG, at a stage subsequent to a charge transfer section 21 composed of a CCD. and the discharging device 22 consisting of the reset gate RG and a drain region D, a source follower circuit 23 and an output element Q ₁ and the load resistance element Q ₂ downstream of the discharge device 22, based on the input of the sample-and-hold pulse Ps A sampling and holding (S / H) circuit 24 for extracting only the signal component Vs from the output signal Sia from the source follower circuit 23;
/ H circuit 24 amplifies the signal component Vs from the output signal S
It is configured to include an amplifier 25 that is taken out as a.
This source follower circuit 23 has its load resistance element Q ₂
Is applied with a fixed bias potential Vg to the input signal Si from the charge transfer unit 21 with a gain ≒ + 1 (+
Indicates non-inversion).

In the charge transfer section 21, signal charges transferred from below the transfer electrode TG in the last stage are temporarily stored in the floating diffusion FD, and a voltage change based on the stored charges, that is, an input signal Si is transferred to the subsequent stage. To the source follower circuit 23.

After the input signal Si is supplied to the source follower circuit 23, a reset pulse P is applied to the reset gate RG.
r, the floating diffusion FD is reset to the initial voltage Vdd, and the charge accumulated in the floating diffusion FD is drained to the drain region D.
Sweep out to the side.

Accordingly, the waveform of the input signal Si from the charge transfer section 21 input to the source follower circuit 23 is shown in FIG.
As shown in FIG. 3, the reset period tr, the field through period tf, and the signal period ts are divided into three periods. In the reset period tr, the initial voltage Vdd of the floating diffusion FD appears. Vs appears.

Then, in the S / H circuit 24 at the subsequent stage, only the signal component Vs in the output signal Sia from the source follower circuit 23 is sampled and supplied to the amplifier 25 at the next stage. In the amplifier 25, the S / H circuit 24
Is amplified and extracted as an output signal S.

[0007]

By the way, recently,
For the purpose of increasing the sensitivity, the output circuit itself is often given a gain, for example, by using an inverter gain amplifier as the amplifier 25.

The problem here is that the charge transfer unit 21
This is the coupling of the reset pulse Pr in the input signal Si from. The coupling amount V is a difference between the potential Vdd in the reset period tr and the bias potential Vb in the field through period tf in FIG.

That is, as shown in FIG. 7, as the gain of the output circuit increases, the slope of the input / output characteristic curve increases (see the broken line), so that the input range decreases.
With respect to the bias potential Vb during the field through period tf of the input signal Si, there is a problem that it is difficult to determine the optimum bias. Further, the bias potential Vb changes due to manufacturing variations and temperature characteristics.
The inconvenience that the sensitivity as a CCD solid-state imaging device changes greatly occurs.

Further, for example, when the capacity of the floating diffusion FD is reduced in order to increase the conversion efficiency (when the formation pattern of the floating diffusion FD is reduced), the coupling amount V increases, and the Since the ratio of the signal component Vs becomes very small, improvement in sensitivity cannot be expected.

The present invention has been made in view of such a problem, and an object of the present invention is to adjust a bias potential by coupling of a reset pulse to an optimum bias value in an input signal from a charge transfer unit. And to provide a solid-state imaging device capable of stabilizing an output signal.

[0012]

According to the present invention, there is provided a solid-state imaging device comprising: a charge transfer unit; an output unit connected to the charge transfer unit and having a reset gate supplied with a reset pulse;
A solid-state imaging device having an output amplifier to which an input signal from the output unit is supplied; and a signal for adjusting a bias component generated by coupling of the reset pulse among input signals supplied from the output unit to the output amplifier. And a bias signal is adjusted by supplying a signal generated by the dummy signal processing unit to the output amplifier.

According to the configuration of the present invention described above, the bias component generated by the coupling of the reset pulse of the input signal from the charge transfer unit is adjusted by the signal generated by the dummy signal processing unit. The bias component generated by the coupling of the reset pulse of the input signal Si can be held at the optimum bias potential. Even if the output circuit itself has a high gain and the input range is narrowed, the charge from the charge transfer unit is reduced. An optimum bias can be set for an input signal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram illustrating a main part of the solid-state imaging device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line AA and line BB in FIG.

In this solid-state imaging device, a floating diffusion FD and a reset gate RG are provided at the next stage of the charge transfer section 1 composed of a CCD via an output gate OG.
And a discharge element 2 including a drain region D, and the pattern output circuit 3 is connected to a stage subsequent to the discharge element 2.

The pattern output circuit 3 includes a source follower circuit 4 including an output element Q ₁ and a load resistance element Q _2, and an output signal Sia from the source follower circuit 4 based on an input of a sample and hold pulse Ps. Signal component V
A sampling and holding (S / H) circuit 5 for taking out only s, and an amplifier 6 for amplifying the signal component Vs from the S / H circuit 5 with a predetermined high gain and taking out as an output signal S. ing.

2A of the charge transfer section 1
, The signal charge transferred from under the transfer electrode TG in the final stage is temporarily changed to the floating diffusion FD.
And a voltage change based on the accumulated charge, that is, the input signal Si is supplied to the source follower circuit 4 of the pattern output circuit 3.
To supply. The output signal Sia from the source follower circuit 4 and the input signal Si from the floating diffusion FD in the discharging element 2 have substantially the same phase.

After supplying the input signal Si to the source follower circuit 4, a reset pulse Pr is applied to the reset gate RG.
To reset the floating diffusion FD to the initial voltage Vdd, and sweeps out the charges accumulated in the floating diffusion FD to the drain region D side.

Accordingly, as shown in FIG. 3A, the waveform of the input signal Si from the floating diffusion FD input to the source follower circuit 4 has a reset period t.
r, a field through period tf, and a signal period ts. In the reset period tr, the initial voltage Vdd of the floating diffusion FD
Appear in the field through period tf, and the signal component Vs accompanying the accumulated charge appears in the signal period ts.

The S / H circuit 5 at the subsequent stage to which the sample hold pulse Ps at the output timing shown in FIG. 3B is input is output from the source follower circuit 4 by the output signal S.
During ia, only the signal component Vs is sampled and supplied to the next-stage amplifier 6. In the amplifier 6, this S / H
The sampling signal Vs from the circuit 5 is amplified at a predetermined high gain and is extracted as an output signal S shown in FIG. 3C.

In this embodiment, however, FIGS.
As shown in FIG. 2B, a dummy output section 7 having substantially the same configuration as the discharge element 2 is formed on the same substrate separately from the discharge element 2. That is, the dummy output unit 7 includes an output gate OG, a floating diffusion FD,
It is composed of a reset gate RG and a drain region D. However, since the charge transfer section 1 is not connected to the dummy output section 7, the output (dummy output signal) Sd from the floating diffusion FD is set to the floating state during the reset period tr as shown in FIG. 3D.
The initial voltage Vdd of the diffusion FD appears, and the bias potential Vb appears in the field through period tf and the signal period ts.

In this embodiment, a dummy output circuit 8 is connected to a stage subsequent to the dummy output section 7. The dummy output circuit 8 includes a source follower circuit 9 and the output element Q ₁ consists of a load resistance element Q _2, a sample hold pulse (see FIG. 3B) on the basis of the input of the Ps of the output signal Sda from the source follower circuit 9 Among them, a sampling and holding (S / H) circuit 10 for taking out only the bias potential Vb, and a bias potential Vb from this S / H circuit 10 are amplified with a predetermined high gain and taken out as an output signal Sb shown in FIG. 3E. It comprises an amplifier 11.

Further, in this embodiment, a comparator 12 for comparing the output signal Sb from the dummy output circuit 8 with a predetermined fixed potential Vd, and an AC comparison result signal Sc from the comparator 12 are converted into a DC signal Vc comprising a low-pass filter 13 to be converted into, which are connected between the respective load resistance element Q ₂ of the low-pass filter 13 and the source follower circuit 4 and 9 gates. Then, the fixed potential Vd supplied to one terminal (+ terminal) of the comparator 12 is set to, for example, an output voltage Vo corresponding to an optimum potential Vi as a bias potential in the input range shown in FIG.

Next, the operation of the solid-state imaging device according to this embodiment will be described. First, the input signal Si and the dummy signal Sd from each floating diffusion FD are supplied to the source follower circuits 4 and 9 of the pattern output circuit 3 and the dummy output circuit 8, respectively. At this time, in the pattern output circuit 3, the signal component V
After extracting only s, the signal is output as an output signal S via the amplifier 6. On the other hand, in the dummy output circuit 8, S
After taking out only the bias potential Vb in the / H circuit 10, the bias potential Vb is supplied to the (−) terminal of the comparator 12 via the amplifier 11.

At this time, if the bias potential Vb of the input signal Si and the dummy signal Sd becomes lower than the optimum bias potential Vi (see FIG. 4) due to, for example, a temperature change, the output signal Sb output from the amplifier 11 is changed to the comparator 1
2 is lower than the fixed potential Vd applied to the (+) terminal of the second comparator 2, and the comparison result signal Sc output from the comparator 12 has a form in which high-level signal components appear continuously.

[0026] As a result, each gate of each load resistance element Q ₂ of the source follower circuit 4 and 9 takes the DC signal Vc of higher potential, and accordingly, the drive current is increased, 4 and the source follower circuit 9, the output signals Sia and Sda, ie, each floating diffusion FD
Are shifted so that the bias potential Vb as a whole approaches the predetermined value Vi and constitutes a feedback circuit, and as a result, the bias potential Vb
Are held at the optimum bias potential Vi.

On the other hand, when the bias potential Vb of the input signal Si and the dummy signal Sd becomes higher than the optimum bias potential Vi, the output signal Sb output from the amplifier 11 becomes higher than the fixed potential Vd. The output comparison result signal Sc has a form in which low-level signal components appear continuously.

[0028] As a result, the direct current signal Vc of the low potential to the gates of the load resistance element Q ₂ of the source follower circuit 4, and 9-consuming, and accordingly, the drive current is decreased, 4 and the source follower circuit 9, the output signals Sia and Sda, ie, each floating diffusion FD
Input signals Si and Sd are shifted such that their bias potentials Vb approach the optimum bias potentials Vi and constitute a feedback circuit. As a result, the bias potentials Vb become the optimum bias potentials Vi. Will be retained.

As described above, according to this embodiment, the dummy signal Sd from the dummy output section 7 is supplied to the source follower circuit 9 of the dummy output circuit 8, and the bias potential Vb is supplied to the S / H circuit 10 at the subsequent stage. Only after the bias potential Vb is amplified by the amplifier 11, the comparator 12 at the next stage compares the output signal Sb from the amplifier 11 with a predetermined fixed potential Vd, and converts the comparison result into a direct current. Signal V
c, the source follower circuits 4 and 9 to which the input signal Si from the charge transfer unit 1 and the dummy signal Sd are supplied, respectively.
And the bias potential Vb of the input signal Si is adjusted to the optimum bias potential V corresponding to the predetermined fixed potential Vd.
i, the pattern output circuit 3
Even if the input range is narrowed by giving a high gain to itself, the optimum bias potential Vi can be set for the input signal Si from the charge transfer unit 1.

Therefore, for example, when the capacitance of the floating diffusion FD is reduced to increase the conversion efficiency, the coupling amount V in the input signal Si from the charge transfer unit 1 increases. The bias potential Vb of Si can be automatically set to the optimum bias potential Vi. Further, even if the bias potential Vb of the input signal Si fluctuates due to fluctuation fluctuations and environmental fluctuations (manufacturing fluctuations, temperature characteristics, etc.), it is possible to automatically set the optimum bias potential Vi. Thus, according to the solid-state imaging device of the present example, the output signal S from the pattern output circuit 3 can be stabilized, the sensitivity can be improved, and the design of the signal processing circuit connected to the next stage can be simplified. Can be planned.

In the above-described embodiment, the case where the configuration of the dummy output circuit 8 is substantially the same as that of the present pattern output circuit 3 has been described. In addition, the configuration of the dummy output circuit 8 may be the output circuit after sampling and holding. A circuit configuration up to a point where a signal having the highest gain can be obtained may be employed.

[0032]

According to the solid-state imaging device of the present invention, even if the output circuit itself has a high gain, the bias potential of the input signal from the charge transfer unit can be set to an optimum value, and Output signal from the input terminal can be stabilized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a main part of an example of an embodiment of a solid-state imaging device according to the present invention.

FIG. 2A is a sectional view taken along line AA in FIG. FIG. 2B is a sectional view taken along line BB in FIG.

FIG. 3 is a waveform chart showing signal processing of the solid-state imaging device according to the example of FIG. 1;

FIG. 4 is a characteristic diagram illustrating input / output characteristics of the solid-state imaging device according to the example of FIG. 1;

FIG. 5 is a circuit diagram showing a configuration of a main part of a solid-state imaging device according to a conventional example.

FIG. 6 is a waveform diagram showing a waveform of an input signal from a charge transfer unit.

FIG. 7 is a characteristic diagram showing input / output characteristics of a solid-state imaging device according to a conventional example.

[Explanation of symbols]

Reference Signs List 1 charge transfer unit, 2 discharge element, 3 pattern output circuit, 4 and 9 source follower circuit, 5 and 10 S / H circuit, 6 and 11 amplifier, 7 {Dummy output section, 8} Dummy output circuit, 12} Comparator, 13} Low pass filter, OG {Output gate, FD} Floating diffusion, RG
{Reset gate, D} Drain region

Claims (1)

[Claims] 1. A solid-state imaging device comprising: a charge transfer unit; an output unit connected to the charge transfer unit and having a reset gate supplied with a reset pulse; and an output amplifier supplied with an input signal from the output unit. The device, further comprising: a dummy signal processing unit that generates a signal for adjusting a bias component generated by coupling of the reset pulse among input signals supplied from the output unit to the output amplifier, A solid-state imaging device, wherein the bias component is adjusted by supplying a generated signal to the output amplifier.