JP2000353961A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture processor using a fractal encoding system or the like for efficiently realizing encoding and decoding and for reducing resources to be used. SOLUTION: Inputted picture data are divided into block lines to be encoded by an encoding block line dividing part 1, and stored in a picture buffer 2. An encoding block dividing part 3 sequentially divides this into blocks to be encoded. A reference block is extracted from the picture buffer 2 by a reference block extracting part 4 and affine-transformed by an affine transformation part 5, and a collation pattern is generated. The generated collation pattern is compared with the block to be encoded, and the collation pattern whose error with the block to be encoded is the smallest is selected by a pattern selecting part 6. Then, the information of the affine transformation applied to the selected collation pattern is encoded by an affine transformation information encoding part 7, stored in a code buffer 8 and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus for performing compression encoding and decoding of image data, especially digital still image data.

[0002]

2. Description of the Related Art Conventionally, various methods have been proposed for encoding image data. As one of the methods, there is a method of dividing image data into blocks including a predetermined number of pixels, and using an index of a pattern matching a pixel pattern of each block as a code. Typical examples include an image vector quantization method and a fractal image coding method. In the image vector quantization method, a typical pattern independent of original image data is registered in a code book in advance, and an index of a code book pattern that matches a pixel pattern of each block is used as a code. Further, the fractal image encoding method encodes information of a mapping adapted to a pixel pattern of each block in a mapping obtained by transforming and transforming an area cut out from original image data.

A more strict definition of the fractal image encoding method is described as follows.
An image coding method in which an affine transformation mapping of a reference area is searched for and the content of the affine transformation performed on the reference area is used as a code of the coding target area. Here, the encoding target area is divided so as not to overlap in the image, and is called a range (Range) block. In the following description, it is called an encoding target block (decoding target block in decoding). In the reference area, an arbitrary area in the image is set,
It is called a domain block. In the following description, it is called a reference block. Further, the affine transformation is a transformation that combines a primary transformation (= enlargement / reduction + rotation + line symmetry) and a translation. In addition, for the scaling of the primary conversion, each axis (vertical,
The enlargement / reduction ratio of the horizontal and pixel values) may be different. However, in the fractal image coding method, conversion is basically performed only in the reduction direction.

[0004] For details of the fractal image coding method, see, for example, Takashi Ida and Takeshi Taketake, "Coding of Images Using Fractals", Image Coding Symposium PCSJ.
91 pp. 149-152, 1991, Takaharu Tokunaga,
"Fractal", Just System, 1993, JP-A-6-98310, Mark Nelson, J
eanLoop Gailly, "The Data
Compression Book, Second
Edition ", M & T Books, 1996 and the like.

In the fractal image coding, the code of each block to be coded has only information of the affine transformation contents for the corresponding reference block, and the code amount does not increase or decrease due to the number of pixels in the block to be coded. Therefore, if a large block to be coded is used, the coding efficiency is directly improved, and an extremely high coding efficiency that cannot be obtained by a conventional coding method represented by JPEG or the like can be obtained.

Generally, the amount of image data is very large. For example, when an A4 size document is read at 400 dpi, the number of pixels is about 3,000 × 4,000. To reduce the resources required for processing to a realistic scale,
Generally, the image data is divided into blocks each including a predetermined number of pixels, and encoding is performed independently for each block.

However, in the fractal image coding method,
It is necessary to find an affine transformation map of a reference block that matches each encoding target block. Therefore, in the conventional encoding process, the entire image data is expanded in a buffer, and reference blocks are sequentially cut out from the expanded image data and affine-transformed, and are used for the encoding process. As described above, the amount of image data is very large, and enormous resources are required to expand the entire image data in a buffer and perform processing. Therefore, there is a problem that the processing scale is not realistic for use in a general device.

[0008] Several countermeasures have been considered for this problem. For example, JP-A-8-21416
Japanese Patent Application Laid-Open No. 9-29409 discloses a technique for setting a reference block including a coding target block to determine whether or not they are similar before referencing the entire image data. Is described. Accordingly, high-speed encoding can be performed only when the current block is similar to the reference block including the current block. However, for an encoding target block that does not satisfy this condition, the entire image data is referred to in the same manner as in the related art.

[0009] For example, in Japanese Patent Application Laid-Open No. 9-37082, several specific patterns are prepared in advance, and the specific pattern is compared with the block to be coded first, so that the entire image data can be obtained. There is described a technique for reducing the number of matchings and efficiently performing encoding. However, also in this case, if the specific pattern and the block to be encoded are not similar, the entire image data is referred to as in the related art.

[0010] Furthermore, for example, Japanese Patent Application Laid-Open No. 9-51539 discloses that an input image is divided into a plurality of search areas, and each of the search areas is ranked. A technique is described in which, when there is a block whose error from the affine transformation mapping is smaller than a predetermined threshold, a code is created from a reference block having the smallest error. As a result, it is possible to find out an affine transformation map suitable for each encoding target block earlier. However, the resources required for the encoding process are not considered, and the processing scale itself is not different from the conventional processing method.

Further, as described above, a search is made for a reference block of the entire image data in which the difference from the affine transformation mapping is smaller than a predetermined threshold value. A reference block may be associated. As described above, when the distance between the encoding target block and the reference block increases, the amount of code necessary for describing the translation transformation increases in the information of the affine transformation content. For this reason, the coding efficiency is reduced, and there is a possibility that the coding efficiency is not different from the conventional coding system or the coding efficiency is lower than the conventional coding system. To solve this problem, the above-mentioned documents, that is, JP-A-8-214169, JP-A-9-37082, and JP-A-9-515 are disclosed.
The technique described in Japanese Patent Publication No. 39 cannot solve the problem.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has been developed in consideration of the above-described circumstances. It is an object of the present invention to provide an image processing apparatus that uses an image processing apparatus that efficiently performs an encoding process and a decoding process and uses less resources.

[0013]

SUMMARY OF THE INVENTION The present invention relates to an image coding method which divides image data into blocks each including a predetermined number of pixels, and codes the index of a pattern which matches a pixel pattern of each block, and in particular, a fractal image. An image processing apparatus that performs encoding using an encoding method, divides input image data into encoding target block lines, and among the encoding target block lines, each encoding target block and a reference block. To perform matching with the affine-transformed pattern, select a matching pattern having the smallest error or within a predetermined error with respect to the pixel pattern of the encoding target block from the matching patterns, and generate the selected matching pattern. Is output as a code.

An image processing apparatus for decoding coded data coded as described above, wherein arbitrary image data is divided into decoding target block lines, and among the decoding target block lines, For each decoding target block, affine transformation information is extracted from the code data, a reference block to be subjected to affine transformation is extracted from the obtained affine transformation information, and an affine transformation is performed on the reference block to obtain a decoding pattern. The process of generating and applying the process to the decoding target block is performed recursively.

As described above, since the processing target is not the entire image data but the encoding target block line or the decoding target block line, resources such as a buffer for expanding the image data are reduced, and the processing amount required for collation is reduced. And the encoding and decoding processes can be performed efficiently. Even if the image data becomes large, the encoding target block and the reference block are associated within the range of the divided encoding target block line or decoding target block line. If the size is adjusted, encoding can be performed without a great distance. Therefore, it is possible to give a degree of freedom to the description of the translation transformation among the information of the affine transformation, and it is possible to perform processing with required encoding efficiency.

Further, at the time of encoding and decoding, a spare reference block can be extracted from a block line other than the block line to be coded or the block line to be decoded, and a collation pattern or a code pattern can be generated.
By setting a block that is frequently referred to as a preliminary reference block, the encoding and decoding processes can be sped up. In particular, by selecting the preliminary reference block based on the frequency of appearance of the pattern, the frequency of using the preliminary reference block as the matching pattern increases, and the processing can be further speeded up. In addition, by selecting a preliminary reference block according to the type of pattern, for example, the presence or absence of an edge, the direction of an edge, and the like, edges in a decoded image can be preserved and a clearer image can be reproduced.

[0017]

FIG. 1 is a block diagram showing a first embodiment of an image processing apparatus according to the present invention. In the figure, 1 is an encoding target block line division unit, 2 is an image buffer,
Reference numeral 3 denotes an encoding target block division unit, 4 denotes a reference block extraction unit, 5 denotes an affine transformation unit, 6 denotes a pattern selection unit, 7 denotes an affine transformation information encoding unit, and 8 denotes a code buffer. In the first embodiment, an example of a configuration in which input image data is encoded by a fractal image encoding method and code data is output is shown.

The encoding target block line dividing section 1 cuts out an encoding target block line to be encoded from the input image data. The current block line includes a plurality of current blocks.

The image buffer 2 is a buffer for storing an encoding target block line. Since the encoding target block line is a part of the input image data, the encoding target block line can be configured with a buffer having a smaller capacity than storing the input image data.

The encoding target block dividing section 3 cuts out the encoding target block to be encoded from the encoding target block line. The encoding target block has a predetermined number of pixels and is cut out as a non-overlapping area.

The reference block extracting section 4 extracts a reference block from the current block line. The reference block is extracted as an area having a size equal to or larger than the encoding target block.

The affine transformation unit 5 performs necessary affine transformation on the extracted reference block to generate a matching pattern. The affine transformation unit 5 functions as a matching pattern generation unit.

The pattern selecting section 6 compares the current block extracted by the current block dividing section 3 with the reference pattern obtained by performing the affine transformation in the affine transformation section 5 and has the smallest error. Alternatively, a reference pattern within a predetermined error is selected.

The affine transformation information coding unit 7 outputs affine transformation information applied to the matching pattern selected by the pattern selection unit 6 as code data.

The code buffer 8 is a buffer for storing the code data obtained by the affine transformation information coding unit 7. The code data may be directly output from the affine transformation information encoding unit 7 without providing the code buffer 8.

FIG. 2 is a flowchart showing an example of the operation of the image processing apparatus according to the first embodiment of the present invention, and FIG. 3 is an explanatory diagram of an example of the operation. When the image data is input in S101, in S102, the encoding target block line dividing unit 1 stores the image data corresponding to one encoding target block line in the image buffer 2.
To be stored. As shown in FIG. 3, the encoding target block line may be a part of the image data, and may be an area composed of a plurality of encoding target blocks. That is, the encoding target block line may be an area having a size composed of M × N encoding target blocks. If the number of vertical and horizontal pixels of the image data is not divisible by the number of vertical and horizontal pixels of one encoding target block, the number of pixels in one encoding target block line or all encoding target block lines is insufficient. In such a case, a pixel having a predetermined pixel value may be added, or a predetermined pixel of image data may be copied and embedded.

After the block line to be coded is stored in the image buffer 2, in S 103, the block to be coded 3 divides the pixel data corresponding to one block to be coded, for example, 8 × 8 pixels into the image buffer. Remove from 2. In FIG. 3B, each rectangle is a block to be sequentially encoded.

On the other hand, in order to find a pattern corresponding to the encoding target block, in step S104, the reference block extraction unit 4 extracts the pixel data of the reference block, for example, 16 × 16 pixels from the image buffer 2, and executes S1.
At 05, the affine transformation unit 5 performs affine transformation on the reference pattern to generate a matching pattern. FIG. 3 (B)
In the figure, four cells are shown.

Here, the affine transformation is based on spatial elements (vertical axis,
(Coordinates on the horizontal axis) and luminance elements (pixel values). As the affine transformation for the spatial element,
There are reduction, rotation, line symmetry and translation. However, if the shape and size of the reference block are fixed, the reduction ratio is uniquely determined, and the translation is also determined by the position of the encoding target block and the reference block. Therefore, the processing for the spatial element of the reference block is only rotation and line-symmetric transformation. Furthermore, since the shape of the matching pattern after affine transformation of the reference block must be equal to the shape of the block to be coded, if the number of pixels in the block to be coded is equal in the vertical and horizontal directions, the affine transformation is performed in four directions of rotation and a line. The conversion is performed in four directions of symmetry, and there are a total of eight types of matching patterns. Since the luminance element is a set of elements having only one value, the affine transformation is moved, reduced, or inverted. If image data is configured for each color component for a color image, 1
The affine transformation of the space element and the luminance element is performed for one color component.

In S106, the pattern selecting section 6
The encoding target block extracted in S103 and S105
Is compared with the collation pattern generated in. It is determined whether or not the error between the two is equal to or less than a predetermined value. If the error is equal to or less than the predetermined value, the matching pattern at that time is selected, and the process proceeds to S107. If the error is not smaller than the predetermined value, and if the error is the smallest so far, the matching pattern is temporarily stored, and the process returns to S105. In S105, a collation pattern subjected to another affine transformation is generated, and the determination in S106 is performed. The process also proceeds to S107 if the error does not become less than or equal to the predetermined value in all of the eight types of affine transformation-matched patterns.

In S107, it is determined whether the error has become equal to or less than a predetermined value, or whether all the reference blocks have been determined. If a matching pattern whose error has become equal to or less than the predetermined value has not been found yet, and reference blocks still remain, the process returns to S104, another reference block is extracted, and the processing of S105 and S106 is performed.

As a result of comparing the affine-transformed matching pattern with the coding target block for all the reference blocks that can be extracted from the coding target block line, no matching pattern with an error equal to or less than a predetermined value was found. In this case, when returning from S106 to S105, the collation pattern temporarily stored is selected. This matching pattern is the matching pattern with the smallest error.

If a matching pattern with an error equal to or less than a predetermined value or the smallest error is obtained for the encoding target block, in S108, the affine transformation information encoding unit 7 generates the matching pattern when generating the matching pattern. The contents of the affine transformation performed on the reference pattern are encoded and stored in the code buffer 8. Here, the contents of the affine transformation to be encoded include the absolute coordinates of the reference block or the relative coordinates with the encoding target block as the information of the parallel movement with respect to the space element, the information of the rotation and line symmetric transformation, the information of the movement with respect to the luminance element, Information on reduction and inversion.

When the information of the absolute coordinates of the reference block is adopted as the information of the parallel movement, the information is, for example, data of a maximum of 16 bits when the block line to be encoded is 256 × 256 pixels. In practice, the code amount is further reduced due to thinning. When information on the relative coordinates with respect to the encoding target block is adopted as the information of the parallel movement, for example, the encoding target block line is 256 × 25.
In the case of 6 pixels, the data is a maximum of 18 bits. Actually, the amount of code is further reduced because of thinning or using variable length coding. As described above, the affine transformation is performed in four directions of rotation and four directions of line symmetry.
Since it is a type, 3-bit data may be used to represent this.

The movement information for the luminance element is, for example, 1
In the case of 8 bits per pixel, the data is a maximum of 9 bits. Actually, since the quantization is performed, the code amount is further reduced. Also, information on reduction and inversion is, for example, in the case of 8 bits per pixel,
The data is a maximum of 9 bits. Also in this case, since the quantization is actually performed, the code amount is further reduced.

Thus, the processing for one encoding target block is completed. In S109, it is determined whether or not processing has been completed for all blocks in the current block line stored in the image buffer 2.
If there is an unprocessed block, the process returns to S103 to perform processing on the unprocessed block.

When the processing has been completed for all the blocks in the current block line stored in the image buffer 2, it is determined in S110 whether the encoding processing has been completed for all the image data. If an unprocessed portion remains, the process returns to S102, where a new encoding target block line is extracted and stored in the image buffer 2, and encoding processing is performed on the encoding target block line.

When the encoding of all the image data is completed, in S111, the encoded data stored in the encoded buffer 8 is output, and the process is terminated.

In this way, each block line to be coded is stored in the image buffer 2, and the block to be coded is compared with the matching pattern obtained by affine-transforming the reference block within the range of the block line to be coded. , Encoding. Therefore, the image buffer 2 does not need to store all the image data, and can be realized with a memory having a small storage capacity. Also, since the range for extracting the reference block is also within the block line to be encoded,
The number of comparison processes is significantly reduced, and the amount of processing can be drastically reduced. Therefore, the encoding process can be performed efficiently, and the circuit can be configured with a practical-scale circuit.

Further, although the code includes the absolute coordinates or relative coordinates of the reference block as the information of the parallel movement, since the absolute coordinates or relative coordinates within the range of the block line to be coded may be used, the image data becomes large. However, the configuration can be such that the data amount is not increased. Therefore, efficient code data can be output.

FIG. 4 is a block diagram showing an image processing apparatus according to a second embodiment of the present invention. In the figure, 11 is a code buffer, 12 is an image file, 13 is a decoding target block line division unit, 14 is an image buffer, 15 is a decoding target block division unit, 16 is an affine transformation information decoding unit,
17 is a decoding pattern generation unit, 18 is a decoding pattern insertion unit, 19 is a decoding image buffer, and 20 is a decoding image file. The second embodiment shows an image processing apparatus that decodes the image data (coded data) encoded in the first embodiment and restores the original image data.

The code buffer 11 is a buffer for storing code data. The code data to be decoded is
Once stored in the code buffer 11.

The image file 12 is an image file having the same size as the original image. The initial contents are arbitrary, and are sequentially updated in the course of performing the encoding process.

The decoding target block line dividing unit 13
A decoding target block line to be decoded is cut out from the image file 12. The encoding target block line is cut out as an area including a plurality of encoding target blocks.

The image buffer 14 is a buffer for storing a decoding target block line. Since the decoding target block line is a part of the image file 12, the decoding target block line can be configured with a buffer having a smaller capacity than storing the entire image file 12.

The decoding target block dividing section 15 cuts out a decoding target block to be decoded from a decoding target block line stored in the image buffer 14. The decoding target block has a predetermined number of pixels and is cut out as a non-overlapping area.

The affine transformation information decoding section 16 decodes necessary affine transformation information from the code data stored in the code buffer 11. Thereby, information of the affine transformation performed on the reference block similar to the decoding target block is obtained.

The decoding pattern generation unit 17 extracts a reference block to be subjected to affine transformation from the affine transformation information obtained by the affine transformation information decoding unit 16, performs affine transformation on the extracted reference block, and performs decoding pattern decoding. Generate

The decoding pattern inserting unit 18 inserts the decoding pattern generated by the decoding pattern generating unit 17 into the decoded image buffer 19 as an image pattern corresponding to the block to be decoded.

The decoded image buffer 19 is a buffer for storing the decoded image. Since the decoding process is performed for each decoding target block line, the decoding image buffer 19 only needs to have a capacity capable of storing the decoding target block line. Since the decoding target block line is a part of the image data, it can be configured with a buffer having a smaller capacity than storing the entire image data.

The decoded image file 20 is a decoded image file. The decoded image file 20 can be stored together with the image file 12 in an external large-capacity storage device such as a disk device. The decoded image file 20 may be shared with the image file 12.

FIG. 5 is a flowchart showing an example of the operation of the image processing apparatus according to the second embodiment of the present invention, and FIG. 6 is an explanatory diagram of an example of the operation. When the code data is input in S121, the input code data is temporarily stored in the code buffer 11.

In S122, an image file 12 (the image to be decoded shown in FIG. 6A) having the same size as the original image data is prepared. The content of the prepared image file 12 is arbitrary. In S123, the decoding target block line dividing unit 13 divides the image file 12 into image data corresponding to the decoding target block line, and one of the decoding target block lines is stored in the image buffer 14. As shown in FIG. 6, it is composed of a plurality of encoding target blocks. If the number of vertical and horizontal pixels of the original image data cannot be divided by the number of vertical and horizontal pixels of one decoding target block, a pixel having a predetermined pixel value is added to the decoding target block line that lacks pixels. Alternatively, a predetermined pixel of the image data may be copied and embedded. Since the image file 12 may be an arbitrary image,
When the image file 12 is prepared, it can be prepared as image data of a size divisible by the number of pixels in the vertical and horizontal directions of the decoding target block.

In step S124, the decoding target block dividing unit 15 extracts one block to be decoded from the decoding target block line stored in the image buffer 14.

In order to generate a pattern corresponding to the decoding target block extracted in S124, in S125, the affine transformation information decoding unit 16 extracts the code data corresponding to the decoding target block from the code buffer 11 and decodes the code data. The information of the affine transformation is passed to the decoding pattern generation unit 17. In S126, the decoding pattern generation unit 17 extracts the reference block subjected to the affine transformation from the image buffer 14 based on the affine transformation information passed from the affine transformation information decoding unit 16 and performs affine transformation. To generate a decryption pattern. S127
In, the decoding pattern insertion unit inserts the decoding pattern generated in S126 into a position in the decoded image buffer 19 corresponding to the decoding target block extracted in S124.

In S128, it is determined whether or not processing has been performed on all the decoding target blocks in the decoding target block line, and if there is an unprocessed decoding target block, the flow returns to S124 to create a new decoding target block. The decoding target block is extracted, and a decoding pattern generation process is performed on a new decoding target block.

After all the blocks to be decoded in the block line to be decoded have been processed, the decoding pattern in the decoded image buffer 19 is written to the decoded image file 20 in S129. Then, in S130, it is determined whether or not the processing for all the decoding target block lines has been completed, and if unprocessed decoding target block lines remain, the process returns to S123, and a new decoding target block line is returned. And performs processing on the decoding target block therein.

When the processing for all the decoding target block lines is completed, it is determined in S131 whether or not the image of the decoded image file 20 obtained by the above processing has converged. For example, as shown in FIG. 6B, when a decoding pattern is generated for a current block to be decoded, if an image area in which the decoding pattern has not been generated is referred to as a reference block, the generated decoding pattern is It is a temporary image. It is determined in S131 whether or not the image portion in which the decoded pattern has been generated as such a temporary image has disappeared. If not converged,
In S132, the contents of the decoded image file 20 are copied to the image file 12, for example, and the above processing is recursively repeated. If the image of the decoded image file 20 has converged, the decoded image file 20 is output in S133, and the decoding process ends.

As described above, since the decoding process is performed for each decoding target block line, it is not necessary to store all the image data in the image buffer 14 and the decoded image buffer 19, and a memory having a small storage capacity is required. Can be realized. Therefore, it can be configured with a circuit of a practical scale.

FIG. 7 is a block diagram showing a third embodiment of the image processing apparatus according to the present invention. In the figure, the same parts as those in FIG. 3
1 is a preliminary reference block extracting unit, 32 is a preliminary image buffer, and 33 is a preliminary reference block updating unit. In the third embodiment, similarly to the above-described first embodiment, a configuration example in which input image data is encoded by a fractal image encoding method and code data is output is shown. Further, an example is shown in which a preliminary reference block is extracted from a line other than the encoding target block line and used.

The preliminary reference block extracting section 31 extracts a predetermined preliminary reference block from a part or all of the input image data. The preliminary image buffer 32 is a buffer for storing the preliminary reference block extracted by the preliminary reference block extraction unit 31.

The affine transformation unit 5 performs affine necessary for the preliminary reference blocks extracted by the preliminary reference block extraction unit 31 and stored in the preliminary image buffer 32 together with the reference blocks extracted by the reference block extraction unit 4. Conversion is performed to generate a matching pattern.

The preliminary reference block updating section 33 changes the preliminary reference block to be extracted in the subsequent processing based on the information on the matching pattern selected by the pattern selecting section 6. For example, the preliminary reference block can be appropriately changed according to the frequency of selection of the matching pattern, the presence or absence of an edge in the pattern, the type of the pattern based on edge information such as the direction of the edge, and the like.

In this way, for example, if the reference pattern used for generating the frequently selected matching pattern is registered in the spare reference block updating unit 33, the matching with the coding target block is completed in a short time. And the encoding process can be performed at high speed. Further, if a preliminary reference block is selected according to the type of the pattern, for example, based on the presence or absence of an edge, the direction of the edge, and the like, it is possible to improve the reproducibility when decoding an image including an edge such as a character image, for example. Will be possible.

FIG. 8 is a flowchart showing an example of the operation of the image processing apparatus according to the third embodiment of the present invention, and FIG. 9 is an explanatory diagram of an example of the operation. Steps for performing the same processing as in FIG. 2 are denoted by the same reference numerals, and redundant description will be omitted. When image data is input in S101, the encoding target block line division unit 1 stores image data corresponding to one encoding target block line in the image buffer 2 in S102.

At the same time, in S141, the preliminary reference block extraction unit 31 extracts a preliminary reference block described in a predetermined table from data that has not been taken into the image buffer 2 among the input image data, and It is stored in the preliminary image buffer 32. As shown in FIG. 9C, the spare image buffer 32 may store a plurality of spare reference blocks.

In step S103, the encoding target block dividing unit 3 extracts pixel data corresponding to one encoding target block from the image buffer 2. In order to find a pattern corresponding to the current block,
In, the reference block extraction unit 4 extracts the pixel data of the reference block from the image buffer 2.

In S105, the affine transformation unit 5 performs affine transformation on the preliminary reference block stored in the preliminary image buffer 32 in S141 or the reference block extracted from the image buffer 2 in S104, and generates a collation pattern.

In S106, the pattern selecting section 6
The encoding target block extracted in S103 and S105
Is compared with the collation pattern generated in. It is determined whether or not the error between the two is equal to or less than a predetermined value. If the error is equal to or less than the predetermined value, the matching pattern at that time is selected, and the process proceeds to S107. If the error is not smaller than the predetermined value, and if the error is the smallest so far, the matching pattern is temporarily stored, and the process returns to S105. In S105, a collation pattern subjected to another affine transformation is generated, and the determination in S106 is performed. The process also proceeds to S107 if the error does not become less than or equal to the predetermined value in all of the eight types of affine transformation-matched patterns.

In S107, it is determined whether or not the error has become equal to or less than a predetermined value, or whether or not the determination has been made for all the preliminary reference blocks and reference blocks. If a matching pattern whose error has become equal to or less than the predetermined value has not been found yet, and a spare reference block or reference block still remains, the process returns to S105 or S104, where another spare reference block or reference block is extracted and S105. , S106.

As a result of comparing the reference pattern subjected to affine transformation with the target block to be encoded for all the reference blocks that can be extracted from the target block line, no reference pattern having an error less than or equal to a predetermined value was not found. In this case, when returning from S106 to S105, the collation pattern temporarily stored is selected. This matching pattern is the matching pattern with the smallest error.

If a matching pattern with an error equal to or less than a predetermined value or the smallest error is obtained for the encoding target block, the affine transformation information encoding unit 7 generates this matching pattern in S108 when generating the matching pattern. The contents of the affine transformation performed on the reference pattern are encoded and stored in the code buffer 8. Here, the contents of the affine transformation to be encoded are information on translation of a spatial element, information on rotation and line-symmetric transformation, information on movement on a luminance element, and information on reduction and inversion. The information of the translation is the absolute coordinates of the reference block, the relative coordinates with the encoding target block, or the coordinates of the preliminary reference block. As the coordinates of the spare reference block, for example, when the encoding target block line is 256 × 256 pixels, the maximum is only 16 bits indicating the position in the encoding target block line and the index indicating the encoding target block line. Data is required. In practice, the amount of code is further reduced due to thinning. Other information is the same as in the above-described first embodiment.

Thus, the process for one encoding target block is completed. In S109, it is determined whether or not processing has been completed for all blocks in the current block line stored in the image buffer 2.
If there is an unprocessed block, the process returns to S103 to perform processing on the unprocessed block.

When the processing has been completed for all the blocks in the block line to be encoded stored in the image buffer 2, it is determined in S110 whether the encoding processing has been completed for all the image data. If an unprocessed portion remains, the process returns to S102, where a new encoding target block line is extracted and stored in the image buffer 2, and encoding processing is performed on the encoding target block line.

At the same time, in S142, the preliminary reference block updating unit 33 updates a table to be referred to in order to extract a preliminary reference block. For example, it is possible to determine whether or not to place the reference block in the table according to the appearance frequency of the reference block used in the encoding so far, and update the table. Alternatively, the table may be updated according to the type of the pattern such as the presence or absence of an edge and the direction of the edge. After that, returning to S141, the preliminary reference block extraction unit 31 extracts the preliminary reference block according to the updated table, and uses the preliminary reference block in processing on a new encoding target block line.

When encoding of all the image data is completed, in S111, the encoded data stored in the encoded buffer 8 is output, and the process is terminated.

As described above, as in the first embodiment, the image buffer 2 only needs to have a capacity capable of storing the block line to be coded, and the range from which the reference block is to be fetched is also the range to be coded. Since it is within the block line, the encoding process can be performed efficiently.

Further, for example, by using a frequently used spare reference block, the probability that the matching pattern obtained by affine-transforming the spare reference block and the encoding target block is high is increased, and the matching pattern selection process is performed. It can be completed in a short time. Therefore, encoding can be performed at high speed. At this time, for example, by arranging the preliminary reference blocks in descending order of the use frequency, it is possible to end the process of selecting the matching pattern at an earlier stage, and it is possible to perform encoding at a higher speed.

Further, when a reference block is selected from the block lines to be coded, the number of patterns is reduced as compared with the case where a reference block is selected from the entire image, so that the matching accuracy may be reduced. However, by extracting and accumulating a frequently used spare reference block from another encoding target block line as a spare reference block, it is possible to minimize a decrease in matching accuracy.

If a preliminary reference block is selected in accordance with a pattern type such as edge information such as the presence or absence of an edge and the direction of the edge as the preliminary reference block, the preservation of the edge is improved particularly in an image including many edges. That is, it is possible to improve the reproducibility of edges when decoding.

FIG. 10 is a block diagram showing an image processing apparatus according to a fourth embodiment of the present invention. In the figure, the same parts as those in FIG. 4 are denoted by the same reference numerals, and redundant description will be omitted. Reference numeral 41 denotes a preliminary reference block extraction unit, and reference numeral 42 denotes a preliminary image buffer. The preliminary reference block extraction unit 41 extracts an area called as a preliminary reference block from the image file. In addition, the affine transformation information decoding unit 16 acquires information on the reference block used for the affine transformation, and updates the preliminary reference block according to, for example, the frequency of use and the type of pattern. The spare image buffer 42
This is a buffer for storing the preliminary reference block extracted by the preliminary reference block extraction unit 41.

FIG. 11 is a flowchart showing an example of the operation of the image processing apparatus according to the fourth embodiment of the present invention.
FIG. 12 is a diagram illustrating an example of the operation. In the figure, steps for performing the same processing as in FIG. 5 are denoted by the same reference numerals. In addition, a part of the overlapping description may be omitted. When the code data is input in S121, the input code data is temporarily stored in the code buffer 11.

At S122, an image file 12 (the image to be decoded shown in FIG. 12A) having the same size as the original image data is prepared. The content of the prepared image file 12 is arbitrary. In S123, the decoding target block line dividing unit 13 divides the image file 12 into image data corresponding to the decoding target block line, and one of the decoding target block lines is
(FIG. 12B).

At the same time, in step S151, the preliminary reference block extraction unit 41 extracts a preliminary reference block described in a predetermined table from image data that has not been captured in the image buffer 14 from the image file 12, and extracts the preliminary image buffer. 42 (see FIG. 12).
(C)).

In S124, the decoding target block dividing unit 15 extracts one block of the decoding target block from the decoding target block line stored in the image buffer 14. In order to generate a pattern corresponding to the extracted decoding target block, in S125, the affine transformation information decoding unit 16 extracts code data corresponding to the decoding target block from the code buffer 11,
Decoding and affine transformation information to decoding pattern generation unit 1
Pass to 7. In S126, the decoding pattern generation unit 17
Extracts the pre-reference block or reference block subjected to the affine transformation from the preliminary image buffer 42 or the image buffer 14 based on the affine transformation information passed from the affine transformation information decoding unit 16, To generate a decoding pattern. In S127, the decoding pattern insertion unit 18 inserts the decoding pattern generated in S126 into a position in the decoded image buffer 19 corresponding to the decoding target block extracted in S124.

In S128, it is determined whether or not processing has been performed on all the decoding target blocks in the decoding target block line, and the processing is performed until all the decoding target blocks in the decoding target block line have been processed.
Returning to S124, the generation processing of the decoding pattern corresponding to each decoding target block is repeated.

When the processing has been performed for all the decoding target blocks in the decoding target block line, the decoding pattern in the decoding image buffer 19 is written to the decoding image file 20 in S129. Then, in S130, it is determined whether or not the processing for all the decoding target block lines has been completed, and if unprocessed decoding target block lines remain, the process returns to S123, and a new decoding target block line is returned. And performs processing on the decoding target block therein.

At this time, in S152, the table referred to for extracting the preliminary reference block is updated in the same manner as in the encoding procedure, and the process returns to S151 to extract the preliminary reference block in accordance with the updated table, and The image data is stored in the image buffer 42.

When the processing for all the decoding target block lines is completed, it is determined in S131 whether or not the image of the decoded image file 20 obtained by the above processing has converged. If not converged, S1
At 32, the contents of the decoded image file 20 are copied to the image file 12, for example, and the above processing is recursively repeated. If the image of the decoded image file 20 has converged, the decoded image file 20 is output in S133, and the decoding process ends.

As described above, since the decoding process is performed for each decoding target block line, the image buffer 14 and the decoded image buffer 19 can be realized with a small storage capacity.

Further, since the decoding is performed using the preliminary reference block, for example, it is possible to decode the encoded data at a high speed using the frequently used preliminary reference block. Furthermore, by selecting a spare reference block according to the type of pattern, such as edge information such as the presence or absence of an edge and the direction of the edge, and decoding encoded data, it is possible to save edges particularly in an image containing many edges. Image with improved edge reproducibility can be restored.

In each of the above-described embodiments, the reference block is extracted from the block line to be encoded or the block line to be decoded. However, the present invention is not limited to this. May be given. Similarly, in the third and fourth embodiments, independent image data may be given as the preliminary reference block, for example, for the preliminary reference block.

[0093]

As is apparent from the above description, according to the present invention, the image data is divided into blocks each containing a predetermined number of pixels, and the index of the pattern matching the pixel pattern of each block is used as the code. In an image encoding method, particularly in fractal image encoding, resources such as an image data expansion buffer required for encoding processing can be reduced. In addition, since the amount of processing for searching for a pattern that matches the current block can be reduced, the encoding processing can be performed at high speed. Furthermore, even if it becomes necessary to take into account the correspondence between the encoding target block and the reference block that are far apart due to the increase in the image data,
Since the description of the translation transformation can be given a degree of freedom, there is an effect that processing can be performed with the required coding efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a flowchart illustrating an example of an operation of the image processing apparatus according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of an operation of the image processing apparatus according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a second embodiment of the image processing apparatus according to the present invention.

FIG. 5 is a flowchart illustrating an example of an operation of the image processing apparatus according to the second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of an operation of the image processing apparatus according to the second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a third embodiment of the image processing apparatus according to the present invention.

FIG. 8 is a flowchart illustrating an example of an operation of the image processing apparatus according to the third embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of an operation of the image processing apparatus according to the third embodiment of the present invention.

FIG. 10 is a block diagram illustrating a fourth embodiment of the image processing apparatus according to the present invention.

FIG. 11 is a flowchart illustrating an example of an operation of the image processing apparatus according to the fourth embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of an operation of the image processing apparatus according to the fourth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Encoding target block line division part, 2 ... Image buffer, 3 ... Encoding target block division part, 4 ... Reference block extraction part, 5 ... Affine transformation part, 6 ... Pattern selection part, 7
... Affine transformation information encoding unit, 8 ... Code buffer, 11
... code buffer, 12 ... image file, 13 ... decoding target block line division unit, 14 ... image buffer, 15 ...
Decoding target block division unit, 16: affine transformation information decoding unit, 17: decoding pattern generation unit, 18: decoding pattern insertion unit, 19: decoded image buffer, 20: decoded image file, 31: preliminary reference block extraction unit, 32: preliminary image buffer; 33: preliminary reference block update unit; 41: preliminary reference block extraction unit; 42: preliminary image buffer.

Claims (11)

[Claims] 1. An image processing apparatus which divides input image data into encoding target blocks including a predetermined number of pixels, and performs encoding for each encoding target block. Encoding target block line dividing means for dividing the image data input to the encoding target block line, encoding target block dividing means for dividing the encoding target block line into the encoding target block, independent image data or A reference block extracting unit that extracts a reference block including the predetermined number or more of pixels from the encoding target block line; and an affine transformation of the reference block extracted by the reference block extracting unit, and a pixel pattern of the encoding target block. Matching pattern generating means for generating a matching pattern for matching with A pattern selecting unit that selects a matching pattern having the smallest error or within a predetermined error from the pixel pattern of the encoding target block among the matching patterns generated by the pattern generating unit; An image processing apparatus comprising: an affine transformation information encoding unit that outputs, as a code, information of the affine transformation performed by the matching pattern generation unit in order to generate the matching pattern. 2. A preliminary reference block extracting means for extracting a preliminary reference block including the predetermined number of pixels or more from input image data other than image data of a block line to be encoded, and storing the preliminary reference block. The reference pattern generating means further includes an auxiliary reference block storage means for storing, and the verification pattern generation means generates the verification pattern by affine transforming the preliminary reference block stored in the preliminary reference block storage means. Item 2. The image processing device according to Item 1. 3. The preliminary reference block extracting means, when extracting the preliminary reference block, causes the preliminary reference block accumulating means to accumulate the preliminary reference block as the preliminary reference block based on the frequency of occurrence of the pattern. 3. The image processing apparatus according to claim 2, wherein the preliminary reference block stored in the preliminary reference block storage unit is taken out according to the appearance frequency of the preliminary reference block, and affine-transformed to generate the matching pattern. . 4. The pre-reference block extracting means, when taking out the pre-reference block, selects a pre-reference block to be stored in the pre-reference block storage means as the pre-reference block based on a type of a pattern. 3. The verification unit according to claim 2, wherein the generation unit extracts the preliminary reference block stored in the preliminary reference block storage unit based on a type of the preliminary reference block, performs affine transformation, and generates the matching pattern. 4. Image processing device. 5. The pattern type used as a reference when the preliminary reference block extracting means selects the preliminary reference block as the preliminary reference block is edge information such as the presence or absence of an edge in the pattern and the direction of the edge. The image processing device according to claim 4. 6. The apparatus according to claim 2, further comprising a spare reference block updating unit for supplying the matching pattern selected by said pattern selecting unit as said spare reference block candidate to said spare reference block extracting unit. Item 6. The image processing device according to any one of items 5. 7. An encoding target block line including a plurality of encoding target blocks including a predetermined number of pixels of image data, and dividing the encoding target block line into the encoding target blocks. In an image processing apparatus for decoding code data including affine transformation information of a matching pattern approximated for each decoding target block including a predetermined number of pixels, a decoding target block line including a plurality of the decoding target blocks Decoding target block line dividing means for dividing arbitrary image data, decoding target block dividing means for dividing the decoding target block line into the decoding target blocks, and extracting affine transformation information from the code data Affine transformation information decoding means, and information on the affine transformation obtained by the affine transformation information decoding means. A decoding pattern generating means for extracting a reference block to be subjected to affine transformation from the report and performing an affine transformation on the reference block to generate a decoding pattern, and the decoding pattern obtained by the decoding pattern generating means An image processing apparatus comprising: a decoding pattern insertion unit adapted to be applied to a block; wherein each unit is recursively executed. 8. A preliminary reference block extracting means for extracting a preliminary reference block including the predetermined number or more of pixels from the image data other than the image data of the decoding target block line, and storing the preliminary reference block. A preliminary reference block accumulating unit, wherein the decoding pattern generating unit accumulates in the preliminary reference block accumulating unit to perform affine transformation according to the affine transformation information obtained by the affine transformation information decoding unit. The image processing apparatus according to claim 7, wherein the preliminary reference block is extracted, and the decoded pattern is generated by performing affine transformation on the block. 9. The preliminary reference block extracting means, based on the frequency of appearance of a block to be subjected to affine transformation, from the affine transformation information obtained by the affine transformation information decoding means, 9. The image processing apparatus according to claim 8, wherein the image is stored in a storage unit. 10. The preliminary reference block extracting means stores the preliminary reference block in the preliminary reference block storage based on the type of a block to be subjected to affine transformation based on the affine transformation information obtained by the affine transformation information decoding means. 9. The image processing apparatus according to claim 8, wherein the image is stored in a unit. 11. The type of a block used as a reference when the preliminary reference block extraction unit selects the preliminary reference block as the preliminary reference block is edge information such as the presence or absence of an edge in a pattern and the direction of the edge. The image processing device according to claim 10.