JP2000353745A - Method of reducing clock skew between a plurality of clocks, and apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a design method, which increases efficiency of a design process and also realizes a reduction in the clock skew between high-accuracy clocks, and a design apparatus. SOLUTION: A clock skew reducing apparatus is constituted into a structure, where a list of the respective nets of each of a plurality of specified clock signal conductors is cut, the plurality of the clock signal conductors on the side connected with sequential elements of the specified clock signal conductors are coupled with one connection point, information on a circuit connection is changed to the tree-shaped clock signal conductors which are formed using the upstream side on the side, where it is inputted with clocks of this connection point as a common single clock signal conductor and the downstream sides of the connection point are respectively branched into the plurality of the original clock signal conductors into a tree shape. The information on the circuit connection is changed to the clock signal conductors (steps S1 to S3), and the skew between the clocks is adjusted to the above clock signal conductors with the changed information on the circuit connection, on the basis of the changed information on the circuit connection by a clock tree synthesis method (step S4). This connection point is separated from the clock signal conductors of the adjusted skew, and the upstream side of the above connection point is connected with the plurality of the original clock signal conductors (step S5).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for designing a semiconductor integrated circuit, and more particularly to a design method suitable for reducing a skew of a plurality of clocks in a layout design of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a layout design of a semiconductor integrated circuit, in order to operate a synchronous circuit with a minimum cycle time, it is necessary to supply a clock to a plurality of sequential elements constituting the synchronous circuit at the same timing. A clock signal from an external terminal or an internal clock signal generating circuit is usually driven by a clock driver, transmitted through a clock line, and supplied to a clock input terminal such as a flip-flop that forms a sequential element. A signal delay is caused by the wiring resistance and the wiring capacitance of the clock line and the capacitance of the clock input terminal of the flip-flop. If the wiring length is different, it appears as a difference (skew) in the propagation time of the clock signal. In a synchronous circuit, a malfunction may occur due to a clock skew, and it is necessary at the design stage to reduce the skew.

In order to minimize clock skew, a delay time equalizing buffer is optimally inserted into a clock wiring network, and clock lines connected to sequential elements are laid out in a tree-like manner called clock tree synthesis (CTS). Method is used.

[0004]

In recent years, the scale of a semiconductor integrated circuit and the SOC (silicon-on-chip) have been increased, and a plurality of systems are mounted on one chip and have a plurality of clock signals. Due to the increasing number of designs, it is required to reduce the clock skew between a plurality of clocks instead of one system, and to automatically reduce the skew as little as possible by hand.

[0005] However, until recently, such a request itself was small, and at present, the following method is used as a skew reducing method for a plurality of clocks.

That is, for example, an average delay is calculated after layout, and a delay (Delay) cell is inserted into a clock path to reduce clock skew.

FIG. 10 is a flowchart showing the processing procedure of this design method. Start layout based on circuit design information (circuit connection information, element library),
After wiring, a skew is obtained, and a skew is examined by inserting a delay cell for skew adjustment.

In step 104, the average delay from each clock to the flip-flop is calculated, the timing is examined, and a delay cell having an average delay difference is inserted into the circuit, and the layout is performed again.

FIG. 11 is a diagram for explaining a conventional design method. The average delay values D1 and D2 from the clocks A and B to the flip-flop are calculated, and the delay on the clock line of the clock B is set so that the average delay values are equal.
The y (delay) gate is inserted, the layout is performed again, and the skew of the clock lines of the clocks A and B is examined again.

As a result, correction such as insertion of a delay (delay) cell is manually performed on the terminal of the CAD apparatus,
For this reason, there are problems such as the occurrence of a human error, such as the accuracy, reliability, the number of man-hours, and the TAT.

Further, after the delay (delay) cell is inserted into the circuit, the layout is performed again. Therefore, depending on the layout situation, the timing study, the delay cell insertion, and the re-layout work are repeated until the skew is reduced. It has to be repeated, and in addition to the problem of increasing the TAT, there is also a problem that the operator needs specialized knowledge.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a method and an apparatus for improving the efficiency of a design process and realizing highly accurate clock skew reduction. It is in.

[0013]

SUMMARY OF THE INVENTION In order to reduce the skew between a plurality of clocks, the present invention achieves the above object by skew-adjusting a plurality of clock trees as a pseudo one clock tree by a clock tree synthesis method. In each clock line.

[0014]

Embodiments of the present invention will be described. FIG. 1 is a flowchart showing a processing procedure according to an embodiment of the present invention. By laying out a plurality of clocks to be subjected to skew as one CTS, clock skew of each flip-flop connected to the plurality of clocks is reduced. After the skew adjustment, the clock line is separated according to the original circuit connection.

A skew reduction method for a circuit in which a plurality of clocks are input and transmitted through different clock signal lines and supplied to sequential elements, includes the steps of: (a) inputting circuit connection information from a storage unit and storing the circuit connection information from the storage unit; Input, and based on the circuit connection information, disconnect the respective netlists for each of the plurality of designated clock signal lines, and couple the plurality of clock signal lines connected to the sequential element to one connection point. A circuit in which the upstream side of the connection point to which a clock is input is used as one common clock signal line, and the plurality of clock signal lines downstream of the connection point are branched in a tree shape and connected to sequential elements, respectively. Changing a clock signal line for connection (steps S1 to S3 in FIG. 1); and (b) changing the clock signal line based on the changed circuit connection information. Adjusting the skew of the adjusted signal line by the clock tree synthesis method (step S4 of FIG. 1); and (c) adjusting the skew of the clock signal line based on the original circuit connection information. Separating the connection points and reconnecting to the original plurality of clock signal lines (step S5 in FIG. 1).

The above steps are executed in a CAD device (design support device or design automation device) such as a workstation for performing an automatic layout process of a semiconductor integrated circuit. That is, according to the present invention, the circuit connection information is input, and based on the circuit connection information, the respective netlists are cut for each of the plurality of specified clock signal lines, and the plurality of clocks on the side connected to the sequential element are cut off. The signal line is coupled to one connection point, the connection point upstream side of the clock input side is a common one clock signal line, and the plurality of clock signal lines downstream of the connection point are branched in a tree shape. Means for changing the clock signal line (means for executing steps S1 to S3 in FIG. 1) to the circuit connection respectively connected to the sequential element, and the changed clock signal based on the changed circuit connection information. Means for laying out lines by clock tree synthesis to adjust skew (means for executing step S4 in FIG. 1); Means for separating the connection point and connecting to the original plurality of clock signal lines for the clock signal line whose skew has been adjusted based on the original circuit connection information (means for executing step S5 in FIG. 1) And the processing and functions of the above-described units are realized by a program executed on a computer.
In this case, the present invention can be implemented by reading out the program from a recording medium on which the program is recorded to a computer and executing the program.

According to the present invention, as in the conventional method, after arranging and wiring each clock as CTS, layout is performed again by taking measures such as inserting a delay gate to adjust the skew of each clock. This is unnecessary, and a plurality of clock skews can be automatically reduced.

Also, since the skew between clocks is adjusted by the CTS method, the skew can be adjusted more easily and more accurately than when a delay gate is inserted.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing a processing procedure of an embodiment of the present invention.

In step 1, circuit connection information is input, and a plurality of clocks whose skew is to be adjusted are designated.

In step 2, each clock line is disconnected once.

Each of the clock lines separated in step 3 is connected so as to form a pseudo one clock tree.

In step 4, in a normal layout process, C
The layout is performed by the TS method.

In step 5, each clock line is reconnected to the original clock line.

As described above, the skew between a plurality of clocks can be adjusted by skew-adjusting the plurality of clocks into one clock tree by the CTS method and separating the clocks into clock lines.

The operation of one embodiment of the present invention will be described.

First, the automatic layout will be described with reference to the circuit diagrams of FIGS.

FIG. 2 is a diagram showing an example of the circuit configuration used in step 1. The circuit connection information is stored in a storage device (not shown) that stores the circuit connection information.
It is read when the layout processing is executed.

Referring to FIG. 2, a clock line transmitting clocks A and B is designated as a skew reducing clock, and a plurality of clock lines are respectively connected to clock input terminals of flip-flops FF1 to FFn and ff1 to ffm. It is connected.

FIG. 3 is a diagram schematically showing a state in which the process of step 2 is performed, that is, a state in which each clock line is disconnected. With the disconnection of the clock line, the netlist information of the circuit connection information is changed.

FIG. 4 is a diagram showing a circuit configuration immediately before the layout design in step 3 is started. Each clock line disconnected in step 2 is connected as a pseudo one clock tree.

That is, there are provided a pseudo clock input terminal 10, a first buffer circuit 1 connected to the pseudo clock input terminal 10, and second and third buffer circuits 2, 3 for branching the output of the first buffer circuit 1. , And the outputs of the second and third buffer circuits 2 and 3 are respectively connected to the original two disconnected clock lines (clock lines connected to the flip-flop).

FIG. 5 is a diagram showing circuit connections for explaining the situation during the layout design in step 4.

As the pseudo same clock line, 1
The layout is adjusted and the clock skew is adjusted using the CTS method related to the system clock. Note that the second and third
The buffers 4, 5, 6, 7, 8, 9 and the like connected to each branch of the clock line connected to the buffer circuits 2 and 3 of the CTS method are used to equalize the delay time to each flip-flop. This is a buffer circuit (CTS buffer circuit) that is automatically arranged and wired in the layout.

FIG. 6 is a diagram showing a state after the layout design in step 5. Referring to FIG. 6, the clock lines connected to the same clock tree in a pseudo manner and laid out by the CTS method are reconnected to the clock lines of the input terminals of the clocks A and B, respectively. That is, for the clocks A and B, the buffer 1 circuit 1a,
1b is connected to a clock tree laid out by the CTS method.

On the other hand, FIG. 7 shows a method for identifying which clock line the flip-flop is connected to when the CTS method of step 4 is used. FIG. 7 shows that the net name of the clock net connected to the flip-flop is changed to “clockA” for the net connected to clock A and “clockB” for the net connected to clock B. , Whether the flip-flop was connected to clock A or clock B
Can be identified.

As described above, when the layout is performed by using the CTS method, erroneous connection can be prevented by distinguishing the net name of each clock.

In this embodiment, two clocks A and B are used.
However, it is needless to say that the same can be applied to three or more clock lines.

In addition, since the CTS method itself is automatic and has a proven track record in reducing the clock skew with respect to the processing result, as in the case of inserting a delay cell as in the related art,
There is no need to repeat the same work, simplifying the design work,
Good wiring and placement results with high clock adjustment accuracy can be obtained.

Next, a second embodiment of the present invention will be described.
The processing procedure of the second embodiment of the present invention is the same as that of the flowchart shown in FIG. 1, but when the CTS method of step 4 is used, the flip-flop connected to each clock is connected to any clock line. The method of identifying whether or not the connection is established is further devised.

FIG. 8 is a diagram showing an example of the operation of changing the instance name of the flip-flop connected to each clock.

The instance name of the flip-flop is FF
From 1 to FFn and ff1 to ffm, FF1_clock
A to FFn_clockA, ff1_clockB to f
It can be identified by replacing it with fm_clockB.

In the layout using the CTS method, erroneous connection can be prevented by changing the instance name of each flip-flop connected to the clock.

In the present embodiment, the effect is obtained that incorrect connection can be prevented by changing the instance name of each flip-flop connected to the clock.

In each of the above embodiments, the method of identifying which clock line the flip-flop is connected to when using the CTS method is obtained by changing the instance name of each flip-flop connected to the clock. However, it can also be obtained by dividing flip-flops into small groups.

Next, a third embodiment of the present invention will be described.
FIG. 9 is a diagram for explaining a third embodiment of the present invention. In the third embodiment of the present invention, the CT of step 4 in FIG.
In order to identify which clock line the flip-flop connected to each clock is connected to when using the S method, the flip-flops are divided into small groups and the number of connected flip-flops is adjusted.

Groups A1 to An, Groups B1 to Bm
The number of flip-flops connected to each group can be made equal by setting the number of flip-flops connected to each group to the greatest common divisor of the number of flip-flops connected to each clock line. .

As described above, in the layout using the CTS method according to the third embodiment of the present invention, the flip-flops of groups A1 to n are used for clock B and the flip-flops of groups B1 to m are laid out for each group. It is possible to prevent an erroneous connection that the loop is connected to the clock A.

Therefore, it is possible to identify to which clock line the flip-flop connected to each clock is connected.

[0050]

As described above, according to the present invention,
By cutting each of the plurality of clocks and temporarily forming a single clock line, clock skew can be reduced for the plurality of clocks using the conventional CTS method.

Further, according to the present invention, since the layout processing itself by the CTS method is automatic, and there is a track record of reducing the clock skew with respect to the processing result, as in the conventional case where a Delay cell is inserted. Without the need to repeat the same work, and without the need for special experience
There is an effect that an accurate result can be obtained as the skew adjustment.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a first embodiment of the present invention.

FIG. 3 is a diagram for explaining a first embodiment of the present invention.

FIG. 4 is a diagram for explaining a first embodiment of the present invention.

FIG. 5 is a diagram for explaining a first embodiment of the present invention.

FIG. 6 is a diagram for explaining the first embodiment of the present invention.

FIG. 7 is a diagram for explaining the first embodiment of the present invention.

FIG. 8 is a diagram for explaining a second embodiment of the present invention.

FIG. 9 is a diagram for explaining a third embodiment of the present invention.

FIG. 10 is a flowchart for explaining a conventional processing procedure.

FIG. 11 is a diagram for explaining a conventional layout method.

[Explanation of symbols]

 1 to 9 buffer circuit 10 pseudo clock input terminal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA04 BA06 JA01 5F064 BB26 DD04 DD25 EE03 EE47 EE54 HH03 HH05 HH06 HH12 HH20

Claims (12)

[Claims] A method for reducing skew in a circuit in which a plurality of input clocks are transmitted through different clock signal lines and supplied to sequential elements, comprising: (a) inputting circuit connection information from storage means; Based on the above, for each of the plurality of designated clock signal lines, the respective netlists are cut at one place, the plurality of clock signal lines connected to the sequential element are connected to one connection point, and the clock is input. The upstream side of the connection point on the side to be connected is a common one clock signal line, and the plurality of clock signal lines on the downstream side of the connection point are branched in a tree shape and connected to the sequential elements, respectively. (B) adjusting a skew of the changed clock signal line by a clock tree synthesis method. And (c) separating the connection points of the plurality of clock signal lines whose skew has been adjusted, and reconnecting the connection points to the original clock signal lines, respectively. . 2. In the step (a), a pseudo clock input terminal is provided, and the pseudo clock input terminal is connected to a common clock signal line upstream of the connection point, and the common clock signal is connected to the connection point. A buffer circuit having a line as an input is disposed, and a plurality of clock signal lines are branched on the output side of the buffer circuit into a plurality of clock signal lines downstream of the connection point.
The clock skew reduction method according to claim 1, wherein: 3. In the step (a), information for identifying the original clock signal before the change of the circuit connection information is added to each of the plurality of clock signals branched on the downstream side of the connection point. 3. The method according to claim 1, wherein the clock skew is reduced. 4. In the step (a), an original clock signal before changing the circuit connection information is identified for a plurality of sequential elements respectively connected to a plurality of clock signals branched on the downstream side of the connection point. 2. The clock skew reduction method according to claim 1, wherein the name is set to an instance name to which information to be added is added. 5. The clock skew reduction according to claim 1, wherein the sequential elements connected to the clock signal line are divided into groups, and the number of sequential elements connected to each clock signal line is adjusted. Method. 6. A skew reduction method for a circuit in which a plurality of input clocks are transmitted through different clock signal lines and supplied to sequential elements, wherein a plurality of clock trees are formed based on circuit connection information input from a storage means. A clock skew reduction method, which comprises simulating one clock tree, adjusting skew according to a clock tree synthesis method, and separating the clock trees. 7. A method according to claim 1, wherein a name of an original clock signal transmitted by said clock line is added as an identifier to said plurality of clock lines which are pseudo one clock tree.
Prevents incorrect connection during layout according to the clock tree synthesis method and facilitates separation after layout.
7. The clock skew reduction method according to claim 6, wherein: 8. A design apparatus for a semiconductor integrated circuit having a configuration in which a plurality of clocks are input from a clock input terminal, and the plurality of clocks are transmitted through different clock signal lines and supplied to sequential elements, respectively. Is input, and based on the circuit connection information, each of the plurality of designated clock signal lines is cut at one place, and the plurality of clock signal lines connected to the sequential element are connected to one at a time. A single clock signal line is connected to the connection point located on the clock input end side, and a plurality of clock signal lines on the downstream side of the connection point are branched in a tree shape and connected to sequential elements, respectively. First means for changing the circuit connection to a new one, and a clock tree thinning circuit for the changed signal line based on the changed circuit connection information. A second means for performing a skew adjustment by performing a layout by a cis method; separating the connection point from the layout result based on the original circuit connection information with respect to the clock signal line whose skew has been adjusted; And a third means for reconnecting to clock input terminals of a plurality of clocks, respectively. 9. The first means comprises a pseudo clock input terminal, connects the pseudo clock input terminal to a common clock signal line upstream of the connection point, and connects the common clock signal to the connection point. 9. The buffer circuit according to claim 8, further comprising: arranging a buffer circuit for inputting a line, branching into a plurality of clock signals at an output side of the buffer circuit, and forming a plurality of clock signal lines downstream of the connection point. Design equipment for semiconductor integrated circuits. 10. The method according to claim 1, wherein the first means adds, to each of the plurality of clock signals branched on the downstream side of the connection point, information for identifying the original clock signal before the change of the circuit connection information. 9. The apparatus for designing a semiconductor integrated circuit according to claim 8, wherein: 11. The first means transmits, to a plurality of sequential elements respectively connected to a plurality of clock signals branched on the downstream side of the connection point, an original clock signal before changing the circuit connection information. 9. The semiconductor integrated circuit designing apparatus according to claim 8, wherein an instance name to which identification information is added is set. 12. A design support apparatus for a semiconductor integrated circuit, wherein a plurality of clocks are input from a clock input terminal, and the plurality of clocks are transmitted through different clock signal lines and supplied to sequential elements. ) Circuit connection information is input, and based on the circuit connection information, the respective netlists are cut for each of the plurality of designated clock signal lines, and the plurality of clock signal lines connected to the sequential element are connected to one. Coupled to a connection point, the connection point upstream side located on the clock input end side is used as one common clock signal line, and a plurality of clock signal lines downstream of the connection point are branched in a tree shape and each of them is a sequential element. (B) a clock tree for the changed signal line based on the changed circuit connection information. (C) separating the connection points of the skew-adjusted clock signal lines from the layout results based on the original circuit connection information, A recording medium recording a program for causing a computer constituting the design support apparatus to execute the processing of reconnecting to the clock input terminals of a plurality of clocks, respectively, and the processing of the above (a) to (c).