JP2000353020A - Regulator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent destruction of external load equipment by suppressing abnormal rise of output voltage even when a power source input terminal to draw power source inside an IC from an output power line is opened. SOLUTION: Since output voltage of a transistor for output to output the voltage by dropping power source voltage is supplied to a feedback control circuit of the transistor Tr1 for output and a start-up circuit to start the transistor Tr1 for output through the power source input terminal VCC and the output voltage is independently supplied to the clamp circuit j through a power source input terminal for clamp, the output voltage is supplied from the power source input terminal for clamp to the clamp circuit j even when an accident that the power source input terminal VCC is opened. Thus, no output voltage of the transistor Tr1 for output rises abnormally by being clamped by the clamp circuit j and no external load is destroyed even when the accident occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a regulator circuit using an external output transistor, and more particularly to a configuration for suppressing abnormalities in a special output voltage.

[0002]

2. Description of the Related Art Conventionally, as a regulator circuit of this kind,
For example, there is a 5V regulator used as a power supply for a CPU. When an abnormal voltage is generated in the output (5V) of the 5V regulator, an external load such as a CPU, a sensor,
It has been pointed out that an I / O IC or the like is destroyed.

As a countermeasure, as shown in FIG. 6, a voltage clamp circuit j at the time of an abnormal output voltage is connected to a regulator circuit (I
C).

FIG. 6 is a circuit diagram showing a configuration example of a conventional regulator circuit. The regulator circuit mainly includes an external output transistor Tr1, a startup circuit 1, a voltage dividing circuit h, a feedback control circuit i, and a clamp circuit J on the IC 100 side.

When a power supply voltage E of 6 V to 16 V is applied, a bias voltage is applied to the base via a resistor R5, turning on an NPN transistor Tr5 and starting up an NPN transistor T5.
A high-level signal is applied to the base of r2 to turn on this transistor Tr2.

As a result, the transistor Tr5 and the transistor Tr2 are turned on, and the PNP transistor T
To set the base of r1 to low level, the transistor T
r1 is turned on, a current flows through the transistor Tr1 to the external load side, and the output voltage supplied to the external load side starts to rise. Therefore, the amplifier circuit 2 starts operating and its output goes to a low level, so that the PNP transistor Tr3 is turned on, and then the transistor Tr2 is turned off by the startup circuit 1. At this time, since the transistor Tr5 and the transistor Tr3 are on, the transistor Tr1 is still on,
The output voltage increases.

The output voltage is divided by a voltage dividing circuit composed of resistors R1 and R2, inputted to the non-inverting input terminal (-) of the amplifier circuit 2, and inputted to the inverting input terminal (+). Is compared with the reference voltage Vref. When the output voltage exceeds 5V, the output of the amplifier circuit 2 is inverted to a high level, turning off the transistor Tr3,
When the voltage drops below 5 V, the output of the amplifier circuit 2 is inverted to a low level to turn on the transistor Tr3.

As described above, when the transistor Tr3 is turned off, the current of the transistor Tr1 is reduced, and the output voltage decreases. When the transistor Tr3 is turned on, the current of the transistor Tr1 increases.
V is kept at a constant value.

However, if the output voltage becomes abnormally high due to disturbance of the output power supply line 7, radiation noise, or short-circuit of the Comp terminal to GND, the resistance R
3, a Zener diode ZD of a clamp circuit consisting of a series circuit of a Zener diode ZD and a resistor R4 is applied with a Zener voltage or more, and a current flows through the Zener diode ZD to the resistor R4, and the NPN transistor T
r4 is turned on. Thereby, the transistor Tr5
Becomes low level, the transistor Tr5 is turned off, and the transistor Tr1 is turned off, so that the output voltage does not further rise and is clamped at, for example, 7 V at the maximum.

[0010]

SUMMARY OF THE INVENTION The above conventional I
In the C type regulator circuit, as shown in FIG.
Although the terminal VCC for detecting the output voltage is rare,
May be in an open state due to disconnection or poor soldering. When this open state occurs, the output voltage cannot be fed back (sensed), and at the same time, the abnormal voltage cannot be sensed. Therefore, the feedback control circuit that holds the output voltage at a predetermined value becomes inoperable. As a result, the output voltage rises to the power supply voltage, causing a problem that the CPU, sensor, and I / O IC, which are external loads, are destroyed. In recent years, the importance of the design FMEA has been called out, and a circuit design that assumes a failure phenomenon has been required from an upstream stage of development, and it is necessary to cope with such a rare case.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a power supply system which can output power even when a power supply input terminal for drawing power from an external output power supply line into the IC is opened. An object of the present invention is to provide a regulator circuit capable of preventing an external load device from being destroyed by suppressing an abnormal rise in voltage.

[0012]

In order to achieve the above object, a first feature of the present invention is to provide a starting circuit for starting an output transistor provided between a power supply line and an output power supply line; A feedback control circuit that controls the output transistor so that an output voltage output from the output transistor becomes a predetermined voltage, a clamp circuit that suppresses an abnormal increase in the output voltage, and a power supply from the output power supply line to the feedback control circuit. In addition to a power supply input terminal for supplying power to the clamp circuit.

According to a second feature of the present invention, a starting circuit provided between a power supply line and an output power supply line for activating the output transistor, and an output voltage output from the output transistor becomes a predetermined voltage. A feedback control circuit that controls the output transistor, a clamp circuit that suppresses an abnormal increase in the output voltage, and a power supply terminal that supplies power from the output power supply line to the feedback control circuit, are connected via wiring. A power output terminal is provided, and the output voltage output from the output transistor from the power output terminal is transmitted.

A third feature of the present invention is that a starting circuit provided between a power supply line and an output power supply line for starting an output transistor, and an output voltage output from the output transistor becomes a predetermined voltage. A feedback control circuit that controls the output transistor, a clamp circuit that suppresses an abnormal increase in the output voltage, and a plurality of power input terminals that supply power to the feedback control circuit and the clamp circuit from the output power line. Is to do.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the regulator circuit of the present invention. However, the same parts as those in the conventional example will be described with the same reference numerals. The regulator circuit includes an output transistor Tr when the power is turned on.
1, a start-up circuit 1 for turning on the reference voltage 1, an amplifier circuit 2 for comparing the output voltage with the reference voltage Vref, a reference voltage Vr
ef, a reference voltage generating circuit 3, resistors R1 and R2 for dividing an external output voltage, and an external PNP transistor Tr for outputting the power supply voltage V at a predetermined voltage.
1. NPN for controlling the base voltage of the transistor Tr1
Circuit transistors Tr2 and Tr3, a resistor R3, a Zener diode ZD1, a clamp circuit j including a series circuit for detecting the clamp voltage of the resistor R4 and an NPN transistor Tr4, a transistor Tr5 for clamping the output voltage of the transistor Tr1, a transistor Tr5 , A resistor R5 for base bias, a phase adjusting capacitor C for preventing oscillation, a power supply voltage input terminal VIN, a control terminal 10 for an external transistor Tr1, and a connection terminal C for the capacitor C
and a power input terminal VCC and a power input terminal 20 for clamping.

The output voltage of the transistor Tr1 is supplied to an external load (not shown) through an external output power supply line 7, and the output power supply line 7 is connected to a power supply input terminal VCC via a power supply line 8 and a power supply line 9 via a power supply line 9. Power input terminal 2 for clamp
0 is connected. Further, the output transistor Tr1 and the capacitor C are externally mounted, and the other components are mounted on the IC 100 side.

Next, the operation of this embodiment will be described. When a power supply voltage E of 6 V to 16 V is applied, the transistor Tr5 is turned on, and the startup circuit 1 applies a high-level signal to the base of the transistor Tr2 to turn on the transistor Tr2. Therefore, the transistor Tr5 and the transistor Tr2 are turned on, and the base of the transistor Tr1 is set to a low level, so that the transistor Tr1 is turned on, a current flows to the external load side through the transistor Tr1, and the output voltage starts to rise. .

As a result, the amplifier circuit 2 starts operating,
Since the output goes low, the transistor Tr3
Is turned on, and then the transistor Tr2 is turned off by the startup circuit 1. At this time, since the transistor Tr5 and the transistor Tr3 are on, the transistor Tr1 remains on, and the output voltage increases.

The output voltage output from the transistor Tr1 to the external load is divided by the resistors R1 and R2, input to the non-inverting input terminal (-) of the amplifier circuit 2, and input to the inverting input terminal (+). Is compared with a reference voltage Vref (for example, 1.2 V) from the reference voltage generation circuit 3. When the voltage on the external load side exceeds, for example, 5 V, the output of the amplifier circuit 2 is inverted to a high level, and the transistor Tr3 is turned off. When the voltage becomes 5 V or less, the output of the amplifier circuit 2 is inverted to a low level, and the transistor Tr3 is turned off. Turn on Tr3.

As described above, when the transistor Tr3 is turned off, the current of the transistor Tr1 is reduced, and the output voltage to the external load decreases, and when the transistor Tr3 is turned on, the current of the transistor Tr1 increases. The voltage is kept at a constant value of 5V.

Here, when the output voltage becomes abnormally high voltage of 5 V or more due to disturbance of the output power supply, radiation noise, or short-circuit of the Comp terminal to GND, the series connection of the resistor R3, the Zener diode ZD1, and the resistor R4. The Zener diode ZD1 of the circuit receives more than the Zener voltage, and the resistance R
4, and the transistor Tr4 is turned on.

For this reason, the base of the transistor Tr5 becomes low level, the transistor Tr5 is turned off, and the transistor Tr1 is turned off. There is no further increase in the output voltage (for example, 7 V or more), and the output voltage is clamped to 7 V at the maximum.

If an accident that the output voltage is not input from the power supply input terminal VCC occurs due to a solder failure of the power supply input terminal VCC or the disconnection of the power supply line 8, the amplifier circuit 2
Does not operate, the transistor Tr3 cannot be controlled, the transistor Tr1 is turned on and released, and the output voltage starts rising abnormally.

However, in this case as well, an output voltage is independently supplied from the clamp power supply input terminal 20 to the clamp circuit j side. When the Zener diode ZD1 is applied with a Zener voltage or more due to the rise of the output voltage, the Zener diode A current flows through ZD1 and the transistor Tr4
Turns on. Therefore, the transistor Tr5 is turned off, and the transistor Tr1 is turned off. This prevents the output voltage from rising to, for example, 7 V or more.

According to the present embodiment, the power supply input terminal VC
The power input terminal V
When CC is opened, the output voltage is changed to the power input terminal VC.
Even if an accident occurs in which the input voltage is not input from C, the output voltage is independently supplied to the clamp circuit j from the clamp power supply input terminal 20, so that an abnormal increase in the output voltage is detected and the output voltage is set to a constant value. Can be clamped.
Thereby, even if the rare accident as described above occurs, it is possible to prevent an accident such as destruction of the external load device,
The reliability of the regulator circuit can be improved.

In this embodiment, the power supply input terminal VCC
If the power supply line 8 and the power supply line 9 are disconnected at the same time, an abnormally high voltage equal to the power supply voltage E is output to the external load, but both the power supply line 8 and the power supply line 9 are disconnected at the same time. Given that is extremely rare, it is unlikely that this will happen.

FIG. 2 is a circuit diagram showing a second embodiment of the regulator circuit of the present invention. However, the same portions as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In this example, the power supply voltage E of a battery or the like is used.
Although the startup circuit of the external output transistor Tr1 when is turned on is different from that of the first embodiment, the other configuration is the same and includes a power input terminal for clamping 20 in addition to the power input terminal VCC. , Output voltage is clamp power input terminal 2
0 is supplied independently to the clamp circuit j side.

When the power supply voltage E is turned on, the power supply voltage is applied to the series circuit of the resistor R6 and the Zener diode ZD2, and a constant voltage is generated at the cathode terminal of the Zener diode ZD2. This voltage is supplied to the amplifier circuit 2 via the buffer 4, and the amplifier circuit 2 is brought into an operating state.

As a result, the output of the amplifier circuit 2 goes low, turning on the transistor Tr3. At this time, since the bias voltage is applied to the base of the transistor Tr5 via the resistor R5 and the transistor Tr5 is turned on, the base of the transistor Tr1 becomes low level and the transistor Tr1 is turned on. Subsequent operations are the same as in the first embodiment.

According to the present embodiment, the power input terminal VC
Even if the output voltage cannot be inputted from the power supply input terminal VCC due to the solder failure of C or the disconnection of the power supply line, even if an accident occurs, the clamp power supply input terminal 20 is provided in the clamp circuit j.
Output voltage is supplied independently from the
Can detect an abnormal rise in the output voltage and clamp the output voltage to a constant value. For this reason, even if a rare accident as described above occurs, an accident such as destruction of an external load device can be prevented, and the reliability of the regulator circuit can be improved.

FIG. 3 is a circuit diagram showing a third embodiment of the regulator circuit of the present invention. However, the same portions as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The circuit on the IC 100 side of this example is shown in FIG.
The same operation as that of the first embodiment is performed.

The difference is that the circuit on the IC 100 side has a power supply output terminal 30 for outputting the output voltage of the transistor Tr1 to the outside.
The output voltage input from the CC is connected to the power output terminal 30 through the wiring 6 on the IC 100 side. Therefore,
In this example, an external load (not shown) is connected to the external output terminal 30.

According to the present embodiment, the power supply input terminal VC
If the output voltage is not input from the power input terminal VCC due to the solder failure of C or the cut of the power line, the output voltage is not transmitted from the power input terminal VCC to the power output terminal 30, so that the external load is abnormal. It can be prevented from being destroyed by the voltage, and the reliability of the regulator circuit can be improved.

The power input terminal VCC and the power output terminal 3
When the wiring 6 connecting 0 is made of aluminum, the resistance of the wiring 6 becomes high, and when the external load current reaches several hundred mA, the voltage drop due to this resistance cannot be ignored and the output voltage accuracy decreases. However, if copper or the like is used, the above effects can be obtained with low loss.

FIG. 4 is a circuit diagram showing a fourth embodiment of the regulator circuit of the present invention. However, the same portions as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The circuit on the IC 100 side of this example is shown in FIG.
The same operation as that of the first embodiment is performed. In this example, in addition to the power supply input terminal VCC and the clamp power supply input terminal 20, a further clamp power supply input terminal 21 is provided.
And the power input terminal 21 for clamping is also connected to the power line 22.
Is connected to the output power supply line 7 via
Power is received by route.

As a result, power is supplied to the clamp circuit j unless the power lines 8 and 22 are disconnected at the same time.
The probability that the power supply for clamping cannot be secured can be significantly reduced, and the clamp circuit j can always detect the abnormal rise of the output voltage, clamp the output voltage to a constant value, and reduce the external load caused by the abnormal rise of the output voltage. Accidents such as destruction of equipment can be reliably prevented.

The number of power supply input terminals for clamping provided separately may be two or more.

FIG. 5 is a circuit diagram showing a fifth embodiment of the regulator circuit of the present invention. However, the same portions as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The circuit on the IC 100 side of this example is shown in FIG.
The same operation as that of the first embodiment is performed. This embodiment is not of a type in which a power input terminal for clamping is separately provided in addition to the power input terminal VCC. Instead, a power supply line 8 is commonly connected to the clamp circuit j and the amplifier circuit 2 from the power input terminal VCC. Power supply is provided.

Further, another power input terminal VCC1 is provided as the power input terminal VCC, and power is received from the output power line 7 by two power input terminals VCC and VCC1. As a result, the power is supplied to the clamp circuit j unless the power lines 8 and 23 are disconnected at the same time. Therefore, the probability that the power supply for clamping cannot be secured due to the disconnection of the power lines 8 and 23 can be significantly reduced. The circuit j can detect the abnormal rise of the output voltage and clamp the output voltage to a constant value, and can surely prevent an accident such as destruction of an external load device due to the abnormal rise of the output voltage. Note that two or more power input terminals may be separately provided.

[0040]

As described above in detail, according to the regulator circuit of the present invention, even if the power supply input terminal for drawing the power from the external output power supply line to the inside of the IC is opened, the output voltage is abnormally increased. Thus, destruction of the external load device can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a regulator circuit of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the regulator circuit of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the regulator circuit of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the regulator circuit of the present invention.

FIG. 5 is a circuit diagram showing a fifth embodiment of the regulator circuit of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a conventional regulator circuit.

FIG. 7 is a circuit diagram showing a failure occurrence example of a conventional regulator circuit. .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Start-up circuit 2 Amplifier circuit 3 Reference voltage generating circuit 4 Buffer 7 Output power supply line 8, 22, 23 Power supply line 10 Control terminal 20, 21 Power supply input terminal for clamp 30 Power supply output terminal 100 ICC capacitor j Clamp circuit R1-R6 Resistance Tr1 to Tr5 Transistor VCC, VCC1 Power input terminal ZD1, ZD2 Zener diode

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (3)

[Claims] A starting circuit provided between a power supply line and an output power supply line for activating an output transistor; and controlling the output transistor so that an output voltage output from the output transistor becomes a predetermined voltage. A feedback control circuit, a clamp circuit that suppresses an abnormal rise in the output voltage, and a power input terminal that supplies power to the feedback control circuit from the output power line, and a power supply from the output power line to the clamp circuit. A regulator circuit comprising a power supply input terminal for clamping which is independently supplied. 2. An activation circuit provided between a power supply line and an output power supply line, the activation circuit activating the output transistor, and the output transistor being controlled so that an output voltage output from the output transistor becomes a predetermined voltage. A feedback control circuit for controlling, a clamp circuit for suppressing an abnormal rise in the output voltage, and a power supply output terminal connected via a wire to a power supply terminal for supplying power to the feedback control circuit from the output power supply line, A regulator circuit for transmitting the output voltage output from the output transistor from the power output terminal. 3. A start circuit for starting an output transistor provided between a power supply line and an output power supply line, and controlling the output transistor so that an output voltage output from the output transistor becomes a predetermined voltage. A feedback control circuit, a clamp circuit for suppressing an abnormal rise in the output voltage, and a plurality of power supply input terminals for supplying power to the feedback control circuit and the clamp circuit from the output power supply line. circuit.