JP2000349627A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a PLL circuit that can reduce a phase error of a generated clock signal and decrease a bit error rate BER considerably at reproduction of data. SOLUTION: The PLL circuit consists of a phase detection circuit 10, a charge pump 20a, a loop filter 13a and a VCO 40, the phase detection circuit 10 compares a phase of a received data series with that of a clock signal generated by the VCO 40, outputs an UP signal SUP/a DOWN signal SDN, the charge pump 20a generates a charge current ICP in response to them, the charge current ICP is controlled so that its current is highest just after a change in an input signal and converged gradually to a prescribed value after that, the loop filter 30 generates a control voltage SV in response to the charge current ICP to control the oscillated frequency of the VCO 40, then the phase of the clock signal generated by the VCO 40 can be controlled, following to the phase of the input data series, so as to reduce a phase error in the clock signal and to improve data recovery accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly, to a serial data communication system provided in a receiving section of a serial interface communication device.
eam) according to a PLL circuit used for recovering (reproducing) a clock signal.

[0002]

2. Description of the Related Art Fiber channel
In a serial interface communication such as that described above, a transmitting unit modulates serialized information data into a clock signal having a predetermined frequency, and transmits the modulated data stream to a receiving side via a transmission line such as an optical fiber. On the receiving side, a data stream is received from the transmission line, a clock signal synchronized with the clock signal used on the transmitting side is reproduced from the data stream, and information data is reproduced from the received data stream using the reproduced clock signal. To restore.

In such serial data communication,
High-speed data communication can be realized using a fiber cable or a metal cable as a communication medium. In addition, since the transmission of the clock signal is unnecessary, the load on the communication line can be reduced, and highly efficient data transmission can be realized. However, on the receiving side, a clock signal reproducing circuit for reproducing the clock signal from the received data stream is required, and the accuracy of the reproduced clock signal directly affects the accuracy of the communication device.

Usually, a PLL circuit is used on the receiving side to reproduce a clock signal with high accuracy. FIG. 7 is a circuit diagram illustrating an example of the PLL circuit. As shown in the figure, this PLL circuit is a phase detection circuit (PD: Phase
Detector) 10, charge pump (CP: Charge Pump)
) 20, a loop filter 30, and a voltage controlled oscillator (VCO) 40.

The phase detection circuit 10 compares the phase of the received data stream SD with the phase of the clock signal generated by the VCO 40, and outputs an up signal S _UP or a down signal S _DW as a result of the comparison. The charge pump 20
The charge current _ICP is output according to the up signal S _UP or the down signal S _DW from the phase detection circuit 20.

The loop filter 30 includes a charge pump 2
Depending on the charge current I _CP from 0, performs charging or discharging, and outputs a control signal S _V corresponding to the charge current I _CP. The VCO 40 includes a loop filter 30
The oscillation frequency is controlled in accordance with the control signal S _V from outputs an oscillation signal. The VCO 40 is a multi-phase clock signal, for example, a plurality of clock signals P having a predetermined phase difference.
0 to Pm (m ≧ 1, an integer) is output.

Here, for example, the frequency of the clock signal used on the transmission side of the communication device is about 1 GHz (gigahertz). Thus, the data stream on the transmission line is 1 Gbps (gigabit / second). On the other hand, the center frequency of the VCO 40 is set to about 200 MHz (megahertz), and a method of reducing the operating frequency of the receiving side circuit has been conventionally known. In this case, VCO 40
Thus, ten clock signals P0, P1,..., P9 whose phases are shifted by 0.5 ns (nanoseconds) are generated. FIG.
Illustrates the waveforms of the clock signals P0, P1,..., P9. As shown, these clock signals have a period of approximately 5 ns, and each clock signal is shifted by 0.5 ns, that is, 1/10 of one cycle.

In order to generate the clock signal shown in FIG. 8, the VCO 40 can be configured by connecting a plurality of delay circuits having a delay time t _D in a ring shape, for example.
By appropriately controlling the delay time t _D of each delay circuit according to the control signal S _V , a clock signal having a constant frequency is generated. For example, the delay time t _D of each delay circuit
Are controlled to 0.5 ns, clock signals P0, P1,..., P9 of 10 phases shown in FIG. 8 are obtained from the output terminals of these delay circuits.

As described above, if the received data stream is 1 Gbps, the 1-bit data period is about 1
ns. Therefore, the clock signals P0, P1,.
From P9, the data stream SD received with every other selected clock signal can be latched. Here, for example, the data stream is latched using the clock signals P0, P2,..., P8. FIG. 9 is a timing chart showing the data latch.

[0010] The data stream SD is, for example, "0".
Alternatively, the binary data is “1”. . Therefore, as shown in FIG. 9, the data (Q
0) and the data latched by the clock signal P2 (denoted by Q2) are different from each other, the data latched by the clock signal P1 is denoted by Q1, and (Q1 = Q0), the clock signal generated by the VCO 40 The phase is ahead of the phase of the received data stream SD. Conversely, when (Q1 = Q2), the phase of the clock signal generated by the VCO 40 is
Lags behind the phase of That is, the phase detection circuit 10 may have such a phase determination function.
According to the result of the phase determination, the up signal S _UP is supplied to the charge pump 20 when the phase of the VCO 40 is delayed, and the down signal S _DW is supplied to the charge pump 20 when the phase of the VCO 40 is advanced. Charge pump 2
A control signal S _V is generated according to the charge current I _CP generated at 0, so that the clock phase of the VCO 40 can be controlled to approach the phase of the received data stream SD.

In the PLL circuit shown in FIG. 7, the phase of the clock signals P0, P1,..., P9 generated by the VCO 40 is controlled by the above-described feedback control, always following the phase of the received data stream SD, and transmitted. The clock signal used on the receiving side is completely reproduced on the receiving side. Information data can be reproduced from the received data stream SD using the generated and clock signal.

[0012]

By the way, in the above-mentioned conventional PLL circuit, information on the amount of phase difference between the clock signal and the data stream SD is not reflected in the result of the phase determination. For this reason, a phase error exists in the generated clock signal, and the phase error fluctuates with time and becomes phase noise as it is. For this reason, there is a disadvantage that a BER (Bit-error rate, bit error rate) representing the reproduction accuracy of the data reproducing unit is deteriorated.

FIG. 10 is a graph showing a cause of occurrence of a phase error. FIG (a) shows the waveforms of the charge pump current I _CP, Fig (b) shows a temporal change in the oscillation frequency f of the VCO 40, Fig. (C) is a clock signal generated by the VCO 40 phase The change with time of φ is shown.

As shown in FIG. 10A, the charge pump current I _CP is an up signal S _UP from the phase detection circuit 10.
_{Alternatively} , it is set according to the down signal _SDW . When the down signal S _DW is output, the charge pump current I _CP becomes a negative level (sink current), and accordingly, the loop filter 30 is discharged, and the level of the control signal S _V decreases. The frequency f decreases. Conversely, when the up signal S _UP is output, the charge pump current I _CP next positive level (source current), a loop filter 30 in response to this is charged, the level of the control signal S _V is increased, The oscillation frequency f of the VCO 40 increases.

As shown in FIG. 10, at the time when the direction of the charge pump current _ICP changes, for example, at times t _a and t _b in FIGS. The phases of the received data stream SD and the clock signal generated by the VCO 40 match. On the other hand, as shown in FIG. _5B , at time t ₀ which is intermediate between times t _a and t _b , the oscillation frequency f of the VCO 40 matches the reference frequency f ₀ .

The operating characteristics of the PLL circuit shown in FIG.
Until the phases match, the up signal S _UP or the down signal S _DW is supplied by the phase detection circuit 10 regardless of the magnitude of the phase difference, so that the charge pump 20 supplies the rectangular wave charge current I _CP to the loop filter 30. Is done. On the other hand, the change in the frequency in the VCO 40 is determined by the transfer characteristic of the loop filter 30 and the response characteristic of the VCO 40, and is as shown in FIG. Here, since the phase φ is obtained by integrating the frequency f,
When the frequency fluctuation curve becomes symmetrical with respect to the time axis,
The phase error no longer converges. As shown in FIG. 10 (b) and (c), when held within the oscillation frequency f is constant variation value Delta] f _max of VCO 40, the phase φ vibrate with a phase error [Delta] [phi. The phase error Δφ becomes phase noise, which causes the bit error rate BER of the data reproducing unit to deteriorate.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce a phase error and to significantly reduce a bit error rate BER in data reproduction.
An L circuit is provided.

[0018]

In order to achieve the above object, a PLL circuit according to the present invention compares the phase of an input signal with the phase of a clock signal and, based on the result of the comparison, determines a first and second phase difference. A phase comparison circuit for outputting a signal;
Receiving the first phase difference signal, the value is the largest immediately after the input of the first phase difference signal, and thereafter, the value gradually decreases.
And outputs a second charge current whose value is largest immediately after the input of the second phase difference signal, gradually decreases thereafter, and flows in a direction different from the first charge current. A charge pump, a control signal generation circuit for generating a control signal having a voltage corresponding to the first and second charge currents, and an oscillation frequency controlled in accordance with the control signal, wherein the oscillation signal is used as the clock signal. And a voltage-controlled oscillation circuit for outputting.

In the present invention, preferably, the charge pump comprises: a first capacitor charged by a predetermined current in response to the first phase difference signal;
A second capacitor charged with a predetermined current in accordance with the phase difference signal of the above, a first current generating circuit for generating the first current in accordance with a terminal voltage of the first capacitor, A second current generating circuit for generating the second current according to a terminal voltage of the second capacitor.

In the present invention, preferably, the charge pump comprises: a first capacitor charged by a predetermined current in response to the first phase difference signal;
Generating a first current in accordance with a terminal voltage of the second capacitor charged by a predetermined current in accordance with the phase difference signal of the first capacitor and a first charge current of the charge pump. And a first current generating circuit for supplying a voltage to the generating unit, and a terminal voltage of the second capacitor,
A second current generating circuit for generating a second current and supplying the generated second current to a second charge current generating section of the charge pump, wherein the charge pump includes a first current source and the first current; A first current mirror circuit that outputs a first charge current based on the current source; a second current source; and a second current mirror circuit that outputs a second charge current based on the second current source. The first current generating circuit is connected between a power supply voltage supply line and a current input terminal of the first current mirror circuit, and a terminal voltage of the first capacitor is applied to a control terminal. A first transistor for inputting the first current according to a terminal voltage of the first capacitor to a current input terminal of the first current mirror circuit, and the second current generating circuit includes: a power supply voltage supply line; And the second current above A terminal voltage of the second capacitor is applied to a control terminal, and the second current corresponding to the terminal voltage of the second capacitor is supplied to the control terminal. A second transistor for inputting to a current input terminal of the mirror circuit.

Also, in the present invention, a third transistor connected between the first transistor and a current input terminal of the first current mirror circuit, a second transistor and a second transistor A fourth transistor connected between the current input terminal of the current mirror circuit,
A current limiting current source and the current limiting current source are connected in series, a control terminal is connected to the control terminals of the third and fourth transistors, and a connection point is connected to the current limiting current source. A fifth transistor, and the first transistor
And the maximum value of the second current is controlled by the supply current of the current limiting current source.

Further, in the present invention, preferably, a first current output circuit receiving the first current and outputting the first charge current to an output terminal according to the first current;
A second current output circuit that receives the second current and outputs the second charge current to the output terminal according to the second current, wherein the first current output circuit includes: A sixth transistor connected between a power supply voltage supply line and the first current output terminal and having a control terminal connected to the first current output terminal; and a sixth current input terminal. A first current source connected between the terminal and the ground potential; a control terminal connected to the control terminal of the sixth transistor;
A seventh transistor that outputs the first charge current in accordance with a difference between a supply current of the first current source and the first current. An eighth transistor, wherein the second current output circuit is connected between a power supply voltage supply line and the second current output terminal, and a control terminal is connected to the second current output terminal. A second current source connected between the output terminal of the second current and the ground potential, and a control terminal connected to a control terminal of the eighth transistor;
A ninth transistor that outputs the second charge current in accordance with a difference between the supply current of the second current source and the second current.

In the present invention, preferably, the control signal generation circuit is charged by the first charge current, a terminal voltage is increased, and the control signal generation circuit is discharged by the second charge current. A first resistor element and a first capacitor connected in series between an output terminal of the charge pump and a reference potential; and an output terminal of the charge pump. A second capacitor connected between the reference capacitor and the reference potential.

Further, in the present invention, preferably, the voltage controlled oscillation circuit has a plurality of stages of delay circuits connected to a ring, and the delay time of each of the delay circuits is adjusted according to the control signal. Controlled.

Further, in the present invention, preferably, the input signal is a data sequence having a predetermined bit rate, and the center frequency of the voltage controlled oscillation signal is determined by the bit rate of the input signal and the bit rate of the delay circuit. It is set according to the number of stages.

According to the present invention, the PLL circuit includes a phase detection circuit, a charge pump, a control signal generation circuit, and a voltage controlled oscillation circuit (VCO). The phase detection circuit compares the phase of the input data series with the phase of the clock signal generated by the VCO, and outputs the first or second phase difference signal according to the result of the comparison. In the charge pump, in response to the first phase difference signal, a first charge current having the largest current value immediately after the start and then gradually converging to a predetermined value is generated. In response to the phase difference signal, the current value is largest immediately after the start, and thereafter the current value gradually converges to a predetermined value, and a second charge current flowing in a direction different from the first charge current is generated. For example, the first
Is the source current flowing from the output terminal of the charge pump to the outside, the second charge current is the sink current from the output terminal of the charge pump. In accordance with these charge currents, a control signal is generated by a control signal generation circuit, for example, a loop filter, and the oscillation frequency of the VCO is controlled accordingly, so that the phase of the clock signal follows the phase of the input data sequence. Is controlled as follows. As described above, in the present invention, the phase error of the clock signal generated by the VCO is reduced by controlling the waveform of the output current of the charge pump from a maximum value to a non-constant value and controlling it to converge to a predetermined value. Therefore, it is possible to improve the data reproduction accuracy.

[0027]

FIG. 1 is a circuit diagram showing an embodiment of a PLL circuit according to the present invention. As illustrated, the PLL circuit according to the present embodiment includes a phase detection circuit (PD) 10, a charge pump (CP) 20a, a loop filter 30, and a voltage controlled oscillator (VCO) 40.
Compared with the conventional PLL circuit shown in FIG.
In the LL circuit, the configuration of the charge pump 20a is different.
Other partial circuits have substantially the same configuration as the respective partial circuits of the conventional PLL circuit.

The phase detection circuit 10 compares the phase of the received data stream SD with the phase of the clock signal generated by the VCO 40, and outputs an up signal S _UP or a down signal S _DW as a result of the comparison. For example, when the phase of the data stream SD is ahead of the phase of the clock signal, an up signal S _UP is output. Conversely, when the phase of the data stream SD is behind the phase of the clock signal,
The down signal _SDW is output.

The charge pump 20a is connected to the phase detection circuit 2
The charge current _ICP is output in response to the up signal S _UP or the down signal S _DW from 0. Further, the charge pump 20a according to the present embodiment is configured such that the charge current I _CP of a certain level is controlled according to the up signal S _UP or the down signal S _DW.
Is supplied, the charge current I _CP has a high current value immediately after rising, and then gradually decreases and then converges to a constant value.

The loop filter 30 includes the charge pump 2
Depending on the charge current I _CP from 0, performs charging or discharging, and outputs a control signal S _V corresponding to the charge current I _CP. As shown, the loop filter 30
It is constructed by connecting a capacitor C _r in parallel with the resistor element R _p and a capacitor C _p connected in cascade between the output terminal and the ground potential of the charge pump 20a. The loop filter 30 has characteristics of a low-pass filter, that is, a low-pass filter, attenuates a high-frequency component in the charge current I _CP , generates a voltage signal S _V corresponding to the low-frequency component, and controls the control signal of the VCO 40. Output as In addition,
The loop filter 30 may be constituted by an active filter circuit.

[0031] VCO40 is controlled oscillation frequency in response to the control signal S _V from the loop filter 30, a plurality of clock signals P0~Pm having a predetermined phase difference (m ≧ 1, integer) to the. Here, the reference frequency f ₀ of the VCO 40
Is set according to the transmission frequency f _S and the number of clock signals 2M (2M = m + 1) used in the communication device, and (f
_S / M). For example, the transmission frequency f _S is 1 GHz,
The VCO 40 has 10 (M = 5) clock signals P0 to P9.
Is generated, the reference frequency f _{0 of the} VCO 40 is 20
It is set to 0 MHz.

FIG. 2 shows a waveform example of the clock signals P0, P1,..., Pm generated by the VCO 40. In the above example, the reference frequency f _{0 of the} VCO 40 is 200 MHz.
z, and the period T _p of each clock signal is 5n
s. The phase difference between the clock signals is represented on the time axis (T _p
/ 2M), each clock signal has a phase difference of 0.5 ns in this case.

By using such a PLL circuit, the oscillation frequency of the VCO 40 and the operating frequency of the PLL circuit can be reduced. For example, in the example described above, the operating frequency of the PLL circuit is 200 MHz, which is 1/5 of the transmission frequency of 1 GHz. Note that the constant M of the PLL circuit is set as appropriate according to the circuit to be used and the manufacturing process. In the example described above, M = 5.

Usually, a ring oscillator type VC in which a plurality of delay circuits having a predetermined delay time t _D are connected in a ring shape.
O, the above-mentioned multi-phase clock signals P0, P1,
.., Pm can be easily generated. Delay time t of each delay circuit
By controlling according to _D to control signal S _V, VC
It is possible to control the oscillation frequency of O and the phase of the clock signal.

In the PLL circuit shown in FIG. 1, the phase detection circuit 10 includes a clock signal P0,
Using P1,..., Pm, the received data stream S
D is latched, and an up signal S _UP or a down signal S _DW for controlling the oscillation frequency of the VCO 10 is generated according to the latched data. FIG. 3 shows latch data Q0, Q1, Q
2 shows a configuration of a partial circuit 10P that outputs an up signal S _UP or a down signal S _DW according to FIG. Here, the latch data Q0, Q1, and Q2 are, for example, data streams SD by clock signals P0, P1, and P2, respectively.
Is data latched.

In the phase detection circuit 10 shown in FIG. 1, in addition to the partial circuit 10P shown in FIG. 3, for example, a data latch circuit for latching a data stream SD in accordance with clock signals P0, P1,. Needless to say, there is. In addition to the latch data Q0, Q1, and Q2, a partial circuit that performs a phase determination using latch data obtained by another clock signal can be provided.

As shown in FIG. 3, the partial circuit 10P of the phase detection circuit includes exclusive OR gates 11, 12,
It comprises inverters 13 and 14 and AND gates 15 and 16. Exclusive OR gate 1
Latch data Q0, Q1 and Q1, Q2
Are respectively input. Exclusive OR gate 1
1 is input to the inverter 13, and the output of the exclusive OR gate 12 is input to the inverter 14. The outputs of the inverter 13 and the exclusive 12 are input to the AND gate 15, and the outputs of the inverter 14 and the exclusive 11 are input to the AND gate 16. The down signal S _DW is output from the AND gate 15 and the up signal S _UP is output from the AND gate 16.

FIG. 4 shows the truth values of the partial circuit 10P of the phase detection circuit shown in FIG. In FIG. 4, X and Y
Indicates binary data having a value of “0” or “1”, respectively, and PD _out indicates an output signal of the partial circuit 10P. As shown, when the latch data Q0 and Q1 match and Q2 does not match, a down signal S _DW is output, and when the latch data Q1 and Q2 match and Q0 does not match, the up signal SDW _UP is output.

The latch data Q0, Q1 and Q2 obtained by latching the data stream SD by the clock signals P0, P1 and P2 by the partial circuit 10P of the phase detection circuit described above.
, An up signal S _UP or a down signal S _DW is generated. In response to the up signal S _UP and the down signal S _DW , the charge pump 20a causes the charge current I _CP
Is generated. The loop filter 30 generates a control signal S _V corresponding to the charge current I _CP, and the clock signals P 0, P 1,.
9 is controlled, and a clock signal in phase with the received data stream SD can be generated.

FIG. 5 is a circuit diagram showing one configuration example of the charge pump 20a constituting the PLL circuit of the present embodiment. As shown, the input terminal T of the charge pump 20a
the _in1 and T _in2, down signal S _DW and up signal S _UP is a pulse signal are input. A charge current I _CP is generated according to these input signals, and the output terminal T _out
Is output to

As shown, the nMOS transistor Q1
And Q2 form a current mirror circuit, and the transistor Q
Current source IS1 is connected between the supply line 1 and the power supply voltage V _CC, between the transistor Q2 and the node ND1, pM
The OS transistor P1 is connected. The down signal S _DW inverted by the inverter INV1 is input to the gate of the transistor P1. A pMOS transistor P4 and a capacitor C1 are connected in parallel between the node ND1 and a supply line of the power supply voltage V _CC . Transistor P
The down signal S _DW is applied to the gate of No. 4. Furthermore, p
The gate of the MOS transistor P5 is connected to the node ND1.

The nMOS transistors Q3 and Q4 form a current mirror circuit, and the transistor Q3 and the power supply voltage V
_A current source IS2 is connected to the supply line of _CC , and a pMOS transistor P2 is connected between the transistor Q4 and the node ND2. The up signal S inverted by the inverter INV2 is applied to the gate of the transistor P2.
_UP is entered. Between the supply line of the node ND2 and the power supply voltage V _CC, pMOS transistor P8 and the capacitor C2
Are connected in parallel. The up signal S _UP is applied to the gate of the transistor P8. Further, the gate of the pMOS transistor P9 is connected to the node ND2.

PMOS transistors P3, P5, P6
A current mirror circuit is constituted by P7, P9 and P10. The gate of the transistor P3 is grounded and is always kept on. Transistors P3, P6
And a current source IS3 are connected in series. Transistor P
The gates of P7 and P10 are both connected to the gate of transistor P6. Further, transistors P5 and P7 are connected in series, and transistors P9 and P10 are connected in series.

PMOS transistors P11 and P12, p
MOS transistors P13 and P14 each constitute a current mirror circuit. The transistor P11 and the current source IS4 are connected in series, and the node ND,
3, the output current I _BU of the transistor P10 is input.
The transistor P13 and the current source IS5 are connected in series, and the output current I _BD of the transistor P7 is input to the node ND4, which is the connection point. Here, the current sources IS4 and IS5
Suppose that both supply currents are I ₀ , the transistor P11
Current I _DW flowing through the current I _UP and the transistor P13 flows to are respectively calculated by the following equation.

[0045]

I _UP = I ₀ −I _BU (1)

[0046]

I _DW = I ₀ −I _BD (2)

The transistor P12 includes a transistor P
The current I _UP1 flows according to the current I _UP flowing through the power supply 11. n
The MOS transistors Q5 and Q6 form a current mirror circuit. By the current mirror circuit, the current I _DW1 corresponding to the current I _DW flowing through the transistor P13 is _returned to the transistor Q6.

PMOS transistors P15, P16, P
17 and P18 form a current mirror circuit. Transistors P15 and P17 are connected in series between the drain of the supply line and the transistor Q6 of the power supply voltage V _CC, connected in series between the transistors P16 and P18 to the supply line of the power supply voltage V _CC and the output terminal T _out I have. The gate of the transistor P15 is grounded, and the transistor P1
The output signal of the inverter INV3, that is, the inverted signal of the down signal S _DW is input to the gate of No. 6. Therefore, the transistor P16 is turned on while the down signal _SDW, which is a pulse signal, is being output, and turned off at other times.

When the transistor P16 is turned on, the current I _DW1 output from the drain of the transistor Q6 is turned back to the transistor P18 and output to the output terminal T _out as the current I _DW2 . That is, while the down signal S _DW is being output, the current I _DW2 output from the transistor P18 is output to the output terminal T _out as the charge current I _CP . The charge current _{ICP in} this case is a source current.

The transistors Q7, Q8, Q9 and Q10 form a current mirror circuit. Transistors Q7 and Q8 are connected in series between the drain of transistor P12 and ground potential, and transistors Q9 and Q10 are connected in series between output terminal _Tout and ground potential. The gate of the transistor Q8 is connected to the supply line of the power supply voltage V _CC , and the output signal of the inverter INV5, that is, a signal having substantially the same phase as the up signal S _UP is input to the gate of the transistor Q10. Therefore, while the up signal S _UP which is a pulse signal is being output, the transistor Q10
Turns on, otherwise turns off.

When the transistor Q10 turns on, the current I _UP1 output from the drain of the transistor P12 is turned back to the transistor Q9 side, and the current I _UP2 flows through the transistor Q9. The current I _UP2 becomes a sink current from the output terminal T _out . That is, while the up signal S _UP is being output, the negative charge current I _CP is applied to the output terminal T
is output to the _out. The charge current I _{CP in} this case is a sink current.

Hereinafter, the operation of the charge pump 20a shown in FIG. 5 will be described with reference to the waveform diagram of FIG. FIG. 6A is a waveform diagram showing the waveform of the output current I _CP of the charge pump 20a, and FIG.
_The change with time of the oscillation frequency of the VCO 40 controlled by the _CP is shown. In addition, for comparison, FIG.
Shows the waveform of the output current I _CP of the charge pump 20 of a conventional PLL circuit shown in FIG. 7, in FIG. 2 (d), shows the time course of the oscillation frequency of the VCO40 controlled accordingly.

As shown in FIG. 6A, the up signal S _UP
Is output, a negative charge current I _UP2 is output, and when the down signal S _DW is output, a positive charge current I _DW2 is output. The currents I _UP2 and I _DW2 are
As shown in FIG. 5, these are the return currents of the currents I _UP1 and I _DW1 , respectively, and correspond to the currents I _UP and I _DW obtained by the equations (1) and (2), respectively.

Hereinafter, the generation of the currents I _BD and I _BU will be described, and the waveforms of the currents I _DW2 and I _UP2 generated accordingly will be described. Currents I _BD and I _BU flowing through transistors P7 and P10 are determined by the conduction states of transistors P5 and P9, respectively. Transistors P5 and P9
Are completely on, currents I _BD and I _BU are set by the supply current of current source IS3. That is, the maximum values of the currents I _BD and I _BU are determined by the current source IS3.

When the down signal S _DW and the up signal S _UP are not input, both the input terminals T _in1 and T _in2 are held at a low level, for example, at the ground potential. At this time, both the transistors P1 and P2 are turned off. Further, since the transistors P4 and P8 are turned on, the transistors P5 and P9 are turned off. That is, when the down signal S _DW or the up signal S _UP is not input, the currents I _BD and I _{BU become} 0
It is. At this time, since the transistors P16 and Q9 are off at the output of the charge pump 20a, there is no output of the charge current _ICP .

When the up signal S _UP is output from the phase detection circuit 10, the transistor P8 switches from the on state to the off state, and the transistor P2 switches from the off state to the on state. Therefore, the capacitor C2 is charged by the current flowing through the transistor P2, and the voltage V _{ND2 of the} node ND2 gradually drops from the power supply voltage V _CC . That is, the gate voltage of the transistor P9 drops.
Assuming that the threshold voltage of the transistor P9 is V _th2 ,
When the condition (V _ND2 ≦ V _CC − | V _th2 |) is satisfied, the transistor P9 is turned on, and the current I _BU flows through the transistor P10. By charging the capacitor C2, the voltage V _{ND2 at the} node ND2 drops at a slew rate determined by the supply current of the current source IS2 and the capacitance value of the capacitor C2. The maximum value of the current I _BU is determined by the supply current of the current source IS3.

When the up signal S _UP is output from the phase detection circuit 10, the transistor P4 switches from the on state to the off state, and the transistor P1 switches from the off state to the on state. Therefore, the capacitor C1 is charged by the current flowing through the transistor P1, and the voltage V _ND1 at the node ND1 gradually drops from the power supply voltage V _CC . That is, the gate voltage of the transistor P5 drops.
Assuming that the threshold voltage of the transistor P5 is V _th1 ,
When the condition of (V _ND1 ≦ V _CC − | V _th1 |) is satisfied, the transistor P5 is turned on, and the current I _BD flows through the transistor P7. Due to the charging of the capacitor C1, the voltage V _ND1 of the node ND1 drops at a slew rate determined by the supply current of the current source IS1 and the capacitance value of the capacitor C1. The maximum value of the current I _BD is determined by the supply current of the current source IS3.

The waveforms of the charge currents I _UP2 and I _DW2 while the up signal S _UP and the down signal S _DW are being output are as shown in FIG. FIG. 2B shows the VCO4
A change in the oscillation frequency f of 0 is shown. FIG.
What shown by the solid line in (b) substantially coincides with the waveform of the control signal S _V outputted from the loop filter 30.

FIG. 6C shows a waveform of the charge current _ICP output from the charge pump 20 in the conventional PLL circuit. As shown, the conventional charge pump 20
As a result, a negative charge current I _UP0 or a positive charge current I _DW0 having a substantially constant value is output according to the up signal S _UP or the down signal S _DW . In response,
The oscillation frequency f of the VCO 40 is controlled as shown in FIG. As shown in the drawing, in the conventional PLL circuit, the change in the oscillation frequency f becomes triangular or sinusoidal and symmetrical with respect to the time axis, the frequency fluctuates greatly, resulting in a large phase error.

Comparing FIGS. 6B and 6C, in the PLL circuit of this embodiment, the current value immediately after switching from the down signal S _DW to the up signal S _UP or from the up signal S _UP to the down signal S _DW. Obtains the largest charge current I _CP (positive or negative). Thereafter, the charge current I _CP
Current value gradually decreases and converges to a constant value. For this reason, as shown in FIG. 6B, the asymmetry of the frequency variation curve is maintained even in a minute region immediately after the direction of the charge current _ICP has changed, so that the phase error can be suppressed low. is there.

As described above, according to the present embodiment, the charge pump 20a outputs the largest charge current I _CP immediately after switching between the up signal S _UP and the down signal S _DW , and thereafter gradually reduces the charge current. By controlling to converge to a constant value.
It is possible to keep the frequency fluctuation curve of the VCO 40 asymmetric and to suppress the phase error low.

[0062]

As described above, according to the PLL circuit of the present invention, since the phase error of the clock signal generated by the VCO can be reduced, the bit error rate BER of the data reproduction in the receiving unit of the serial interface communication is greatly increased. Can be reduced. As a result, in a communication device that requires a constant bit error rate BER, there is an advantage that a communication line to be used can be extended or a transfer rate can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a PLL circuit according to the present invention.

FIG. 2 is a waveform diagram of a clock signal generated by a PLL circuit of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a partial circuit of the phase detection circuit of the present invention.

4 is a diagram showing truth values of partial circuits of the phase detection circuit shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of a charge pump of the present invention.

FIG. 6 is a waveform diagram comparing the operation of the present invention and the operation of a conventional charge pump.

FIG. 7 is a circuit diagram illustrating a configuration example of a conventional PLL circuit.

FIG. 8 is a waveform diagram of a clock signal generated by a conventional PLL circuit.

FIG. 9 is a timing chart showing a data latch in the phase detection circuit.

FIG. 10 is a waveform diagram showing a cause of occurrence of a phase error in a conventional PLL circuit.

[Explanation of symbols]

10: phase detection circuit, 20, 20a: charge pump,
30: loop filter, 40: VCO, C1, C2: capacitor, INV1, INV2, INV3, INV4
INV5 ... inverter, V _CC ... the power supply voltage, GND ... ground potential.

Claims (13)

[Claims] A phase comparison circuit for comparing a phase of an input signal with a phase of a clock signal and outputting first and second phase difference signals in accordance with a result of the comparison; In response to the signal, a first charge current whose value is the largest immediately after the input of the first phase difference signal and then gradually decreases is output, and the value is the largest immediately after the input of the second phase difference signal. A charge pump that gradually decreases in value and outputs a second charge current flowing in a direction different from the first charge current, and a control signal having a voltage corresponding to the first and second charge currents And a voltage-controlled oscillation circuit that controls an oscillation frequency according to the control signal and outputs the oscillation signal as the clock signal. 2. A charge pump according to claim 1, wherein said charge pump controls connection / disconnection between a current source for outputting said first charge current and a charge current output terminal in accordance with said first phase difference signal. A switching element; and a second switching element that controls a connection / disconnection state between the current source that outputs the second charge current and the charge current output terminal in accordance with the second phase difference signal. The PLL circuit according to claim 1. 3. The charge pump according to claim 1, wherein the charge pump is charged by a predetermined current in response to the first phase difference signal, and charged by a predetermined current in response to the second phase difference signal. A first current generating circuit that generates a first current according to a terminal voltage of the first capacitor and supplies the first current to a first charge current generating unit of the charge pump; And a second current generating circuit for generating a second current in accordance with a terminal voltage of the second capacitor and supplying the second current to a second charge current generating section of the charge pump. PLL circuit. 4. The charge pump includes a first current source, a first current mirror circuit that outputs a first charge current based on the first current source, a second current source, and a second current source.
A second current mirror circuit that outputs a second charge current based on the current source of the first current mirror circuit. The first current generation circuit includes a power supply voltage supply line and the first current mirror circuit.
Connected to the current input terminal of the current mirror circuit, and the terminal voltage of the first capacitor is applied to the control terminal, and the first current corresponding to the terminal voltage of the first capacitor is supplied to the first terminal. A first transistor for inputting to a current input terminal of a current mirror circuit, and the second current generating circuit are connected between the power supply voltage supply line and a current input terminal of the second current mirror circuit, A second transistor configured to apply a terminal voltage of the second capacitor to a control terminal and to input the second current corresponding to the terminal voltage of the second capacitor to a current input terminal of the second current mirror circuit; Claim 3 having
The PLL circuit as described in the above. 5. A third transistor connected between the first transistor and a current input terminal of the first current mirror circuit; and a third transistor connected to the second transistor and the second current mirror circuit. A fourth transistor connected between the current input terminal, a current limiting current source, and a series connected to the current limiting current source, and a control terminal connected to a control terminal of the third and fourth transistors. A fifth transistor whose connection point is connected to the current limiting current source, wherein a maximum value of the first and second currents is determined by a supply current of the current limiting current source. The PL according to claim 4, which is controlled.
L circuit. 6. A first current output circuit for receiving the first current and outputting the first charge current to an output terminal according to the first current, and receiving the second current. 6. The PLL circuit according to claim 5, further comprising: a second current output circuit that outputs the second charge current to the output terminal according to the second current. 7. The first current output circuit is connected between a power supply voltage supply line and the first current output terminal, and a control terminal is connected to the first current output terminal. A sixth transistor, a first current source connected between the output terminal of the first current and a ground potential, a control terminal connected to a control terminal of the sixth transistor, 7. The PLL circuit according to claim 6, further comprising: a seventh transistor that outputs the first charge current according to a difference between a supply current of a current source and the first current. 8. The second current output circuit is connected between a power supply voltage supply line and the second current output terminal, and a control terminal is connected to the second current output terminal. An eighth transistor, a second current source connected between the output terminal of the second current and a ground potential, a control terminal connected to a control terminal of the eighth transistor, 7. The PLL circuit according to claim 6, further comprising: a ninth transistor that outputs the second charge current according to a difference between a supply current of a current source and the second current. 9. The control signal generating circuit according to claim 1, further comprising a capacitor charged by the first charge current, a terminal voltage of which rises, discharged by the second charge current, and a terminal voltage of which falls. P described
LL circuit. 10. A control signal generating circuit comprising: a first resistor element and a first capacitor connected in series between an output terminal of the charge pump and a reference potential; an output terminal of the charge pump; 2. The PLL circuit according to claim 1, further comprising a second capacitor connected between the reference capacitor and the reference potential. 11. The PLL circuit according to claim 1, wherein said input signal is a data sequence having a predetermined bit rate. 12. The voltage controlled oscillation circuit according to claim 1, wherein the voltage controlled oscillation circuit has a plurality of delay circuits connected to a ring, and a delay time of each of the delay circuits is controlled according to the control signal. PLL circuit. 13. The center frequency of the voltage controlled oscillation signal is:
13. The PLL circuit according to claim 12, wherein the PLL circuit is set according to a bit rate of the input signal and the number of stages of the delay circuit.