JP2000349296A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain a stepped part from affecting the characteristics of a semiconductor device by a method wherein an active layer is equipped with a first, a second, and a third region, and the second region is brought into contact with the first region and the edge of the active layer. SOLUTION: An active layer is equipped with a first region 104a, second regions 104b and 104c, and a third region, only a part of the first region 104a forms a channel forming region, and the second regions 104b and 104c near a gate electrode 105 are set high in resistance. The second regions 104b and 104c are brought into contact with the first region 104a where the gate electrode 105 is superposed and the edge of the active layer, by which a current is restrained from concentrating locally on a point. By thins setup, a stepped part is restrained from affecting the characteristics of a device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit constituted by thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

FIG. 9 shows a top view and a sectional view of a general TFT. In FIG. 9, 11 is a substrate, 12 is a drain region, 13 is a source region, 14 is a channel formation region, 15
Is a gate wiring, 16 is a gate insulating film, 17 is an interlayer insulating film, 18 is a drain wiring, and 19 is a source wiring. Note that the channel forming region 14 is a region (having a channel length L and a channel width W) existing below the gate wiring 15.
It is.

In the step of manufacturing the TFT shown in FIG. 9, a semiconductor film patterned in an island shape is
Used as an active layer of FT, a gate insulating film 16 is formed on the active layer.
Is formed, a step 10 is formed in the gate insulating film at the end of the active layer. Therefore, the gate insulating film 16
The film thickness at the step portion 10 was smaller than the film thickness at the central portion of the active layer. In the portion where the thickness of the gate insulating film 16 is reduced, that is, in the stepped portion 10, the electric field intensity of the gate voltage is increased and the stress on the gate voltage is increased, thereby adversely affecting the withstand voltage and reliability of the TFT element. Was.

In addition, since the stress of the substrate and each thin film concentrates on the step portion 10, a change in device characteristics is caused, which is a problem.

As a means for improving the problem caused by the step 10, a means for forming the end of the active layer into a tapered shape has been considered. However, the concentration of electric fields and stresses remains a problem. In addition, since the thickness of the semiconductor film at the end of the channel formation region is reduced, the spread of the depletion layer in the vertical direction at the time of channel formation is limited, so that the charge amount of the depletion layer controlled by the gate voltage decreases. Channels are easily formed. As a result, the current tends to concentrate and flow more easily at the end portion than at the center portion of the channel formation region, so that a problem such as deterioration due to hot carriers is promoted.

As another means for solving the problem caused by the step 10, a means for increasing the thickness of the gate insulating film at the end of the active layer has been considered. However, in order to realize this structure, it is necessary to increase the number of TFT manufacturing steps, which causes a problem of lowering the throughput and increasing the cost.

As described above, some means for solving the problem caused by the step 10 have been proposed, but none of them has been satisfactory.

[0010]

SUMMARY OF THE INVENTION The present invention is directed to a structure for reducing fluctuations in device characteristics, which is considered to be mainly caused by a partial thinning of a gate insulating film formed by an end portion of an islanded active layer. The task is to provide

The present invention is a technique for solving such a problem, and includes a portion in which the thickness of a gate insulating film is reduced,
That is, an object is to reduce the influence of the step portion on the element characteristics and improve the reliability of the element. Another object is to provide a manufacturing method for realizing such a semiconductor device.

[0012]

According to the invention disclosed in this specification, an active layer made of a thin film semiconductor formed in an island shape on an insulating surface, a gate insulating film covering the active layer, and a gate insulating film are provided. TFT consisting of a gate electrode formed on an insulating film
Wherein the active layer includes a first region overlapping the gate electrode, a second region including an intrinsic or substantially intrinsic region, and a third region to which an impurity element is added. Wherein the second region is in contact with the first region and is in contact with an end of the active layer.

According to another aspect of the present invention, there is provided an active layer made of a thin film semiconductor formed on an insulating surface in an island shape, a gate insulating film covering the active layer, and a gate formed on the gate insulating film. A semiconductor device including a TFT including an electrode, wherein the active layer includes: a first region overlapping the gate electrode; a second region to which a first impurity element is added;
A third region to which an impurity element is added, wherein the second region is in contact with the first region and is in contact with an end of the active layer. .

In the above structure, the first impurity element is an impurity element that imparts P-type or N-type to the second region.

Further, in the above structure, the second impurity element is an impurity element that imparts P-type or N-type to the third region.

Further, in the above structure, the concentration of the first impurity element added to the second region is lower than the concentration of the second impurity element added to the third region.

In any one of the above structures,
The second region has a higher electric resistance than the third region.

In any one of the above structures,
Length X of the boundary between the first area and the second area
Is larger than the width Z of the gate electrode.

Further, in any one of the above configurations,
A boundary between the first region and the third region does not contact an end of the active layer.

Further, in any one of the above structures,
The third region is a source region or a drain region.

According to another aspect of the present invention, there is provided an active layer made of a thin film semiconductor formed on an insulating surface in an island shape, a gate insulating film covering the active layer, and a gate formed on the gate insulating film. A semiconductor device including a TFT including an electrode, wherein the active layer includes a first region overlapping the gate electrode, a second region not overlapping the gate electrode, a source region, and a drain region. The semiconductor device is characterized in that four of the second regions are arranged in a region in contact with the first region in an end of the active layer.

In another aspect of the invention, an active layer made of a thin film semiconductor is formed on an insulating surface in the form of an island, a gate insulating film covering the active layer, and a gate formed on the gate insulating film. A semiconductor device including a TFT including an electrode, wherein the active layer includes a first region overlapping the gate electrode, a second region not overlapping the gate electrode, a source region, and a drain region. The second region may include, among the ends of the active layer, the first region on the drain region side.
And a semiconductor device arranged in a region in contact with the region.

In any one of the above structures,
The first region and the second region are intrinsic or substantially intrinsic regions.

In any one of the above structures,
The second region has a higher electric resistance than the source region or the drain region.

In another aspect of the present invention, an active layer made of a thin film semiconductor is formed on an insulating surface in the form of an island, a gate insulating film covering the active layer, and a gate formed on the gate insulating film. A semiconductor device including a TFT including an electrode, wherein the active layer includes a source region, a drain region, and an intrinsic or substantially intrinsic region sandwiched between the source region and the drain region; The layer has a region where the distance between the source region and the drain region is different, and the distance between the source region and the drain region has a maximum value at an end of the active layer. It is a semiconductor device.

In any one of the above structures,
An end of the active layer may have a tapered shape.

Further, the invention for realizing the above structure comprises a step of forming an active layer by patterning a semiconductor thin film, and a step of forming a gate electrode above the active layer via an insulating film. Forming an island-shaped mask pattern having a width Y and a length X above an end of a region of the active layer overlapping with the gate electrode; and forming the island-shaped mask pattern with the gate electrode and the island-shaped mask pattern. Adding an N-type or P-type impurity element to the active layer as a mask.

In the above structure, the length X of the island-shaped mask pattern in the longitudinal direction of the gate electrode is provided.
Is larger than the width Z of the gate electrode.

In each of the above structures, a width Y of the island-shaped mask pattern in a direction perpendicular to a longitudinal direction of the gate electrode is larger than a width Z of the gate electrode.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION The present inventor used a hot carrier analyzer (C3230: manufactured by Hamamatsu Photonics) to perform TF analysis.
T was observed. This hot carrier analyzer is an apparatus that detects weak light emission accompanying hot carriers mainly generated in an electric field concentration portion at a photon count level and forms an image. FIG. 10 shows a photograph (top view) observed by this hot carrier analyzer. This TFT emits strong light at two places, and this light emitting portion is considered to be the main cause of deterioration of device characteristics due to hot carriers.
The light emitting portion includes a region where the active layer overlaps the gate electrode and a region where the active layer is connected to the drain wiring (drain region).
And the gate electrode overlapped with the edge of the active layer. In this part, it is considered that a part of the gate insulating film is partially thinned at the step. Therefore, it is presumed that the current was concentrated at the end of the drain region in contact with the stepped portion overlapping with the gate electrode, and light emission occurred.

When the dependence of the TFT characteristics on the channel width W was evaluated, it was found that as the channel width W became smaller, the apparent μFE became larger.

In addition, one of the typical reliability tests, B
T test (stress condition: gate voltage V _G = + 20 V (n
(Channel type), −20 V (p-channel type), drain voltage V _D = source voltage V _S = 0 V, 150 ° C., test time 1 hour) and the channel width W dependency was evaluated. according, it was found that the parallel characteristics are greatly shifted relative to V _G axis at I _D -V _G characteristics.

From these facts, the present invention provides a TFT having a structure which overlaps with the gate electrode and has a structure in which current is not concentrated at the end of the active layer (at least the end of the drain region) in contact with the step. . The present invention is characterized in that a region having a high electric resistance is provided in a region of an active layer in contact with a step portion overlapping with a gate electrode so that current is not concentrated on a region of the active layer in contact with a step portion overlapping with the gate electrode. .

Further, the region having a high electric resistance value (hereinafter referred to as a region having a high electric resistance)
The high-resistance region) has a higher value than the electric resistance of the source region or the drain region, thereby preventing concentration of current generated in the region of the active layer in contact with the step portion overlapping with the gate electrode. . Therefore, the impurity concentration in the high-resistance region may be lower than the impurity element concentration in the source region and the drain region. Note that the impurity element included in the high-resistance region has the same conductivity type as the impurity element included in the source region and the drain region, and is different from the impurity element included in the source region and the drain region. It may be an impurity element imparting a different conductivity type.

With the above structure, the distance between the source region and the drain region is different between the center of the active layer and the end of the active layer in which the high-resistance region is provided. The distance between the region and the drain region has a maximum value.

With the above structure, current is prevented from being concentrated on the end of the active layer (at least the end of the drain region) which overlaps the gate electrode and is in contact with the step.

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1A shows a top view of a TFT utilizing the present invention, and FIGS. 1B, 1C and 1D.
Respectively show AA ′, BB ′, CC ′ in FIG.
It is sectional drawing cut | disconnected by.

In FIG. 1, reference numeral 101 denotes a substrate having an insulating surface; and 102 and 103, a pair of impurity regions formed by adding an impurity element imparting N-type or P-type to an active layer formed of a semiconductor thin film, respectively. (Source region or drain region).

Then, a pair of impurity regions 102 and 103
Or substantially intrinsic semiconductor region 104 sandwiched between
a, 104b, and 104c are formed. here,
In the intrinsic or substantially intrinsic semiconductor region, a region overlapping with the gate electrode 105 is called a first region 104a, and a region not overlapping with the gate electrode 105 is defined as a second region 104a.
b, 104c.

The term “electrode” in this specification refers to
It is a part of the “wiring” and refers to a portion where electrical connection with another wiring or a portion intersecting with a semiconductor layer is made. Therefore,
For convenience of explanation, we use "wiring" and "electrode" properly,
It is assumed that the term “electrode” always includes “wiring”.

In this specification, an intrinsic semiconductor region refers to a completely neutral semiconductor region to which an impurity exhibiting one conductivity is not added at all. The term “substantially intrinsic” means that the threshold voltage can be controlled (the impurity concentration of N-type or P-type is 1 × 10 ¹⁷ atoms / cm ^3).
(Hereinafter, preferably 1 × 10 ¹⁶ atoms / cm ³ or less) means an N-type or P-type region or a region where the conductivity type is intentionally canceled.

The first region 104a is a region which is located directly below the gate electrode 105 through the gate insulating film 106 in FIG. 1A, and uses the gate electrode as a mask when forming a source region or a drain region. Thus, they are formed in a self-aligned manner. Further, since the first region 104a overlaps with the gate electrode 105, a channel formed at the time of TFT operation is formed in the first region 104a.

In the case of the structure shown in FIG. 1, it is considered that carriers move preferentially in the region where the pair of impurity regions 102 and 103 are closest. The second, high-resistance region
By providing the regions 104b and 104c,
(A second region 104b, 104c)
A region that is in contact with the carrier) hardly contributes to carrier movement, and therefore cannot be called a channel forming region (carrier movement route) strictly. Note that in this specification, only an intrinsic or substantially intrinsic semiconductor region which exists below the gate electrode and serves as a carrier movement path is referred to as a channel formation region.

That is, in FIG. 1, a region which can be called a channel formation region (carrier moving route) is a first region 1
Only a part of 04a (a region where a pair of impurity regions 102 and 103 are close to each other).

The second region 104 near the gate electrode
Also in b and 104c, a channel is formed during the TFT operation, but hardly contributes to the movement of carriers and functions as a high-resistance region.

As described above, the second regions 104b and 104c functioning as high-resistance regions are formed in the first region overlapping the gate electrode.
Is formed so as to be in contact with the region 104a and the edge of the active layer, whereby a structure in which current does not locally concentrate can be obtained. The second regions 104b and 104c also have a role as a heat sink for releasing Joule heat generated in a region of the first region 104a to be a channel formation region.

The second regions 104b, 104c
Is intentionally formed by photolithography or the like. FIG.
(A) shows the first region 10 overlapping the gate electrode 105;
An example is shown in which a total of four second regions (length X, width Y) 104b and 104c are provided in contact with the active layer 4a and the ends of the active layer. In the present invention, at least two of the second regions 104b and 104c may be provided in the second region on the drain region side. The carrier is the first
This length X is desirably set to a large value with respect to the channel length (L) so that the flow does not concentrate on the end of the active layer in contact with the region 104a. Similarly, it is desirable that the width Y is set to a large value with respect to the channel length (L).

Here, the channel length (L) and the channel width are defined with reference to FIG.

The length of the channel formation region sandwiched between the impurity regions is defined as a channel length (L). In FIG. 1D, the minimum distance (corresponding to the width Z of the gate electrode) connecting the pair of impurity regions 102 and 103 is defined as a channel length (L) (along this channel length). The direction is called the channel direction). However, when the impurity region is formed so as to overlap with the gate electrode, the channel length (L)
Does not correspond to the width Z of the gate electrode.

The width of the channel formation region (carrier moving path) in a direction perpendicular to the channel direction is defined as a channel width (W2). As described above, of the first region 104a having the width (W1), the region indicated by the distance Y (the region in contact with the second region) almost contributes to carrier movement even immediately below the gate electrode. Not
In this specification, it is not called a channel formation region (carrier movement path). Therefore, in FIG. 1, the width (W2) of the channel formation region is equal to the width (W2) of the first region 104a.
Does not match 1).

As described above, the TFT utilizing the present invention
Has a second region (high-resistance region) in contact with the first region overlapping with the gate electrode and in contact with the end of the active layer. Is characterized in that the second region is used as a heat sink that emits Joule heat generated by other portions.

As shown in FIG. 2, when the second regions 204b and 204c are provided by using the present invention and the edge of the active layer is tapered, a step formed in the gate insulating film is formed. Since the portion 200 can be made gentle, the influence on the element characteristics can be further reduced, which is very effective.

Further, as shown in FIG.
By arranging the first and second regions 4b and 304c at the ends of the active layer, the first region overlapping with the gate electrode 305 has the structure of an active layer which is not sandwiched between the source and drain regions 302 and 303. May be configured to further reduce the current (leakage current) flowing to the end of.

As shown in FIG. 4, a skewer-shaped intrinsic or substantially intrinsic region may be formed in the active layer.
With such a configuration, an intrinsic or substantially intrinsic region is used as a channel forming region that contributes to carrier movement, and another region can be used as a heat sink that emits generated Joule heat.

The present invention having the above structure will be described in more detail with reference to the following embodiments.

[0057]

[Embodiment 1] A manufacturing process of a TFT utilizing the present invention will be described with reference to FIGS. FIG. 5 illustrates a cross section viewed from two cuts. That is, FIGS. 5A to 5E are cuts obtained by cutting FIG. 1A along line BB ′, and FIGS. 5A to 5E are views in which FIG.
This is a cut cut at C '.

5A and 5A, reference numeral 101 denotes a substrate having an insulating surface, and a glass substrate provided with a base film, a silicon substrate, a glass ceramics substrate, or the like can be used. In the case of a quartz substrate, a base film may not be provided. If the maximum process temperature is within an allowable range, a plastic substrate can be used.

Next, an active layer 501 made of a crystalline silicon film is formed on the substrate 101. As the crystalline silicon film, either a single-crystal thin film or a polycrystalline thin film can be used. If a single crystal thin film is used, a known SIMOX or UN
An SOI substrate such as IBOND may be used. However, the active layer 501 is patterned in an island shape and has an end.

In addition, if a polycrystalline thin film is used, any process may be used as long as it is a polycrystalline thin film obtained by known means. Usually, the amorphous silicon film is crystallized by laser treatment or furnace annealing treatment. In addition to the silicon film, Si _x Ge _1-x (0 <X <
A compound semiconductor containing silicon as shown in 1) may be used.

Next, a 120-nm-thick gate insulating film 106 is formed to cover the active layer 501, and a gate electrode 105 is formed thereover using a metal film or a conductive silicon film.
In this state, the thickness of the gate insulating film is reduced at the end of the active layer. (FIGS. 5B and 5B)

After the gate electrode 105 is formed, the resist mask 5 intersects with the gate electrode 105 at right angles to the longitudinal direction of the gate electrode 105 (substantially parallel to the channel direction).
02 is formed. The resist mask 502 is patterned and arranged on an end portion of the active layer overlapping the gate electrode so as to cover a region of length X and width Y.

Then, in this state, an impurity element exhibiting N-type or P-type is added to the active layer 501 using the gate electrode 105 and the resist mask 502 as a mask to form a pair of impurity regions 102 and 103. It is to be noted that phosphorus or arsenic may be added for N-type, and boron may be added for P-type.

At this time, as shown in FIG. 5C, an intrinsic or substantially intrinsic region is formed in a portion where the resist mask 502 is intentionally provided with a width larger than the width Z of the gate electrode. In this embodiment, the width X of the gate electrode is 8 μm, and the length X = X with respect to the active layer (length 20 μm, width 200 μm).
Regions (intrinsic or substantially intrinsic regions) of 4 μm and width Y = 4 μm are formed at the ends (four corners) of the active layer overlapping the gate electrode. In the present embodiment, the length X and the width Y are smaller than the width Z of the gate electrode = 8 μm, but a sufficient effect can be obtained. Note that the length X and the width Y are preferably larger than the width Z of the gate electrode. On the other hand, in a portion where the resist mask 502 is not arranged as shown in FIG. 5C, an intrinsic or substantially intrinsic region is formed in a self-aligned manner using only the gate electrode 105 as a mask.

In the intrinsic or substantially intrinsic region shown in FIG. 5C, the first region 1 is located immediately below the gate electrode.
04a, the other area is the second area 104b,
104c. Then, the intrinsic or substantially intrinsic regions 104a, 104b, 1
04c substantially functions as a high-resistance region and also functions as a heat sink.

After a pair of impurity regions (source / drain regions) and an intrinsic or substantially intrinsic semiconductor region are formed in this manner, the impurities are activated to form the interlayer insulating film 107. (Fig. 5 (d), (d '))

Next, a source or drain electrode 108, 109 is formed by opening a contact hole, and finally hydrogenation is performed to complete a TFT having a structure as shown in FIGS. 5 (e) and 5 (e '). .

In order to simplify the description of the present invention, the TFT structure in this embodiment is a simple top gate type TFT.
FT structure was adopted.

The most important thing in this embodiment is to use the active layer having the structure as described with reference to FIG. 1. Other structures and structures are not limited to this embodiment. Not something.

Therefore, as long as the configuration of the active layer shown in the present invention is implemented, the present invention can be sufficiently applied to a TFT having another structure or a TFT manufactured by another manufacturing method. .

For example, even if the structure is such that a low-concentration impurity region (LDD region) or an offset region is provided between the source / drain region and the channel formation region, the present invention is implemented because the basic structure is not changed It does not prevent you from doing so.

[Embodiment 2] In this embodiment, an example different from the structure of the active layer shown in Embodiment 1 will be described with reference to FIG.

This embodiment is an example in which second regions 204b and 204c are provided in the active layer in the same manner as in the first embodiment, and the end of the active layer has a tapered shape.

A semiconductor thin film is formed on the insulating surface in the same manner as in the first embodiment, and when the semiconductor thin film is patterned or after patterning, the edge of the active layer is tapered by using a known etching technique or the like. The process may be performed. By performing the following steps in the same manner as in Example 1, the TFT shown in FIG. 2 is completed.

In FIG. 2, 201 is a substrate, 202,
203 is a source or drain region, 204a is a first region, 204b and 204c are second regions, 205 is a gate electrode, 206 is a gate insulating film, 207 is a first interlayer insulating film, 208 and 209 are source electrodes or It is a drain electrode.

With the structure of the active layer of the active layer shown in FIG. 2, the step portion 200 formed in the gate insulating film can be made gentle, and the influence on the element characteristics is further reduced.

[Embodiment 3] In this embodiment, an example different from the structure of the active layer shown in Embodiment 1 will be described with reference to FIG.

This embodiment is an example in which the area of the second region is larger than that of the first embodiment. As shown in FIG. 3, the end of the first region overlapping with the gate electrode 305 is sandwiched only by the second regions 304b and 304c, that is, the end of the first region overlapping with the gate electrode 305 is the source region. And an active layer not sandwiched between the drain regions 302 and 303. To make such a configuration,
The pattern of the resist mask 502 in the first embodiment may be appropriately changed by an operator.

With the configuration of the active layer shown in FIG. 3, the current flowing to the end of the first region can be further reduced as compared with the first embodiment.

In FIG. 3, 302 and 303 are source or drain regions, 304b and 304c are second regions, 305 is a gate electrode, and 308 and 309 are source or drain electrodes.

This embodiment can be freely combined with the structure of the second embodiment.

[Embodiment 4] In this embodiment, an example different from the structure of the active layer shown in Embodiment 1 will be described with reference to FIG.

In this embodiment, as shown in FIG.
This is an example in which a skewer-shaped intrinsic or substantially intrinsic region is formed in the active layer.

In FIG. 4, 402 and 403 are source or drain regions, 404b and 404c are second regions, 404d is a third region, 405 is a gate electrode,
08 and 409 are source electrodes or drain electrodes.

The third region 404d divides the channel forming region into a plurality, and has a configuration in which a plurality of TFTs are arranged substantially in parallel. The third region 404d is mainly used as a heat sink. The third area is
Intrinsic or substantially intrinsic region 404d.

In order to make the structure of the active layer shown in FIG. 4, the pattern of the resist mask 502 in the first embodiment is appropriately changed.
It may be changed by the implementer.

In the structure of the active layer shown in FIG. 4, a part of the intrinsic or substantially intrinsic region is used as a channel forming region contributing to carrier movement, and the other part emits generated Joule heat. Can be used as a heat sink.

This embodiment corresponds to the second or third embodiment.
Can be freely combined with the above configuration.

[Embodiment 5] In this embodiment, an example of a TFT manufactured by another manufacturing method different from that of Embodiment 1 will be described.

As long as the structure of the active layer shown in Examples 1 to 4 is implemented, the present invention is not limited to a TFT having another structure or a TFT manufactured by another manufacturing method. For example, Japanese Patent Application No. 11-45558 and Japanese Patent Application No. 11-657 filed by the present applicant.
The TFT structure described in Japanese Patent Application No. 37, Japanese Patent Application No. 11-104646 can also be used.

The structure of the present invention is characterized by a structure in which a high-resistance second region is provided in contact with the end of the active layer, and other structures may be determined by the practitioner as appropriate.

This embodiment can be freely combined with any of the structures of the first to fourth embodiments.

[Embodiment 6] Various semiconductor circuits can be formed by forming circuits using the TFTs having the structure of the present invention shown in Embodiments 1 to 5 of the present invention. And
By forming such a circuit integrally on the same substrate, an electro-optical device represented by an active matrix type LCD can be manufactured.

In the active matrix type LCD, various liquid crystals can be used in addition to the TN liquid crystal. For example, 1998, SID, "Characteristics and Driv
ing Scheme of Polymer-Stabilized Monostable FLCD E
xhibiting Fast Response Time and High Contrast Rat
io with Gray-Scale Capability "by H. Furue et al.
And 1997, SID DIGEST, 841, "A Full-Color Threshold
less Antiferroelectric LCD Exhibiting Wide Viewing
Angle with Fast Response Time "by T. Yoshidaet a
l., 1996, J. Mater. Chem. 6 (4), 671-673, "Thresh
oldless antiferroelectricity in liquid crystals an
d its application to displays "by S. Inui et al.
Alternatively, the liquid crystal disclosed in U.S. Pat. No. 5,594,569 can be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal. As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V (cell thickness is about 1 μm to 2 μm).
m) have also been found.

Here, FIG. 11 shows an example showing characteristics of light transmittance with respect to applied voltage of a thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optical response. The vertical axis of the graph shown in FIG. 11 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. The transmission axis of the polarizing plate on the incident side of the liquid crystal display device is set substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal, which substantially matches the rubbing direction of the liquid crystal display device. . The transmission axis of the polarizing plate on the output side is
The angle is set substantially at right angles (crossed Nicols) to the transmission axis of the polarizing plate on the incident side.

As shown in FIG. 11, it can be seen that when such a thresholdless antiferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible.

When such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having an analog driver, the power supply voltage of the image signal sampling circuit is, for example, about 5 V to 8 V. It becomes possible to suppress to. Therefore, the operating power supply voltage of the driver can be reduced, and low power consumption and high reliability of the liquid crystal display device can be realized.

Also, when such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having a digital driver, the output voltage of the D / A conversion circuit can be reduced. , The operating power supply voltage of the D / A conversion circuit, and the operating power supply voltage of the driver can be lowered. Therefore, low power consumption and high reliability of the liquid crystal display device can be realized.

As another electro-optical device, it is effective to use the present invention for an electro-optical device using a TFT as a switching element such as an image sensor.

Also, in the case of manufacturing a semiconductor circuit such as a high-frequency circuit or a processor circuit using a TFT having a high operation speed, it is effective to use the TFT having the configuration of the present invention.

When manufacturing the electro-optical device and the semiconductor circuit (these are collectively included in the semiconductor device), by using the TFT having the configuration of the present invention, the variation in the characteristics of the TFT due to the step portion can be reduced. In addition, since thermal deterioration of the entire circuit is reduced, a highly reliable (durable) semiconductor device can be realized.

[Embodiment 7] The present invention can be applied to an active matrix type EL (electroluminescence) display. An example is shown in FIG.

FIG. 6 is a circuit diagram of an active matrix type EL display. 81 represents a pixel circuit,
An X-direction drive circuit 82 and a Y-direction drive circuit 83
Is provided. Each pixel of the pixel circuit 81 includes a switch TFT 84, a capacitor 85, and a current control TF.
T86, an organic EL element 87, and a switching TFT 8
4, the X direction signal line 88a (or 88b) and the Y direction signal line 89a (or 89b, 89c) are connected. The power supply lines 90a and 90b are connected to the current control TFT 86.

In the active matrix type EL display of this embodiment, the TFT used for the X-direction drive circuit 82, the Y-direction drive circuit 83 or the current control TFT 86.
Is the p-channel type TF produced according to Examples 1 to 5.
It is formed by combining T and n-channel TFTs. The TFT of the switching TFT 84 is an n-channel type TF.
Formed with T.

The active matrix EL display of this embodiment may be combined with any of the structures of the first to fifth embodiments.

[Embodiment 8] A TFT formed by carrying out the present invention can be used for various electro-optical devices. That is, the present invention can be applied to all electronic devices in which these electro-optical devices are incorporated as display media.

Such electronic devices include a video camera, a digital camera, a head mounted display (goggle type display), a wearable display,
Examples include a car navigation system, a personal computer, and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). One example of them is shown in FIG.

FIG. 7A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display device 20.
03, a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.

FIG. 7B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 7C shows a mobile computer (mobile computer), which includes a main body 2201 and a camera section 2.
202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 and other signal control circuits.

FIG. 7D shows a goggle type display, which includes a main body 2301, a display device 2302, and an arm 230.
3 The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 7E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display device 2402, and a speaker unit 24.
03, a recording medium 2404, and operation switches 2405. This device uses a DVD (Di) as a recording medium.
It is possible to watch music, watch a movie, play a game, or use the Internet by using a CD (g. Versatile Disc) or a CD. The present invention can be applied to the display device 2402 and other signal control circuits.

FIG. 7F shows a digital camera, which comprises a main body 2501, a display device 2502, an eyepiece section 2503, operation switches 2504, and an image receiving section (not shown).
The present invention can be applied to the display device 2502 and other signal control circuits.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 7.

[Embodiment 9] The TFT formed by carrying out the present invention can be used for various electro-optical devices. That is, the present invention can be applied to all electronic devices in which these electro-optical devices are incorporated as display media.

As such an electronic device, there is a projector (rear type or front type). FIG. 8 shows an example of them.

FIG. 8A shows a front type projector, which comprises a display device 2601 and a screen 2602. The present invention can be applied to a display device and other signal control circuits.

FIG. 8B shows a rear type projector, which includes a main body 2701, a display device 2702, and a mirror 270.
3. It is composed of a screen 2704. The present invention can be applied to a display device and other signal control circuits.

It is to be noted that FIG. 8C corresponds to FIGS.
FIG. 3B is a diagram illustrating an example of the structure of the display devices 2601 and 2702 in FIG. Display devices 2601, 2702
Are the light source optical system 2801, the mirrors 2802, 2804-
2806, dichroic mirror 2803, prism 2
807, a liquid crystal display device 2808, a retardation plate 2809, and a projection optical system 2810. Projection optical system 2810
Is composed of an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. In addition, the practitioner may appropriately place an optical lens, a film having a polarizing function, a film for adjusting a phase difference,
An optical system such as an R film may be provided.

FIG. 8D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 8C.
In this embodiment, the light source optical system 2801 includes the reflector 2
811, light sources 2812, 2813, and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 8D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 6.

[0123]

According to the present invention, since a large current can be suppressed from flowing through the stepped portion, deterioration of device characteristics due to hot carriers at the stepped portion can be reduced.

Further, since current does not flow through the step,
As a result, the influence on the ON operation of the TFT is reduced. Therefore, even if deterioration due to gate BT stress or the like occurs at the stepped portion, there is no problem in the operation of the TFT.

[Brief description of the drawings]

FIG. 1 shows a top view and a cross-sectional view of the present invention.

FIG. 2 shows a top view and a cross-sectional view of the present invention.

FIG. 3 shows a top view and a cross-sectional view of the present invention.

FIG. 4 shows a top view and a cross-sectional view of the present invention.

FIG. 5 is a diagram showing a manufacturing process of a TFT.

FIG. 6 illustrates an EL display device.

FIG. 7 illustrates an example of an electronic device.

FIG. 8 illustrates an example of an electronic device.

FIG. 9 shows a top view and a cross-sectional view of a conventional TFT.

FIG. 10 is an observation photograph by a hot carrier analyzer.

FIG. 11 is a diagram showing characteristics of light transmittance with respect to applied voltage of a thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optical response.

Continued on the front page F term (reference) 2H092 JA25 JA34 KA22 NA24 QA07 QA13 QA14 RA01 RA05 5F110 AA08 AA13 AA23 AA30 BB01 CC02 DD01 DD02 DD03 DD05 EE02 EE09 EE29 GG01 GG02 GG12 GG13 GG22 GG14 GG24 GG14 GG28 NN03 PP01 PP03 QQ11 QQ17 QQ21

Claims (18)

[Claims] An TF comprising an active layer made of a thin film semiconductor formed in an island shape on an insulating surface, a gate insulating film covering the active layer, and a gate electrode formed on the gate insulating film.
A semiconductor device including T, wherein the active layer comprises: a first region overlapping the gate electrode;
A second region consisting of an intrinsic or substantially intrinsic region;
A third region to which an impurity element is added;
A region in contact with the first region and with an end of the active layer. 2. An TF comprising: an active layer made of a thin film semiconductor formed in an island shape on an insulating surface; a gate insulating film covering the active layer; and a gate electrode formed on the gate insulating film.
A semiconductor device including T, wherein the active layer comprises: a first region overlapping the gate electrode;
A second region to which a first impurity element is added; and a third region to which a second impurity element is added, wherein the second region is in contact with the first region, and A semiconductor device in contact with an end of the active layer. 3. The semiconductor device according to claim 2, wherein the first impurity element is an impurity element that imparts P-type or N-type to the second region. 4. The semiconductor device according to claim 2, wherein the second impurity element is an impurity element that imparts P-type or N-type to the third region. 5. The method according to claim 2, wherein the concentration of the first impurity element added to the second region is equal to or less than the third impurity element.
A semiconductor device having a concentration lower than the concentration of the second impurity element added to the region. 6. The semiconductor device according to claim 1, wherein the second region has a higher electric resistance than the third region. 7. The method according to claim 1, wherein a length X of a boundary between the first region and the second region is:
A semiconductor device having a width larger than the width Z of the gate electrode. 8. The semiconductor device according to claim 1, wherein a boundary between the first region and the third region does not contact an end of the active layer. 9. The semiconductor device according to claim 1, wherein the third region is a source region or a drain region. 10. An active layer made of a thin film semiconductor formed in an island shape on an insulating surface, a gate insulating film covering the active layer,
T comprising a gate electrode formed on the gate insulating film
A semiconductor device including FT, wherein the active layer includes a first region overlapping the gate electrode;
A second region that does not overlap with the gate electrode; a source region; and a drain region.
Semiconductor devices, four of which are arranged in a region in contact with the region. 11. An active layer made of a thin film semiconductor formed in an island shape on an insulating surface, a gate insulating film covering the active layer,
T comprising a gate electrode formed on the gate insulating film
A semiconductor device including FT, wherein the active layer includes a first region overlapping the gate electrode;
A second region that does not overlap with the gate electrode; a source region; and a drain region. The second region includes an end of the active layer and the first region on the drain region side. A semiconductor device, wherein the semiconductor device is arranged in a contact region. 12. The method according to claim 10, wherein
The semiconductor device according to claim 1, wherein the first region and the second region are intrinsic or substantially intrinsic regions. 13. The semiconductor device according to claim 10, wherein the second region has a higher electric resistance than the source region or the drain region. 14. An active layer made of a thin film semiconductor formed in an island shape on an insulating surface, a gate insulating film covering the active layer,
T comprising a gate electrode formed on the gate insulating film
A semiconductor device including an FT, wherein the active layer includes a source region, a drain region, and an intrinsic or substantially intrinsic region sandwiched between the source region and the drain region; A semiconductor device comprising a region having a different distance between a region and a drain region, wherein the distance between the source region and the drain region has a maximum value at an end of the active layer. 15. The semiconductor device according to claim 1, wherein an end of said active layer has a tapered shape. 16. A step of forming an active layer by patterning a semiconductor thin film, a step of forming a gate electrode above the active layer via an insulating film, and overlapping the gate electrode in the active layer. Forming an island-shaped mask pattern having a width Y and a length X above the end of the region; Adding a dopant element to the semiconductor device. 17. The length X of said island-shaped mask pattern in a longitudinal direction of said gate electrode.
Is larger than the width Z of the gate electrode. 18. The method according to claim 16, wherein
A method of manufacturing a semiconductor device, wherein a width Y of the island-shaped mask pattern in a direction perpendicular to a longitudinal direction of the gate electrode is larger than a width Z of the gate electrode.