JP2000348489A - Semiconductor memory device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make preventable an erroneous read operation caused by a precharging shortage generated at a time when the speed of a cycle used to perform a read operation in succession to a write operation is made high, the breakdown of data and the reliability of write data from being dropped, in a semiconductor memory which is constituted in such a way that a data bus and a data bus which are identical are used, that the data is changed into a complementary signal so as to be transmitted and that the write operation and the read operation are performed. SOLUTION: An auxiliary precharging circuit 10 is installed with respect to a memory cell array part 1, a precharging circuit 4, in which an I/O data bus T and an I/O data bus B as well as a data bus are charged to a VDD level, a write buffer 5, and a read buffer 6. During write operation, before an intrinsic precharging operation by the precharging circuit 4, the data bus T and the data bus B are supplementaly precharged in advance to a level of VDD-q×VTN which is lower than the precharging level VDD. Since the amount of an electric charge to be supplied to the data bus T and the data bus B is small in an intrinsic precharging operation by the precharging circuit 4, this semiconductor memory device can be charged to the VDD level in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for writing the same, and more particularly, to a semiconductor memory device having a structure in which data is read and written by using the same data bus and transmitting data as complementary signals. About.

[0002]

2. Description of the Related Art As a semiconductor memory of this type, for example, there is a dynamic random access memory (DRAM). FIG. 6 schematically shows an example of the configuration of a data transmission path at the time of reading and writing in a DRAM. Referring to FIG. 6, the semiconductor memory shown in FIG. 6 includes a memory cell array unit 1, a column switch unit 2, an I / O bus unit 3, a precharge circuit 4, a write buffer 5, and a read buffer 6.
It has.

The memory cell array section 1 has m × n memory cells C11, C1n,..., Cm1,
A memory cell array in which Cmn are arranged in m rows and n columns, and complementary digit line pairs (D1, $ D1), $, (Dn, $ Dn) ($) provided for each column of the memory cell array.
Is a substitute for the upper bar which means inversion. The same applies hereinafter), m word lines WL1,..., WLm for selecting one row from the memory cell array, and n sense amplifiers SA1,. , SA
n. The memory cell has a so-called one-transistor, one-capacitor configuration including one nMOS transistor and one capacitor, as shown in FIG. 6, and each word line WL1,. Connected to the gate electrode of each nMOS transistor in the row. Then, usually, the power supply voltage VDD is applied to the memory cell.
To perform level writing, select the word line WL
The high levels of 1,..., WLm are at least equal to the power supply voltage VDD + the threshold voltage VTN of the nMOS transistor.

[0004] The column switch section 2 is connected to each sense amplifier S
It is composed of 2n nMOS transistors provided so as to form a current path between complementary output points of A1,..., SAn and complementary data buses T and B of the I / O bus unit 3. Each nMOS transistor has a column switch control signal φc1,..., Φ applied to each column of the memory cell array.
cn is given to the gate electrode. During a read or write operation, one of the n sense amplifiers SA1,..., SAn is selected by setting any one of the column switch control signals φc1,. It is connected to the I / O bus unit 3 to transmit complementary data of the digit line pair to the data buses T and B or to transmit complementary data of the data buses T and B to the digit line pair.

The write buffer 5 is activated by a write control signal φw to take in write data DW to be written to a designated memory cell from the outside, and as a complementary signal to the data buses T and B of the I / O bus unit 3. Send out.

The read buffer 6 sends out complementary data read from the designated memory cell and transmitted from the digit line to the data buses T and B as read data DR.

The precharge circuit 4 is connected so as to form a current path between the power supply voltage supply line (voltage = VDD) 7 and the data bus T and between the power supply voltage supply line and the data bus B one by one. And two pMOS transistors. Each pMOS transistor is turned on while the precharge control signal φp commonly input to the gate electrode is at the low level, and charges (precharges) each data bus T, B to the level of the power supply voltage VDD.

Here, in the above-described semiconductor memory, the sense amplifiers SA1,.
A circuit as shown in FIG. That is, p
Combining two CMOS inverters each having a MOS transistor and an nMOS transistor connected in series so that their own input point and the other's output point are connected to each other;
The input points (nodes N1 and N2) of each inverter are connected to complementary digit lines D and .DELTA.D. Then, the source electrodes 8P commonly connected to the two pMOS transistors
, A sense amplifier activation signal SAP is input, and the source electrodes 8N of the two nMOS transistors connected in common are connected to each other.
Supplies a sense amplifier activation signal SAN. The two sense amplifier activation signals SAP and SAN are shown in FIG.
As shown in the upper waveform diagram, when the sense amplifier is activated at the time of the write or read operation, the signal SAP is set to the level of the power supply voltage VDD and the signal SAN is set to the ground level. To deactivate the other sense amplifiers, both signals SAP and SAN are set to the level of VDD / 2. Therefore, as shown in the lower waveform diagram of FIG. 7B, when the word line is at the low level and the sense amplifier is inactive, that is, the sense amplifier activation signal SA
When the levels of P and SAN are SAP = SAN = VDD / 2, the paired digit lines D and .DELTA.D are both VDD / 2.
Level. On the other hand, when the word line goes high, the sense amplifier activation signal SAP goes to the VDD level, and the other sense amplifier activation signal SAN
Are brought to the ground level, the complementary digit lines D,
A potential difference corresponding to the charge stored in the memory cell is generated during the period ▽ D, and the potential difference between the digit lines D and ▽ D between the complementary input points (connection nodes N1 and N2) of the sense amplifier is generated. A potential difference occurs. And the nodes N1, N
The potential difference of 2 is amplified by the sense amplifier, and one input point of the sense amplifier is driven to the VDD level and the other input point is driven to the ground level.

At this time, the column switch control signal φc
When 1,..., Φcn are at low level and the sense amplifier is disconnected from the data buses T and B, the complementary input points (nodes N1 and N2) of the sense amplifier are connected to the digit lines D and. The potential is applied as it is. On the other hand, when the column switch control signals φc1,..., Φcn are at a high level and the sense amplifier is connected to the data buses T and B, the potentials of the complementary input points N1 and N2 of the sense amplifier are The electric charge stored in the data buses T and B and the electric charge stored in each of the digit lines D and #D are redistributed according to the capacitance of the data buses T and B and the capacitance of the digit lines D and #D. To a potential determined by the

The above description of the sense amplifier relates to one sense amplifier. When a read or write operation is performed in the semiconductor memory shown in FIG. 1, first, one of m word lines is read out. And the level of the selected word line is set to VDD + VTN (VDD is the power supply voltage,
VTN is set to the threshold voltage of the nMOS transistor of the memory cell). Assuming that the word line WL1 in the first row is selected, the charge corresponding to the information stored in the n memory cells C11,..., C1n connected to the word line WL1 is previously set to VDD / 2. Digit line pairs (D1, $ D1), $, (Dn, $ Dn)
Is read out. Thereby, each digit line D1 and ▽
A small potential difference is generated between ΔDn and ΔDn between D1 and D1 in accordance with the amount of moved electric charge.

Next, sense amplifiers SA1,.
n is activated. The activated sense amplifiers have complementary input points N1 and N1 of the sense amplifier according to the charge amount and capacitance of the digit line and the charge amounts and capacitance of the data buses T and B.
The potential difference between the two is sensed and amplified, and one digit line and data bus are driven to VDD level and the other digit line and data bus are driven to ground level.

Based on the above operation of the sense amplifier, read and write operations in the DRAM shown in FIG. 6 will be described below. In the following, in order to facilitate understanding of the present invention, first, writing to the memory cell C11 is performed, and immediately thereafter, the memory cell C1 connected to the same word line is written.
A series of operations for reading the stored data of n will be described. Further, in this series of operations, initially, the storage data of the memory cell C11 is "0" (when the word line WL1 is selected, the digit line D1 is at a low level and the digit line # D1 is at a high level), The storage data of the memory cell C1n is also “0” (the same as the digit line D).
n is at a low level and the digit line #Dn is at a high level), and the stored data "0" of the memory cell C11 is rewritten to the write data DW = "1" (similarly, the digit line D1 is set to the VDD level, and D1 is switched to the ground level).

FIG. 8 is a timing chart showing a series of operations of the above-described writing from the memory cell C11 to reading from the memory cell C1n. Referring to FIGS. 6 and 8, first, word line WL1 in the first row is selected, and sense amplifiers SA1,..., SAn are activated as described above. Thereby, the memory cells C1 in the first row
1,..., C1n are charged according to the data stored in each digit line pair (D1,... D1),.
▽ Dn), amplified by each sense amplifier,
Each digit line is driven to a VDD level or a ground level, respectively. As a result, the digit line pair (D1,
▽ D1), the digit line D1 is at the ground level,
Digit line # D1 is driven to the VDD level. Similarly, in digit line pair (Dn, ▽ Dn), digit line Dn is at ground level and digit line 、 Dn is VD
Driven to D level.

Next, the write data D is stored in the memory cell C11.
At time T ₀ , the precharge control signal φp is switched from a low level to a high level in order to write W = “1”. Thereby, the two pMOs in the precharge circuit 4
Both the S transistors are switched from the on state to the off state, and the precharge that has been charging the data buses T and B to the power supply voltage VDD is stopped.

[0015] Then, inputs the write data DW = "1" in the write buffer 5, at time T ₁ by changing the write control signal φw from the low level to the high level to activate the write buffer 5. As a result, the write data DW = "1" is complemented, amplified and sent to the I / O bus unit 3, and the data bus T is driven to the VDD level and the bus B is driven to the ground level.

Thereafter, at time T ₂ , the column switch control signal φc 1 for the first column is changed from the low level to the high level, and the digit line pair (D 1 ▽ D 1) and the I / O
The two nMOS transistors between the bus unit 3 are made conductive, the digit line D1 is connected to the data bus T, and the digit line # D1 is connected to the data bus B. At this time, the data bus T is at the VDD level and the digit line D
Since 1 is the ground level, the level of the digit line D1 rises from the ground level. On the other hand, the data bus B is at the ground level and the digit line # D1 is at VDD.
Level, so that the level of digit line # D1 is VD
Decrease from D level. As a result, the level of digit line D1 and the level of digit line # D1 are inverted. Then, the potential difference between the digit lines D1 and # D1 whose levels have been inverted is sensed and amplified by the sense amplifier SA1, and
Digit line D1 is at VDD level and digit line ▽ D
1 is driven to ground level. As a result, data “1” is written to the memory cell C11. That is,
The write data D input from the outside
W = "1" is complemented, and the write data DW = "" is written to the memory cell array C11 via the data bus T, B → sense amplifier SA1 → digit line pair (D1, $ D1).
1 "is written.

[0017] After this, at time T ₃ to change the column switch control signal φc1 from the high level to the low level, and the nMOS transistor of the column switch unit 2 in an off state, the digit line pairs (D1, ▽ D1) and I / O Bus part 3
And disconnect. At the same time, the write control signal φw is changed from the high level to the low level, and the write buffer 5 is deactivated. Then, start the precharge on the data bus T, B precharge control signal φp at time T ₄ from the high level to switch to the low level, after the data bus T, B is charged to the VDD level, the memory cell C
The read operation for 1n is started.

In order to perform the read operation, first, the word line WL1 in the first row is selected and the sense amplifier S in the n-th column is selected based on an external read operation command.
An is activated to store the data stored in the memory cell C1n.
0 "is read out to the digit line pair (Dn, ▽ Dn),
The digit line Dn is driven to the ground level and the digit line 、 Dn is driven to the VDD level by the sense amplifier SAn.

[0019] Then, at time T ₅ by the precharge control signal φp is changed from the low level to the high level, the data bus T, and stops the pre-charge against B. At this time, the data buses T and B have already been sufficiently precharged and both have reached the VDD level. Next, at time T ₆
Next, the column switch control signal φcn for the n-th column is changed from the low level to the high level, and the two nMOS transistors in the column switch unit 2 are turned on, and the digit line pair (Dn, ▽ Dn) and the I / O Bus part 3
And connect. As a result, the digit line Dn already driven to the ground level is connected to the data bus T storing the charge at the VDD level, and the digit line ▽ Dn driven to the VDD level and the charge at the VDD level are connected. Is connected to the data bus B storing the data. As a result, while the data bus B keeps the VDD level, the data bus T falls from the VDD level, and a potential difference of the level of the bus T <the level of the bus B occurs between the data buses T and B. The potential difference between the data buses T and B is sensed and amplified by the sense amplifier SAn, and the data bus T is driven to the ground level and the data bus B is driven to VDD. As a result, the storage data "0" of the memory cell C1n is transmitted to the data buses T and B, and is output from the read buffer 6 as read data DR.

[0020] Then, at time T ₇ to change the column switch control signal φcn for the n-th column from the high level to the low level, the digit line pair (Dn, ▽ Dn) and was cut and a data bus 3, a time T ₈ , the precharge control signal φp is switched from the high level to the low level to precharge the data buses T and B to the VDD level, and waits for a subsequent read or write operation command.

[0021]

In recent years, there has been a strong demand for higher speeds of semiconductor memories. One way to satisfy the demand is to use all the input / output information as a system clock, such as in a synchronous DRAM. Speed up by adopting a different control method, such as controlling by synchronous operation, which is taken in by the latch of the chip's input / output unit, so-called synchronous operation, and operating multiple circuit blocks in parallel by pipeline method. There is a technical philosophy of doing. However, D by such a new idea
Even in the case of a RAM, it is possible to further increase the speed by shortening the write and read operation cycles. This is not limited to synchronous DRAM,
The same is true for M.

However, in the above-described write and read operations, if the operation cycle is shortened, the stored data is destroyed or erroneous data is read, the retention time of the written data is shortened, or the data cannot be written normally. In some cases, the reliability of the write operation may be degraded. The description is given below.

[0023] As described above, in a read operation immediately after the write operation to the memory cell in the semiconductor memory shown in FIG. 6, the time T from the time T ₄ in FIG. 8
After the write operation is completed as in the period up to ₅ , the data buses T and B are precharged, and both data buses are set to the same precharge level (in this case, the power supply voltage VD
The read operation must be started after sufficiently charging until D). In this case, the time from the start of the write operation (time T ₀ ) to the end of the read operation (time T ₈ ) is the column switch control signal φcn for the n-th column.
There will be substantially determined by the time T ₆ is switched from the low level to the high level.

Therefore, in FIG. 8, in order to shorten the operation cycle time from time T _{0 to} T ₈ , the timing at which the next read operation is started after the end of the write operation is advanced. That is, in the timing chart shown in FIG. 8, the digit line pair (Dn, .DELTA.Dn) in the n-th column
The timing for connecting the I / O bus unit 3 (the timing for switching the column switch control signal φcn from the low level to the high level), as shown in FIG. 9, it is assumed to accelerate at the time T ₁₆ from the original time T ₆ . The early was timing data bus T after the write operation is completed, a right after the precharge is started for B, and the time of the time T _16, the low level to the precharge control signal φp earlier it time T ₄ Since the switching has been performed, the data buses T and B are precharged. However, the precharge is not sufficient, and the data bus B remains at a low level close to the ground level. In this state, the I / O bus unit 3 and the digit line pair (Dn, ▽ Dn)
Are connected, the VDD level data bus T and the ground level digit line Dn are connected, and the low level data bus B close to the ground level is connected to the VDD level digit line ▽ Dn. Will be.
As a result, the data bus T drops from the VDD level and the digit line Dn rises from the ground level, and at the same time, the digit line ▽ Dn connects the data bus B to the VDD line completely.
The voltage drops significantly from the VDD level as compared with the case where the battery is charged to the D level. The level of the data bus B approaches the level of the data bus T rises from the level that has been charged by time T _16, digit lines Dn, ▽ Dn and between data bus T, the potential difference between B decreases.

The above data bus T, B, and between the digit lines Dn, ▽ magnitude of the potential difference between Dn, the data bus by the precharge by time T ₁₆ T, the charge amount is B and digit lines Dn,電荷 The amount of charge stored in Dn is equal to the capacitance of data buses T and B and the digit line D
The potential difference between the data buses T, B and the digit lines Dn,.
When the sensitivity is lower than the sensitivity of An, which of the data bus T and the digit line Dn and the data bus B and the digit line #Dn is driven to the VDD level and which is driven to the ground level cannot be uniquely determined. As a result, like the waveforms of the I / O buses T and B shown at the fifth stage in FIG. 9 and the waveforms of the read digits Dn and.
And the digit line Dn is driven to the VDD level, while the data bus B to be driven to the VDD level and the digit line #Dn are driven to the ground level, and the data stored in the memory cell C1n is "0". Regardless,
An erroneous read that reads this as the opposite "1" occurs, and the data "
A so-called data destruction of rewriting to 1 "occurs.

As described above, in the semiconductor memory shown in FIG. 6, if the timing of starting the read operation after the write operation is simply advanced, the stored data may be destroyed or an erroneous read may occur. Therefore, as another method for speeding up the write and read operations, in the timing chart shown in FIG. 8, when writing data “1” to the memory cell C11 first, the column switch control signal φc1 for the first column is set to high. During the level (time T _{2 to} T ₃
) Can be shortened. However, in this case, the digit line D1 may not be sufficiently driven to the VDD level and the digit line # D1 may not be sufficiently driven to the ground level. As described above, when the level of the data written in the memory cell C11 is not sufficiently VDD, the retention time of the written data is shortened.
In the worst case, the reliability of the write operation is impaired, for example, a so-called write-disable occurs in which the data to be rewritten becomes the same as before the write operation.

Therefore, according to the present invention, in a semiconductor memory having a configuration in which writing and reading are performed by using the same data bus and converting data into complementary signals for transmission, a cycle of performing a read operation after a write operation can be performed at a high speed. An object of the present invention is to prevent the destruction of stored data, the reading of erroneous data, or the deterioration of the reliability of write data, even if performed.

[0028]

According to the present invention, there is provided a semiconductor memory device comprising: a memory cell array in which memory cells for storing data are arranged in rows and columns; a word line for selecting a row of the memory cell array; Complementary digit lines provided for each column of the cell array and transmitting data stored in the memory cells or data to be stored in the memory cells, and the complementary digit lines provided for each column of the memory cell array. A sense amplifier that amplifies a potential difference between the two, a pair of complementary data buses for input / output connected to the digit line via a column switch, and activated in response to a write control signal and input from the outside. A write buffer for receiving write data to be written to the memory cell and transmitting the write data as a complementary signal to the data bus; A first precharge circuit for charging the tabus to a predetermined first potential, and a second precharge circuit for charging the data bus to a second potential lower than the first potential during a write operation. At least.

[0029]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a configuration of a data transmission path at the time of reading and writing in the semiconductor memory according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor memory shown in FIG. 1 is different from the conventional semiconductor memory shown in FIG.
It is to have. The auxiliary precharge circuit includes: a charging circuit 12B provided between the power supply voltage supply line 7 and the data bus B; a charging circuit 12T provided between the power supply voltage supply line 7 and the data bus T; And a charge control signal generation circuit 11.

Auxiliary precharge control signal generation circuit 11
Captures the write control signal φw and outputs the write control signal φ
An auxiliary precharge control signal φwd having a high level width of td2, which rises from a low level to a high level with a delay of a predetermined time td1 from w, is generated (see the uppermost waveform and the second waveform in FIG. 4). FIG. 2 shows a circuit diagram of an example of the auxiliary precharge control signal generation circuit 11. Referring to FIG. 2, the auxiliary precharge control signal generating circuit receives a write control signal φw and delays it by a time td1, and an output signal of the first delay circuit 13 by a time td2. Second delay circuit 14 for adding delay and inverting
And an inverter 15 that generates an AND logic signal of the output signal of the first delay circuit 13 and the output signal of the inverter 15 and outputs the AND logic signal as the auxiliary precharge control signal φwd.
And a D gate 16.

The charging circuit 12B has k nMOS transistors QB1 to QBk inserted in series between the power supply voltage supply line 7 and the data bus B, and is connected in parallel between the drain and source of each nMOS transistor. It consists of k-1 fuses FB2 to FBk. Note that only the transistor QB1 closest to the data bus B is not provided with a fuse. Even when all fuses are connected,
This is because at least one nMOS transistor is inserted between the power supply voltage supply line 7 and the data bus B. Similarly to the charging circuit 12B, the charging circuit 12T includes k serially connected nMOS transistors QT1 to QTk and k-1 fuses FT2 to FT.
k. Each nMOS in the charging circuits 12B and 12T
The output signal φwd of the auxiliary precharge control signal generation circuit 11 is commonly input to the gate electrode of the transistor.

The write operation and the subsequent read operation of the semiconductor memory according to this embodiment will be described below with reference to FIG.
This will be described with reference to the timing chart shown in FIG. FIG.
7 shows a timing chart when an operation of reading storage data of the memory cell C1n in the same row is performed after writing the write data DW = "1" to the memory cell C11.
The initial storage data of the memory cells C11 and C1n is
It is assumed that both are "0". Referring to FIGS. 1 and 4, first, a word line WL1 in the first row is selected, and the sense amplifier SA is set in the same manner as in the conventional semiconductor memory.
Activate 1,..., SAn to drive digit line D1 to ground level and digit line # D1 to VDD level.

Next, at time T ₀ , the precharge control signal φ
The signal p is switched from the low level to the high level, and the precharge operation for the data buses T and B is stopped.

[0034] Then, inputs the write data DW = "1" in the write buffer 5, a write control signal φw to time T ₁ is changed from the low level to the high level, the write by activating the write buffer 5 data DW = "1"
To drive the data bus T to the VDD level and the data bus B to the ground level.

Then, at time T ₂ , the column switch control signal φc 1 for the first column is changed from low level to high level to connect the digit line D 1 to the data bus T, and to connect the digit line ΔD 1 and the data bus B to each other. Connecting.
As a result, the digit line D1 is driven to the VDD level, the digit line # D1 is driven to the ground level, and the write data DW = "1" is written to the memory cell C11. The writing operation so far is the same as the writing operation in the conventional semiconductor memory.

[0036] Then, with a delay of the rise from the time td1 of the write control signal φw at time T _1, the time T ₂₉ is an auxiliary pre-charge control signal φwd rises from the low level to the high level. Thereby, nMOS transistors QB1-QBk, QT in auxiliary precharge circuit 10
1 to QTk change from the OFF state to the ON state, and electric charges are supplied from the power supply voltage supply line 7 to the data buses T and B through the charging circuits 12T and 12B (auxiliary precharge). As shown by the waveforms of the I / O buses T and B, the potential of the data bus B starts to rise toward the VDD level. The auxiliary precharge for the data buses T and B continues for a time td2 when the auxiliary precharge control signal φwd is at the high level. Here, the delay time td1 of the first delay circuit 13 is such that the digit line D1 is sufficiently amplified to the VDD level and the digit line # D1 is sufficiently amplified to the ground level, and the write data DW = "1" is stored in the memory cell C1.
Surely written auxiliary precharge time t ₂₉ after which is adjusted to begin to 1. The auxiliary precharge level in this embodiment is VDD-q × VTN (q
Is the number of nMOS transistors inserted in series between the power supply voltage supply line 7 and the data buses T and B after the fuse is cut off. Therefore, the difference between the auxiliary precharge level and the power supply voltage VDD ( = Q × VTN) is adjusted so that the number of fuses to be cut does not fall below the sensitivity of the sense amplifier. This is for preventing data destruction from occurring in the memory cell C11.

[0037] Then, at time T ₃ the column switch control signal φc1 from the high level is changed to the low level, the digit line pair (D1, ▽ D1) to cut the the I / O bus unit 3. At the same time, the write control signal φw is changed from the high level to the low level, and the write buffer 5 is deactivated.

[0038] Then, to start the precharge on the data bus T, B at time T ₄ the precharge control signal φp from the high level to switch to the low level. In that case,
The data bus B is already supplied with VDD-
Since the battery has been charged up to q × VTN, the precharge after time T ₄ only needs to charge the charge corresponding to the potential difference q × VTN. Therefore, it is possible to charge to the VDD level in a shorter time than in the conventional semiconductor memory shown in FIG. 6, at time T ₁₆ the precharge control signal φp from low when stopping the precharge switch to the high level at the same time, When the column switch control signal φcn for the n-th column is switched from low level to high level to connect the digit line pair (Dn, ▽ Dn) to the data buses T and B and read the data stored in the memory cell C1n, Both data buses T and B have sufficiently reached the VDD level. Therefore, erroneous reading or data destruction due to insufficient precharge in the memory cell C1n does not occur.

[0039] Then, at time T ₁₇ to change the column switch control signal φcn from the high level to the low level, the digit line pair (Dn, ▽ Dn) and was cut and a data bus 3, the precharge control at time T ₁₈ The signal φp is switched from the high level to the low level, and the data buses T and B are set at V level.
It is precharged to the DD level and waits for a subsequent read or write command.

In the present embodiment, the memory cell C1
Data bus T to time T ₂₉ in write operation to 1, B
To perform auxiliary precharge for the data bus T in the original precharge starting at time T _4, reducing the amount of charge to be supplied to B, thereby charging the data bus T, B to VDD level in a short time as compared with conventional ing. Thus, the column switch control signal φcn never precharge lack read or data destruction erroneous cause occurs even earlier timing T ₁₆ to switch to the high level from the low level,
Write and read operations can be sped up. In the present embodiment, at the same time the auxiliary precharged to the precharge stop time T ₁₆ is to stop. The setting is performed by adjusting the delay time td2 of the second delay circuit 14 in the auxiliary precharge control signal generation circuit 11.

Next, a second embodiment of the present invention will be described. This embodiment is different from the first embodiment in the auxiliary precharge control signal φwd. FIG. 5 shows a timing chart of the write and read operations in the present embodiment. In the present embodiment, the second
As shown in the waveform at the second stage, the auxiliary precharge control signal φ
As wd, a delay signal of the write control signal φw is used.
The auxiliary precharge control signal generation circuit 11 according to the present embodiment includes only a first delay circuit 13, as shown in FIG. The delay time is set to td1 as in the first embodiment. Auxiliary precharge control signal φw
The high-level width W of d is the same as the high-level width of the write control signal.

[0042] In this embodiment, the column switch control signal φcn switches from the low level to the high level at time T _16, and the data bus T precharge control signal φp is changed from the low level to the high level, the precharge for the B Even after stopping, the auxiliary precharge continues. Thus, the I / O bus T until time T ₁₆ through T _30, as shown in the waveform of B, until the auxiliary precharge time T ₃₀ is completed, the I / O bus T is an auxiliary pre-charge level It drops only to VDD-q × VTN,
After time T ₃₀ to a data bus T, the supply of the auxiliary pre-charge the charge on B is stopped, and a full swing to ground level. However, even in this case, since the potential difference q × VTN between the power supply voltage VDD and the auxiliary precharge level VDD−q × VTN is set to be larger than the sensitivity of the sense amplifier, erroneous reading or data destruction may occur in the memory cell C1n. There is no.

[0043] In the first embodiment, since the auxiliary precharging and original precharge are simultaneously stopped, the column switch control signal φcn at time T ₁₆ is changed from the low level to the high level, the data bus T is Immediately swing to the ground level. Therefore, narrowing the high-level width of the column switch control signal Faicn (by advancing the timing T ₁₇₎ is a read operation speed can be increased by stable, is complicated configuration of the generation circuit of the auxiliary pre-charge control signal φwd Become. On the other hand, the present embodiment has an advantage that the auxiliary precharge control signal generation circuit 10 can be simplified.

In the first and second embodiments, to facilitate understanding, the write and read operations are continuously performed on the memory cells C11 and C1n belonging to the same word line WL1. In this case, the auxiliary precharge level VDD-qVTN is set to the data line T
Has been described so that the difference (= VTN) between the level (= VDD) and the level of the data line B (= auxiliary precharge level) does not fall below the sensitivity of the sense amplifier. Precharge level is 1st, 2nd
It is desirable that the level be lower than that in the embodiment described above in order to ensure the reliability of the written data. That is, in a semiconductor memory, a write operation is performed on a certain memory cell and then a read is performed on another memory cell belonging to the same word line as in the first and second embodiments. In addition to the operation sequence in which a word line does not need to be switched after writing to a memory cell, a write operation is performed on a certain memory cell, and then a write operation is performed on a memory cell belonging to another word line. Alternatively, there is an operation sequence of performing a read. In the case of this operation sequence, for example, immediately after writing to the memory cell C11, it is necessary to switch the word line from WL1 to another word line WLi (i is a suffix representing a word line other than the first row). The word line WL1 is closed (deselected) immediately after writing to the memory cell C11. At this time, if the auxiliary precharge level is set to the same level as in the first and second embodiments, the restoration (the levels of the data buses T and B immediately before the word line is closed) becomes insufficient, and There is a possibility that writing of write data to the cell C11 cannot be guaranteed. Therefore, generally, the level of the auxiliary precharge is set at the time T
Third, the memory cell is connected between the time when the column switch control signal φc1 for the first column goes low and the data buses T and B and the digit line pair (D1,... D1) are disconnected and before the word line WL1 is closed. It is preferable that the data written in C11 be set to a level at which the sense amplifier can be driven to the VDD level or the ground level. As described above, the auxiliary precharge level needs to be adjusted to an appropriate level, but the level can be adjusted by adjusting the number of blown fuses in the charging circuits 12B and 12T in the auxiliary precharge circuit.

In the first and second embodiments, a DRAM having a configuration in which the data buses T and B are precharged to the level of the power supply voltage VDD has been described as an example. You don't have to. As long as the two data buses T and B can be at the same level, VDD / 2 may be used, or another level may be used.

[0046]

As described above, according to the present invention, the auxiliary precharge to the predetermined level is performed on the I / O bus portion during the write operation on the memory cell,
The charge amount to be supplied to the data bus in the original precharge is reduced.

As a result, according to the present invention, the data bus can be charged to the precharge level in a shorter time than in the prior art. Therefore, during the read operation following the write operation, erroneous data due to insufficient precharge can be obtained. The timing for connecting the digit line pair to the I / O bus portion can be advanced without destruction of reading or storage data, and the writing and reading operations can be speeded up. In order to speed up the write and read operations, the digit line during write operation and I / O
Since it is not necessary to reduce the time for connecting to the O bus unit, the level of the write data does not decrease and the reliability of the write data does not decrease.

The present invention has a particularly remarkable effect when applied to a semiconductor memory such as a synchronized DRAM which requires a high speed.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a configuration of a data transmission path at the time of reading and writing in a semiconductor memory according to a first embodiment.

FIG. 2 is a circuit diagram illustrating an example of an auxiliary precharge control signal generation circuit according to the first embodiment;

FIG. 3 is a circuit diagram illustrating an example of an auxiliary precharge control signal generation circuit according to a second embodiment;

FIG. 4 is a diagram showing a timing chart at the time of write and read operations in the first embodiment.

FIG. 5 is a diagram showing a timing chart at the time of write and read operations in the second embodiment.

FIG. 6 is a diagram schematically showing a configuration of a data transmission path at the time of reading and writing in a conventional semiconductor memory.

FIG. 7 is a diagram illustrating a circuit diagram of an example of a sense amplifier, and a diagram illustrating signal waveforms during operation of the sense amplifier.

FIG. 8 is a diagram showing a timing chart at the time of normal write and read operations in a conventional semiconductor memory.

FIG. 9 is a diagram showing a timing chart at the time of write and read operations in a conventional semiconductor memory when the read operation is accelerated.

[Explanation of symbols]

 Reference Signs List 1 memory cell array section 2 column switch section 3 I / O bus section 4 precharge circuit 5 write buffer 6 read buffer 7 power supply voltage supply line 8N, 8P source electrode 9 10 auxiliary precharge circuit 11 auxiliary precharge control signal generation circuit 12B, 12T charging circuit 13,14 delay circuit 15 inverter 16 AND gate

Claims (11)

[Claims] A memory cell array in which memory cells for storing data are arranged in rows and columns; a word line for selecting a row of the memory cell array; and a memory cell provided for each column of the memory cell array. A complementary digit line for transmitting stored data or data to be stored in a memory cell; a sense amplifier provided for each column of the memory cell array to amplify a potential difference between the complementary digit line; and the digit. A pair of complementary data buses for input and output, connected to the line via a column switch, and fetching write data to be written to the memory cell, which is activated in response to a write control signal and input from the outside; A write buffer for transmitting a signal complementary to the data bus, and a write buffer for charging the data bus to a predetermined first potential. 1. A semiconductor memory device comprising: at least one precharge circuit; and a second precharge circuit that charges the data bus to a second potential lower than the first potential during a write operation. 2. The semiconductor device according to claim 2, wherein said second precharge circuit includes at least one or more MOS field effect transistors connected in series between said first potential supply line and each of said data buses. 2. The semiconductor memory device according to claim 1, further comprising control signal generation means for generating a binary sub-precharge control signal for controlling a conduction state of said MOS field-effect transistor from a write control signal. . 3. The semiconductor memory according to claim 1, wherein the second precharge circuit is capable of adjusting the second potential in a process of manufacturing the semiconductor memory device. apparatus. 4. Each of the MOS field-effect transistors constituting the second precharge circuit has a fuse cut or left in parallel according to a potential difference between the first potential and the second potential. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is provided. 5. A first control signal generating means for receiving the write control signal, outputting the write control signal after delaying the write control signal by a predetermined time.
A delay means, a second delay means for receiving an output signal of the first delay means, applying a predetermined delay thereto, inverting the output signal, and outputting the inverted signal, and an AND of the first delay means and the second delay means
3. The semiconductor memory device according to claim 2, further comprising: an AND gate that generates a logic signal and outputs the signal as the sub-precharge signal. 6. The semiconductor memory device according to claim 2, wherein said control signal generating means comprises a delay means for inputting said write control signal, adding a delay of a predetermined time, and outputting it. 7. The semiconductor memory device according to claim 1, wherein the first potential is a potential of a power supply voltage of the semiconductor memory device. 8. A first precharge step of previously charging a pair of input / output data buses to a predetermined first potential, and a write data to be written to a memory cell after charging on the data bus is stopped. And a second precharging step of charging the data bus to the first potential by writing the memory cell by sending the data bus to the data bus. During the period of writing the write data to the memory cells, prior to the second precharge step, an auxiliary precharge step of previously charging the data bus to a second potential lower than the first potential is performed. A method for driving a semiconductor memory device, comprising: 9. The semiconductor memory device according to claim 8, wherein the charging of the data bus in the auxiliary precharge step is terminated at the same time as the completion of the charging of the data bus in the second precharge step. Drive method. 10. The semiconductor according to claim 8, wherein the charging of the data bus in the auxiliary precharging step is continued until a predetermined time after the completion of the charging of the data bus in the second precharging step. A method for driving a storage device. 11. The method for driving a semiconductor device according to claim 1, wherein a first step of charging said data bus to said first potential by said first precharge circuit; and said data bus. After the charging of the data bus is stopped, the write control signal activates the write buffer and transmits the write data to the data bus as complementary data. A third step of connecting the digit line and the digit line, transmitting the write data to the digit line and writing the write data to a predetermined memory cell, and opening the column switch to release the digit line and the data. A fourth step of separating the bus from the bus and deactivating the write buffer by the write control signal; A fifth step of charging the data bus to the first potential by a path, wherein the second precharge is performed in parallel with the writing to the memory cell in the third step. A method of charging the data bus to the second potential by a circuit.