JP2000341586A - Signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a signal generator for generating a pairing wipe pattern and superior in flexibility. SOLUTION: A lamp function generation unit includes 1st an 2nd ramp function signal generators 201 and 202, and they respectively generate ramp function signals R=Ah+Bv+C and R'=A'h+B'v+C'. Here, (v) is defined as a scan line number, and (h) is defined as a pixel position on the scan line. A, B and C (A', B' and C') are coefficients to which positive/negative values can be set arbitrarily by a state machine decoder 206 controlled by a controller 207. Even though specific relations do not have to exist between two generated lamp functions, generally one is frequently inverted or the like, by the other. Outputs of the both function signal generators are alternately selected by a selector 205 and are also subjected to limit processing by a limiter 208. A combiner 209 may be connected with the outputs of a 2nd unit with similar configurations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a signal generator. This signal generator is suitable for generating a "solid function signal" for use in a video mixer generator of a vision mixer.

[0002] A solid function signal is an electrical signal representing a three-dimensional surface of a desired shape. The solid function signal is composed of at least one ramp function signal, and is usually composed of a combination of two or more ramp function signals. Each lamp function signal constituting the solid function signal may be subjected to a modification process in advance. The solid function signal may take the form of a signal defined in a polar coordinate system, in which case the solid function signal is a signal representing a curved surface.

[0003]

2. Description of the Related Art A description will now be given with reference to FIGS.

FIG. 1 is a diagram showing a screen switching process by a well-known simple wipe executed to switch between an image of a video source X and an image of a video source Y on a screen.

As the screen switching process by the wipe proceeds as shown by the arrow W, the image portion of the video source X is replaced with the image portion of the video source Y (inversely, the video source Y Can be replaced with the image part of the video source X). The screen switching process by the wipe is achieved by mixing the video signal of the video source X and the video signal of the video source Y according to the following equation. KX + (1−K) Y where K
Is a keying signal. The keying signal K is derived from the “solid function signal”. This will be described below with reference to FIGS. The solid function signal is a function signal having a value corresponding to the hv coordinate of the screen, where v is a scan line number and h is a pixel position on the scan line.

FIG. 2 shows a known concrete example of the "solid function signal". The solid function signal shown in FIG. 2 is composed of only one ramp function signal. FIG.
As shown in the figure, the clip level CP is set. The clip level CP defines a plane that extends over the entire field or frame, and is referred to herein as a clip plane. This clip plane will be described in more detail later with reference to FIG. The method of deriving the keying signal K from the solid function signal is well known, ie
The signal obtained by amplifying the solid function signal with a high gain may be subjected to limit processing as shown in FIG. 2B. As a result, the keying signal becomes a two-level signal that takes one of the levels “0” and “1”. This keying signal transitions from one level to the other at the point where the solid function signal crosses the clip plane CP. By providing an offset to the solid function signal, its traversing position can be changed, thereby generating a wipe.

FIG. 3 shows a block diagram of a vision mixer wipe generator, which includes a solid function signal generator,
It includes a clip element, a gain element, a limiter, and a mixer. The mixer mixes the video source X and the video source Y in accordance with the keying signal K.

The solid function signal generator generates a solid function signal, and the generated solid function signal may be, for example, a ramp function signal as shown in FIG. 2A. The clip element changes the position of the line of intersection of the ramp function signal with the clip plane CP by giving an offset to the ramp function signal, as shown in FIGS. A gain is applied to the gain function to the ramp function signal to which the offset has been applied, and a limiter is applied to a signal obtained by the gain processing to obtain a keying signal K. When the magnitude of the applied gain is changed, as shown in FIG. 2B, the gradient of the portion of the keying signal K that transitions between the upper limit and the lower limit can be changed.

[0009] The mixer mixes the video source X and the video source Y according to the following equation. KX + (1-K) Y According to this mixing method, when K = 1, the output signal is the video source X itself, and K = 0.
In this case, the output signal is the video source Y itself. Also, the gain given to the solid function signal is “1”.
When the offset amount of the clip plane is “0”, the solid function signal and the keying signal are the same signal.

[0010]

It is desirable to generate a new solid function signal that can generate a variety of new wipe patterns. Also,
"Pairing" to one of the known wipe patterns
There is a wipe pattern called. This wipe
The effect of using the pattern is that both the portion on the screen where the first image is displayed and the portion where the second image is displayed are striped, and the striped portion is a blank portion between the striped portions. However, the phases of one image and the other image are opposite to each other. However, the conventional configuration for generating this pairing wipe pattern was inflexible.

[0011]

According to the present invention, there is provided a signal generator, the signal generator comprising:
The first ramp function signal generator includes a pair of ramp function signal generators including a ramp function signal generator and a second ramp function signal generator, and the first ramp function signal generator includes a plurality of predetermined scanning lines vr1 (vr1 = 0 to vr1) on a screen.
m), a predetermined plurality of pixels hr1 (hr1 = 0 to n) present on each of the scanning lines of the scanning line set consisting of m)
For each of its pixels in the pixel set consisting of
Signal value Rr1 of first ramp function signal which is a video signal
Is generated according to the following equation: Rr1 = A1 · hr1 + B1 · vr1 + C1, where A1, B1, and C1 are coefficients that can take positive and negative values, and the second ramp function signal generator generates Of a scan line set consisting of a plurality of predetermined scan lines vr2 (vr2 = 0 to m), a pixel set consisting of a plurality of predetermined pixels hr2 (hr2 = 0 to n) present on each of the scan lines, For each pixel, the signal value Rr2 of the second ramp function signal, which is a video signal, is calculated as Rr2 = A2 · h
r2 + B2 · vr2 + C2, where A2, B2, and C2 are coefficients that can each take a positive or negative value.
A signal generator comprising a selection unit for alternately selecting the first ramp function signal and the second ramp function signal.

The term "screen" used in the above description and in the claims is a term meaning both fields and frames of an image signal.

[0013] The selection means alternately selects the first ramp function signal and the second ramp function signal on the screen. A vertical stripe can be selected, and a horizontal stripe can also be selected. To select a vertical stripe portion, the selection means alternately selects the first ramp function signal and the second ramp function signal along each of the scanning lines on the screen. In addition, in order to select a stripe portion of a horizontal stripe, when p is an integer of 2 or more, the selection unit includes, in a scanning line set including p consecutive scanning lines of the screen, The first ramp function signal and the second ramp function signal are alternately selected.

One embodiment of a signal generator for generating two solid function signals constituting a paired solid function signal includes a plurality of signal generators according to the present invention, and a plurality of the first ramp functions. A signal generator for generating a first solid function signal by combining a plurality of ramp function signals respectively generated by the signal generator;
A signal generator, comprising: a second combination means for generating a second solid function signal by combining a plurality of ramp function signals respectively generated by the ramp function signal generator.

Therefore, according to the present invention, it is possible to generate a pair-solid function signal which can take any form of vertical stripes and horizontal stripes. There is no need for a specific relationship to exist between the two solid function signals that make up this paired solid function signal, both in terms of their shape and their position in the screen. The two solid function signals are a solid function signal that can be generated by combining a plurality of first ramp function signals and a solid function signal that can be generated by combining a plurality of second ramp function signals. It is only necessary to be a function, and there are no other restrictions, so that a wide variety of paired solid function signals can be generated according to the present invention.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in more detail with reference to the accompanying drawings in accordance with preferred embodiments. The ramp function signal generator shown in FIG. 5 generates a ramp function signal according to the following equation.
R = Ah + Bv + C where A, B and C
Is a coefficient whose value can be arbitrarily set, v is a scanning line number, and h is a pixel position on the scanning line. The ramp function R defined by this equation is, for example, a three-dimensional ramp function R existing in a three-dimensional space as shown in FIG. For each pixel position h on each scan line v, the signal value of the ramp function R corresponding to that pixel position is calculated based on the values of the coefficients A, B, and C. The calculated value is represented by a positive / negative value (a numerical value that can be both a positive number and a negative number), and is particularly preferably represented in the form of a two's complement. As described in further detail below, the range of h is 0-n and the range of v is 0-m.

In which one of a plurality of scanning lines v in one field or frame, the ramp function signal is generated, and in which one of the plurality of pixels h on the plurality of scanning lines v, the ramp function is generated. Regarding whether to generate a signal, a specific plurality of scanning lines v and a specific plurality of pixels h can be selected.
In that case, the plurality of scanning lines v shall be included in a scanning line set consisting of a plurality of scanning lines that are continuously arranged, that is, closely arranged without any space between them. A plurality of pixels are also included in a pixel set consisting of a plurality of pixels arranged continuously, that is, closely arranged without any gap. It is possible to generate a ramp function signal in the field or to generate a ramp function signal in the frame. However, in the following description, for simplicity,
A case where a ramp function signal is generated in a frame of the progressive scanning method will be described.

The range of the signal value R of the ramp function signal is from the negative limit value -M to 0 through the positive limit value + M. The dynamic range DR of the ramp function signal is set such that the area where the signal value R of the ramp function signal is generated is a sufficiently large area than the active frame area of the video signal.

FIG. 4 shows a TV frame of the progressive scanning system, and the scanning lines v constituting the whole of the frame are provided with the first to second,... Until the turn,
They are numbered sequentially. Further, pixel positions h constituting the entire length of each scanning line are sequentially numbered from the 0th to the nth. In the ramp function R of the specific example shown in FIG. 4, the offset amount from the reference plane RP located at the height of −M is C.

In brief, the clip plane shown by the plane CP in FIG. 4 intersects the ramp function R at the intersection line L as shown. The position where the ramp function R intersects the clip plane CP changes according to the offset amount C. The slope of the ramp function R along the scan line v = 0 is equal to the value of the coefficient A. The slope of the ramp function R along the pixel position h = 0 on all scan lines v is equal to the value of the coefficient B. The transition region of the keying signal K extends along the straight line L. In an area where the level of the keying signal K exceeds the level of the clip plane CP, an image of one of the video sources Y is displayed on a screen portion corresponding to the area, and the level of the keying signal K is equal to the level of the clip plane CP. In an area at the same height or lower, an image of the other video source X is displayed on a screen portion corresponding to the area. This is as described above with reference to FIGS. 1 and 3.

The ramp function signal generator shown in FIG. 5 includes a register R1 (INCA) and a register R2 (INC).
CB) and a register R3 (Start C). These registers are coefficient registers for storing respective values selected as the values of the coefficients A, B, and C. The coefficient registers R1, R2, and R3 are connected to an increment selector SEL1, which selectively selects one of the coefficient registers R1 to R3 and selects a register REG1.
To the adder 1 via. Register REG1 contains a clock signal HFCK_S that defines the pixel rate.
Clocked by YS. Two feedback registers FB1 and FB2 are connected to another selector, a feedback selector SEL2. The feedback selector SEL2 selectively couples any one of the feedback register FB1, the feedback register FB2, and the 0 input to the adder 1. The output of adder 1 is output register R
The output register REG2 is connected to the clock signal HFCK_S similarly to the register REG1.
Clocked by YS. The registers R1, R2, R3, FB1, FB2 and the selectors SEL1, SEL2 listed above correspond to the real-time controller 2
Is controlled by The real-time controller 2 outputs a signal pulse IP_H indicating the starting point of each scanning line.
And a signal pulse IP_V indicating the start point of the frame;
And a control signal IncSel for controlling the selector SEL1.
And a control signal Acc for controlling the selector SEL2.
Sel. The controller 2 also controls a loading operation for loading the respective values of the coefficients A, B, and C into the registers R1 to R3.

Prior to the start of each frame, the computer 6 generates respective values of the coefficients A, B, and C and the control data corresponding to the frame, and converts the generated values of the coefficients and the control data in real time.・ Supply to the controller 2. The real-time controller 2 supplies the values of these coefficients to the registers R1, R2, R3. The computer 6 functions as an interface for connecting between a control operation performed by an operator and the real-time controller 2. The computer 6 generates respective values of the coefficients A, B, and C according to the set value of the control operation performed by the operator.

The operation of the ramp function signal generator described above will now be described with reference to FIG. The basic operating principle is that the adder 1 stores one of the integrated value stored in the feedback register FB1 and the integrated value stored in the feedback register FB2 in each of the registers R1 to R3. Is added as an increment value, and the total value obtained is added to the two feedback values.
By feeding back to one or both of the registers FB1 and FB2, the increment is repeatedly performed.

For the sake of simplicity, the procedure for generating the signal value R of the ramp function signal will now be described with reference to FIG.
Is assumed to start from the pixel position h = 0 on the scanning line v = 0. Also, the respective values of the coefficients A, B, and C are represented by the same characters A, B, and C. Therefore, the offset amount is C. The values of the coefficients A, B, and C are stored in registers R1 to R
3 shall be loaded. When the controller 2 receives the frame start signal pulse IP_V indicating the start point of the active scanning line of the frame, the controller 2 selects the selector SEL1.
To select the value C stored in the register R3,
The signal is supplied to the adder 1 via the register REG1. The supply of the value C from the register REG1 to the adder 1 is as follows.
This is performed at the timing when the first pulse of the clock signal HFCK_SYS is input to the register REG1. At the same time, the controller 2 sets the selector SEL2 to 0.
A value is selected and supplied to the adder 1. As a result, the total value C + 0 output from the adder 1 is obtained.
Are two feedback registers FB1 and FB2
Feedback to both. This gives the value C +
0 represents both feedback registers FB1 and FB2
Will be stored. This total value C + 0 is further supplied to the output register REG2, and the clock signal HFC
It is output from the output register REG2 at the timing when the next pulse of K_SYS occurs. Thereafter, each time a pulse of the clock signal HFCK_SYS is transmitted, the selector SEL1 selects the value stored in the register R1 (coefficient A), and the selector SEL2 selects the feedback register FB.
Select the stored value of 1. As a result, the stored value of the feedback register FB1 is continuously incremented, and a plurality of pixel positions h = 0 to 0 on the scan line v = 0 are set.
The integrated value C + hA corresponding to each of n is successively represented. When the end of the scanning line v = 0 is reached, the integrated value stored in the feedback register FB1 is C + nA. At this point, a signal pulse IP_H is sent out to indicate the start of the next scan line. At this time, the selector SEL1 selects the increment value B stored in the register R2, and selects the selector S
EL2 selects the value stored in feedback register FB2 (at this point, equal to value C). The stored value B of the register R2 and the stored value C of the feedback register FB2 are added in the adder 1 to generate a new total value B + C, and this total value is sent to both the two feedback registers FB1 and FB2. Feedback will be given. As a result, the value B + C is stored in both the feedback registers FB1 and FB2 as the signal value of the ramp function signal corresponding to the pixel position h = 0 at the start end on the new scanning line v = 1. . Thereafter, until the end of the scanning line v = 1, the selector SEL
2 keeps selecting the feedback register FB1, the stored values of the feedback register FB1 are continuously and successively integrated to correspond to each of the plurality of pixel positions h = 0 to n on the scan line v = 1. Integrated value C + B + hA
Will be represented one after another. When the end of the scanning line v = 1 is reached, the integrated value C + B + nA is stored in the feedback register FB1. At the beginning of the next scanning line v = 2, the selector SEL1 again selects the coefficient B stored in the register R2, and
EL2 selects the stored value of the feedback register FB2 (which is now C + B), increments the stored value, and feeds it back to both feedback registers FB1 and FB2 to provide them with feedback. .Registers FB1 and F
The stored value of B2 is updated to C + 2B. After this, the value stored in the feedback register FB1 becomes the scan line v = 2
, And when the signal pulse IP_H is transmitted next, the stored value of the feedback register FB2 is again incremented by the coefficient B, and a new value obtained by the increment is obtained. Are two feedback registers FB
1 and FB2. The above-described process is repeatedly performed on each of a plurality of scanning lines arranged in succession, and the next signal pulse IP_V indicating that the frame ends and the next frame starts is generated. Continue until it occurs. Further, the entirety of such a process is performed iteratively for each frame.

As is apparent from the above description, here, the build-up method is performed by calculating the signal value of the ramp function signal corresponding to each pixel in synchronization with the pulse of the clock signal HFCK_SYS. Generates a ramp function signal.

In the above description, the entire area of one frame is 1
It is the case that is occupied by one ramp function.
However, the whole area of one frame is not always occupied by one ramp function, and one ramp function may occupy only a part of the frame.

The method of generating a ramp signal described above inversion ramp function by incrementing sequentially the signal value R, i.e., go one after another adds the value of the coefficient A to the coefficient B Thus, a signal is generated. As a method opposite to this method, the ramp function signal generator in FIG. 5 may generate the inverted ramp function by continuously decrementing the signal value R of the ramp function signal. it can. This is performed using the positive / negative reversal processing circuit 3. The positive / negative reversal processing circuit 3 includes an EXOR circuit and a register REG1.
If one of the increment values stored in R3 is selected, it works to reverse the sign of the selected increment value. The stored increment value is represented in the form of a two's complement. To reverse the sign of the two's complement, all bits representing the numerical value are inverted and 1 is added. The EXOR circuit inverts all bits of the selected increment value in response to the positive / negative reversal processing control bit negCtrl.
The positive / negative reversal processing control bit negCtrl is further supplied as a carry bit to the register REG1.
Thereby, 1 is added to the value of the register REG1. When using this method, as shown in FIG. 6A for one dimension of the ramp function signal 60, first, the signal value of the positive ramp function signal 60 is generated by the method described above, and the signal value Has reached the desired maximum value, as shown in FIG. 6B, the data is continuously decremented from there, and this decrement is performed by using the incremented value whose polarity is reversed. Otherwise, the operation of the ramp function signal generator is no different from using the method described above. The positive / negative reverse processing control bit negCtrl is supplied from the controller 2. By reversing the positive or negative of one or both of the value of the coefficient A and the value of the coefficient B, an inverted ramp function occupying the whole area of the frame can be generated.

A limiter 4 is inserted in the path from the adder 1 to the feedback registers FB1 and FB2 to prevent overflow and underflow of the limit processing for the ramp function . Further, another one is added to the output of the ramp function signal generator.
Two further limiters 5 have been inserted as output limiters. FIG. 7 is a diagram showing how the output limiter 5 limits the output. When the signal value of the ramp function signal exceeds a positive limit value, as shown in FIG. The value can be a positive limit, or
, The value can be a negative limit. When the signal value of the ramp function signal exceeds the negative maximum value, the value can be set to a negative limit value as shown in FIG. 7C, or as shown in FIG. 7D. As such, the value can be a positive limit. The limiter 5 is controlled by the controller 2, and a desired limit processing characteristic is selected by the control.

Changing the values of the coefficients A, B and C
The effect increment value A defines the slope of the ramp function in the scanning line direction. The increment value B is
This defines the slope of the ramp function in the frame direction perpendicular to the scanning line direction. By appropriately changing both A and B at individual magnifications, the effect of rotating the ramp function in space can be obtained. The value of the coefficient C is a value that offsets the ramp function in a direction perpendicular to the line direction and the frame direction. By changing the offset value C, the effect of shifting the intersection of the ramp function and the clip plane can be obtained. That is, by changing the offset value C, the position of the ramp function can be moved within the frame.

Solid Function Signal Generator System
It is shown in binding FIGS. 8 and 9 embodiments ramp function, which is a simplified block diagram of a solid function signal generator system. The solid function signal generator system includes a plurality of ramp function signal generators 80, each of which may include, for example, the ramp function signal generator described above with reference to FIGS. It has a similar configuration. The solid function signal generator systems of FIGS. 8 and 9 include only two ramp function signal generators (further, only one of them is shown in FIG. 8), but in general, The solid function signal generator system can be configured to include more ramp function signal generators, such as with eight ramp function signal generators. The combiner 86 combines the ramp functions. In the combiner 86, the combination of the ramp functions is determined by the control signal supplied to the combiner 86.

The ramp function signals sent from the individual ramp function signal generators can be subjected to edge modification processing in block 81. This edge modification processing will be described later in detail with reference to FIGS. Will be described. The ramp function signal can be further subjected to absolute value processing, positive / negative reversal processing, offset processing, and limit processing.
Indicated at 85. A "box-shaped solid function" can be formed by combining two absolute value ramp functions, which will be described with reference to FIGS. 10, 11, and 12. FIG. The combination of the ramp function is performed by the combiner 86.
This will be described later with reference to FIG. The adjuster 89 is for adjusting the level and scale of the solid function relative to the clip plane. The solid function selector 87 is for selecting one of a solid function signal output from the combiner 86 and an externally generated solid function signal.

The solid function signal generator systems shown in FIGS. 8 and 9 are provided as illustrative examples. The ramp function signal generation method, the edge modification processing method, and the solid function modification processing method used in the solid function signal generator systems of FIGS. 8 and 9 can also be used in other solid function generator systems. Yes, and will be described later.

The solid function signal generator systems of FIGS. 8 and 9 are controlled by a controller 802. Each algorithm defining various wipe patterns is stored in the controller 802, and these algorithms are selected by the control panel 803, and the controller 802 executes the selected algorithm.

The simple ramp function shown in FIG. 10A is a ramp function whose dynamic range is defined in a range from -M to 0 through + M. The signal value of this ramp function is represented by a numerical value (positive / negative value) in the form of a two's complement. The processing by the absolute value function (82) converts all the negative signal values of the ramp function to positive numbers according to a known method, thereby converting the ramp function as shown in FIG. 10B. To be generated. FIG.
The ramp function of B can also be inverted (83), so that a ramp function represented by a negative number as shown in FIG. 10C is obtained. By adding a constant value to the value of the absolute value ramp function, offset processing (vertical movement processing) can be performed (84). FIG.
D shows a ramp function obtained by further performing an offset process on a ramp function (C in FIG. 10) obtained by inverting the sign of the absolute value ramp function (B in FIG. 10). Similarly,
It is also possible to generate a ramp function obtained by performing an offset process on the ramp function of FIG. 10B.

In general, one or some of absolute value processing, positive / negative inversion processing, and offset processing are performed on the ramp function. What is shown in FIG.
One example of a solid function is a "square" solid function. This square-shaped solid function has a quadrangular pyramid shape, and is formed by combining two ramp functions shown in FIG. 10D in directions perpendicular to each other.

FIG. 11 is a diagram showing a preferred specific example of the combiner. The signal values of the two ramp function signals A and B (these signal values may be processed by the processing circuits 81 to 85) have four inputs from a 0th input to a third input. It is supplied to a selector 96. A ramp function signal value A is input to the 0th input, and a ramp function signal value B is input to the first input. The first input of the two ramp function signal values A and B output from the first ramp function combination circuit (97, 98) is input to the second input. To the third input, a second ramp function coupling circuit 99 is provided.
The second combination of the ramp function signal values A and B output from is input. One of the 0th to 3rd inputs is 2
It is selected by a bit selection signal SEL and sent out as an output of the selector 96. The output of the selector 96 is connected to the output of the combiner 93 via another selector 100. The selector 100 selects one of the output of the selector 96 and “0” in response to the 0 selection signal. When the 2-bit selection signal SEL represents “0” or “1”, the ramp function signal value A or B is output through the selector 96 in the form as it is input. Therefore, in such a case, the combiner 93 functions as a switch element or a signal router.

First ramp function coupling circuit (97, 98)
Is composed of an adder 97 and a 1/2 circuit 98. The 回路 circuit 98 has a control input to which a 制 御 control signal is input. The 1/2 control signal is 1
/ 2 circuit 98 is selectively operated. Therefore, selector 9
6 is input to the second input (A +
B) may be input, or (A + B) / 2 may be input.

On the other hand, the second ramp function coupling circuit 99 includes a non-additive mixer (Non-Additive Mixer).
r: NAM), and FIG. 11 shows a specific example of this NAM. The NAM in FIG. 11 is the first selector SE
L1, the second selector SEL2, the third selector SEL3,
And a comparator 104. The comparator 104
The current signal value A of one ramp function is compared with the current signal value B of the other ramp function. And if A> B,
The comparator 104 outputs a logical value “0”, and otherwise outputs a logical value “1”. The first selector SEL1 and the second selector SEL2 operate according to the output of the comparator 104.
Either the input value to the 0th input or the input value to the first input is transmitted as an output. The third selector SEL3 is
The first selector SEL according to the value of the signal POS / NEG
1 and the output of the second selector SEL2. The truth table of this NAM as a whole is as follows.

Ramp function signal value comparison result POS / NEG NAM output A> B POS A B> A POS B A> B NEG B B> A NEG A

When the value of the signal POS / NEG indicates POS, this NAM is always the signal value A and B at any pixel location on any scan line.
The larger value is output. On the other hand, the signal POS / N
When the value of EG indicates NEG, this NAM
Outputs the smaller of the signal values A and B.

Summing up the above, combiner 93 has 5
One of the outputs is selectively output, and the five outputs are the signal value of the ramp function A,
The signal values of the ramp function B, the additive combination of these ramp function signal values, the non-additive mixture of these ramp function signal values, and "0".

Box-shaped solid function "Box-shaped solid function" is a well-known solid function. In order to generate a box-shaped solid function, in FIG. 10, FIG. 11 and FIG. 12, two ramp functions whose directions are orthogonal to each other are subjected to absolute value processing, and then they are subjected to a negative NAM function. What is necessary is just to combine using. If a positive NAM function is used, a box-shaped solid function in another form can be generated.
By using the addition function, another form of solid function can be generated.

Edge Modification Processing FIG. 16B shows one specific example of the edge modification signal. The edge modification signal changes sinusoidally in the scanning line direction (extending direction of the scanning line), and the manner of change is uniform in all the scanning lines of the frame. FIG. 16C
The edge modification signal shown in (1) changes sinusoidally in the frame direction (the direction orthogonal to the direction in which the scanning lines extend), and the manner of change is uniform in the scanning line direction. D in FIG.
The edge modification signal shown in (1) changes sinusoidally in the scanning line direction, and the phase is relatively shifted between adjacent scanning lines. Therefore, a wavefront WF is formed by a set of sine waves, and the direction of this wavefront is inclined at an angle θ with respect to the scanning line direction. E of FIG. 17 shows one specific example of the solid function. The solid function of this embodiment is composed of only one simple ramp function, and is combined with a sinusoidal edge-modifying signal having the form shown in FIG. Are modified as a whole, and as a result, an edge modification effect occurs at the intersection with the clip plane CP.

This edge modification function is realized by the ramp function signal generator shown in FIG. 13, that is, the ramp function signal generator shown in FIG. By performing the conversion by the circuit described above, a desired edge-modified waveform is obtained. For ease of explanation, first, FIG. 13 and FIG.
A method for generating a sinusoidal edge modification signal having the form shown in FIG.

The ramp function signal generator shown in FIG. 13 includes an output register REG, which is clocked at a pixel rate by a clock signal HFCK_SYS. Register RE
The output of G is supplied to one input of the adder 121. The other input of the adder 121 includes a selector SEL1
Through the coefficient register 12 storing the value of the coefficient L.
2 and a coefficient register 123 storing the value of the coefficient M. The output of the adder 121 is the selector S
It is coupled to the register REG via EL3. Here, assuming that the functions of the two selectors SEL1 and SEL3 are ignored, the register REG and the adder 121 form an integrator that continuously adds the selected coefficient to the content of the register REG. It can be said that there is. Register RE
G is configured so that its accumulation operation is circulated without being reset, that is, the value stored in this register REG increases, and all bits that are the maximum value of this register reach "1". If this is the case, all the bits that are the minimum value of this register REG pass the state of "0", and the integration is further continued from there. Therefore, the register REG repeatedly executes the operation of successively outputting numerical values.

The selector SEL3 is connected to the output register REG.
Is provided for preloading the value selected by the selector SEL2.
Either the value N stored in 24 or the value stored in the feedback register 125 is selected. The value stored in the output register REG includes a count L and a coefficient M
Is incremented by the value of the coefficient selected by the selector SEL1.

The operation of the ramp function signal generator described above is as described below. By performing the operation, the signal value of the ramp function signal is generated according to the following equation. R = Lh + Mv + N In this equation, h is the pixel position on the scan line,
v is a scanning line number. H and v are numbers indicating the order, and h = 0 to n and v = 0 to m.

At the pixel position h = 0 on the scanning line v = 0, the value of the coefficient N stored in the coefficient register 124 is selected by the selectors SEL2 and SEL3.
It is preloaded into the output register REG. Therefore, the output register REG outputs the value of the coefficient N, and the output value is fed back to the adder 121 and also fed back to the feedback register 125 enabled at this time. Is stored in Pixel location h
= 1, the selector SEL1 selects the value of the coefficient L stored in the coefficient register 122,
The value N stored in G is incremented by this value L, whereby the value stored in the output register REG becomes N +
It becomes L. This value N + L is fed back to the adder 121, but not to the feedback register 125, since the feedback register 125 is now disabled. Thereafter, similarly, the accumulation is repeated by the output register REG and the adder 121, so that the accumulated value is represented by N + hL. When the integrated value N + hL reaches the maximum value of the output register REG, the output register REG rolls over. Therefore, the stored value passes through “0”, and from there the hL reaches the maximum value again.
Are accumulated. This integration is continued until the end of the scanning line v = 0. The repetition period of the operation for integrating hL is determined by the value of coefficient L. The phase at the start of the integration is determined by the value of the coefficient N.

When the end of the scanning line v = 0 is reached, the selectors SEL2 and SEL3 select the coefficient N again, and the value of the coefficient N is preloaded into the output register REG, which is fed back to the adder 121. You. Also,
If necessary, the selector SEL1 selects the coefficient M, and the value obtained by adding the value of the coefficient M to the value of the coefficient N in the adder 121 is stored in the output register REG, which is output to the adder 121. Feedback,
At this time, the feedback is also fed back to the enabled feedback register 125, whereby the value N + M is stored in the feedback register 125. Thereafter, the selector SEL1 again selects the coefficient L, and the integration is repeated, and the integrated value is N + M + hL
It is represented by If the integrated value N + M + hL reaches the maximum value of the output register REG while the integration is performed on the scanning line v = 1, the output register REG rolls over and the stored value passes “0”. Then, the integration of hL is continued again toward the maximum value, and this is performed in the same manner as the integration on the scanning line v = 0 described above. When the end of the scanning line v = 1 is reached, the selector SEL2
Selects the value N + M from the feedback register 125 enabled at this time, and the value N + M is preloaded into the output register REG by the selector SEL3. This value N + M is output from the register REG and fed back to the adder 121. continue,
Since the selector SEL1 selects the value of the count M stored in the register 123, the value N + 2
M is output. This value N + 2M is output register REG.
And output therefrom to adder 121
Is fed back to the feedback register 125 enabled at this time, and is stored in the feedback register 125. Thereafter, the integration is repeated as in the case of the scanning line v = 0 or the scanning line v = 1 described above, and the integrated value is represented by N + 2M + hL. The above process is repeated for each successive scan line, and each time a transition is made to the next scan line, the output register RE
The value preloaded into G is incremented by the value of coefficient M. By performing the increment by the coefficient M, there is an effect that the integration phase is shifted by a magnitude corresponding to the value of the coefficient M for each scanning line.

Based on the signal value R of the ramp function signal output from the output register REG in this manner, RO in FIG.
The look-up table stored in M130 is addressed, thereby generating a sinusoidal modification signal. The ROM 130 may store all values for one cycle of the sine wave. In the illustrated example, the ROM 130 stores only the value of a portion corresponding to one quadrant of the sine wave. In addition, the amount of stored data is reduced.
In the illustrated example, the signal value R of the ramp function signal is represented in the form of an 11-bit two's complement, and the lower 9 bits of the 11 bits are assigned to bits for addressing the ROM 130. The upper two bits of the 11 bits are used to specify which quadrant value is to be generated. In FIG. 16A, four quadrants of the sine function are represented by quadrants a to d. If the upper two bits are "00", the value in quadrant a is selected. If the upper two bits are “01”, quadrant b
In this case, the address obtained by inverting the lower 9 bits by the address inversion processing unit 133 is used. If the upper two bits are "10", a value in the quadrant c is generated. In this case, the positive / negative reversal processing unit 134
, The value of the sine function data is subjected to a positive / negative reversal process. If the upper two bits are "11", a value in the quadrant d is generated. In this case, both the inversion of the address and the inversion of the sine function data are performed. .

Referring back to FIG. 14, the upper two bits of the 11-bit signal value R of the ramp function signal are sent to the logic 132 in order to specify which quadrant part of the value is to be generated. Supplied. The logic 132 receiving the two bits outputs a positive / negative reverse enable signal S
And a 1-bit address inversion enable signal I and a 2-bit switching control signal. The 2-bit switching control signal is a signal for controlling the selector 136 according to which quadrant has been designated. The lower 9 bits of the signal value R of the ramp function signal are supplied to the ROM 130 via the address inversion processing unit 133. The address inversion processing unit 133 inverts the address according to the inversion enable signal I received from the logic 132 or supplies the address to the ROM 130 without inversion. The ROM 130 is addressed by the address supplied from the address inversion processing unit 133, and data representing a value corresponding to a desired position in the quadrant is output.
The data output from the ROM 130 is transmitted to the positive / negative
The positive / negative inversion processing unit 134 inverts the sign of the data in accordance with the positive / negative inversion enable signal S received from the logic 132 or passes the data without inversion. A gain adjustment unit 135 is connected to the subsequent stage of the positive / negative inversion processing unit 134, and the gain adjustment unit 135 controls the amplitude of the decoration signal. Subsequently, the decoration signal is added to the signal value of the solid function signal, for example, by adding the decoration signal in the adder 81 to the solid function signal generated by the ramp function generator 80 of FIG. .

FIG. 16B shows one specific example of the sinusoidal modification signal. In this specific example, N = 0,
This is a decoration signal generated when M = 0. The frequency of the decoration signal is determined by the value of the coefficient L. The sinusoidal change occurs repeatedly in the scanning line direction, and the phase shift amount of the sinusoidal change on the scanning line with respect to the start point of each scanning line is determined by the value of the coefficient N. The phase shift amount of the sine wave change on the subsequent scanning line is determined by the value of the coefficient M. FIG. 16C shows a specific example where N = 0 and L = 0, and the direction in which the decoration signal changes in a sine wave shape is the frame direction. FIG. 17D shows a specific example in which N = 0 and the values of L and M are not 0, and the direction in which the decoration signal changes sinusoidally is the value of L and M. It is a diagonal direction determined by. In this specific example, since the value of M is not 0, the amount of phase shift between the preceding scanning line and the succeeding scanning line is accumulated.

By adding the modification signal of FIG. 16C to the solid function signal, for example, a signal as shown in FIG. 17E is obtained. In the specific example shown in FIG. It consists of two simple ramp functions. The simple ramp function thus modified and the clip plane intersect at the intersection line CL, and the intersection line CL is a projection of the modification signal onto the clip plane. The modification process is performed only on one edge. When it is desired to apply a modification process to a plurality of edges of one solid function, the edge function is individually applied to each of a plurality of ramp functions constituting the solid function, and then the ramp functions are combined. To construct a solid function.

As shown in FIGS. 14 and 15, it is also possible to generate edge modification patterns of various shapes other than the sine function. FIGS. 15E to 15H show a case where a decoration signal having a triangular wave shape is generated.
Alternatively, it can be generated only by performing the positive / negative inversion processing, and no other processing is required. Also, i in FIG.
1 to 1 show a case where a rectangular wave-like decoration signal is generated, and this decoration signal selectively performs positive / negative inversion processing on upper two bits of the signal value R of the ramp function signal, and / or , By performing a reversal process.

Referring now to FIG. 14 again, how these non-sinusoidal modification patterns are generated under the control of the logic 132 will be described. The logic 132 decodes the quadrant selection signal and outputs a 4-bit 2 representing a numerical value corresponding to decimal numbers “0” to “15”.
A binary number is generated, and a combination of the positive / negative reversal process and the reversal process and a pattern type as shown in FIG. 15 are selected based on the binary number. The portion of the pattern selection signal of the 4-bit binary number is supplied to the selector 136.
In addition to the sine wave data input from the ROM 130, the signal value of the ramp function signal is input to the selector 136 as it is to the input 137 of the selector 136. A rectangular wave pattern generated by the logic 138 based on the upper two bits is also input. In addition, in the specific example of the edge modification unit shown in FIG. 14, a pseudo random number is also input to the input 139 of the selector 136. The selector 136 selects one of the inputs according to the pattern selection signal. When the selector 136 is controlled to select the input 139, the effect is obtained that the edge is modified by random “noise”. Logic 132 may be comprised of a 16-bit register that functions as a 4 × 4 bit look-up table. By rewriting the 16-bit input value stored in the register,
Various edge modification patterns can be set.

Solid Function Modification Processing FIG. 18 shows a simple example of a solid function modification processing. The specific example shown is a box-shaped solid function 1
61 (which is formed by combining two ramp functions subjected to absolute value processing, as described above), is formed by additively combining two sine waveforms 162 and 163 which are orthogonal to each other. It is a combination of composite waveforms. In the solid function that has been subjected to the solid function modification processing as described above, the line of intersection with the clip plane has a general shape as indicated by 164 in the drawing.

The solid function modification processing is different from the edge modification processing in that the solid function modification processing is processing that is executed after a solid function is formed by combining a plurality of ramp functions, and / or two types of modification are performed. That is, the process is performed using a composite modified waveform formed by combining the waveforms.

Therefore, the solid function modification processing is to modify the entire solid function (not just one edge) using the modification waveform. The modification waveform used here is composed of two types of waveforms. It is particularly preferable to form the structure by bonding

In the specific example of FIG. 19, two waveform generators (reference numerals 170 and 17) described with reference to FIGS. 14 and 15 are used to generate a solid function modification signal.
1), and combines the two waveforms respectively generated in these waveform generators. The combination of the two waveforms is performed in the combiner described with reference to FIGS. 11 and 12 (indicated by reference numeral 172). Note that the two waveforms to be combined can be any of various types of waveforms that can be generated by the waveform generator of FIG. For example, a sine wave and a rectangular wave can be combined. Further, even for the same type of waveform, the shape can be made different by changing the values of the coefficients L, M, and N. Further, the combiner 172 has both a function of performing an additive combination and a function of performing a non-additive combination. Therefore, it is possible to generate a large number of modification signals having different shapes.

In the specific example of FIG. 19, two waveforms are combined, but three or more waveforms may be combined. Also, the solid function modification processing unit may be provided together with the edge modification processing unit, or a solid function modification processing unit may be provided instead of the edge modification processing unit. Further, the solid function modification processing may be performed on a solid function that has not been subjected to the edge modification processing, or may be performed on a solid function that has been subjected to the edge modification processing.

Pairing Each of the two solid functions shown in FIGS. 20A to 20C as concrete examples has, as shown in FIG.
It consists of two simple ramp functions, and a "striped pattern" is formed in the simple ramp function. In the figure,
The hatched stripes represent the portion where the image of one video source Y is displayed, and the blank portions between the unhatched stripes and the stripes of the other video source X. Represents the part where the image is displayed. Then, the image of the video source X is replaced with the image of the video source Y by these two solid functions. As shown in FIG. 20B, the stripe portion of one solid function and the stripe portion of the other solid function are in a complementary positional relationship. Such two striped solid functions are called a “pair solid function”. These two solid functions can be fused as shown in FIG. 20C, i.e., as the height of the clip plane is reduced, both stripes in a complementary positional relationship fuse with each other. Go. The solid functions shown in FIG. 20 each consisting of only one simple ramp function are merely presented as specific examples, and a plurality of striped ramp functions are combined to form a more complicated solid function. It is also possible to configure.

As shown in FIG. 20A, first, a pair of ramp functions is generated. In the specific example shown in FIG. 20A, each ramp function corresponds to the inverse of the other ramp function, but in general, there is a specific relationship between the two ramp functions. Need not be present. Subsequently, based on the stripe portion selection waveform shown on the left side of FIG. Select multiple stripes. FIG.
In the specific example, the extending direction of the stripe pattern is set in the horizontal direction of the screen. However, as shown in FIG. 21, the extending direction of the stripe pattern can be set in either the vertical direction or the horizontal direction of the screen.

FIG. 22 is a block diagram showing a circuit for generating a pair ramp function. The circuit includes a first ramp function generation unit and a second ramp function generation unit. The first ramp function generation unit includes a first ramp function signal generator 201 and a second ramp function signal generator 202. Similarly, the second
The ramp function generating unit also includes a first ramp function signal generator 203 and a second ramp function signal generator 204.
And Ramp function signal generator 201-
Each of 204 is, for example, similar to the ramp function signal generator described with reference to FIG. Since the first and second ramp function generating units have the same configuration, only the first ramp function generating unit will be described in detail here. The first ramp function generation unit includes a selector 205, which is controlled by the stripe portion selection waveform, and alternates between the output of the first ramp function signal generator 201 and the output of the second ramp function signal generator 202. To choose. These two ramp functions generated by the ramp function signal generators 201 and 202 may be, for example, one in which one ramp function corresponds to the inversion of the other ramp function, as shown in FIG. In general, however, the two ramp functions generated by these ramp function signal generators may be independent of each other. However, there is usually some relationship between the two ramp functions, as in the example above, so that one ramp function is the inverse or mirror image of the other ramp function. Many. In general, however, there is no need for a specific relationship to exist between the ramp functions. The ramp functions generated in ramp function signal generators 201 and 202 are functions defined by the values of coefficients A, B, and C, the values of which are controlled by state machine / decoder controlled by controller 207. From 206, it is supplied to ramp function generators 201 and 202. The generated ramp function signal may be subjected to limit processing by the limiter 208.

The stripe portion selection signal is sent from the signal generator 210 shown in FIG. The signal generator 210 generates a rectangular wave, and the width of the stripe portion is determined by the rectangular wave.
The position of each stripe portion within the frame is determined.
Using this rectangular wave, a horizontal stripe (horizontal stripe) can be selected, and a vertical stripe (vertical stripe) can be selected. First, in order to facilitate understanding of the description, a case where a vertical stripe pattern is selected will be described. In this case, in order to generate a square wave, the counter 21
Let 1 count the pulses of the clock signal HFCK_SYS being sent at the pixel rate. The output count value of the counter 211 is compared in the comparator 212 with a count value indicating the reference width set by the controller 207. When the count values become equal, the counter 211 is reset,
The count value is returned to “0”. This counter 21
Each time a 1 is reset, the state of the bistable flip-flop (toggle register) 213 changes from "0" to "1".
, Which generates the above-described square wave. Further, the data is loaded into the counter 211.
By supplying the enable pulse loadEn, the counter 211 has the count value PAIR_PHA.
The SE is preloaded, and the initial phase of the count value of the counter 211 can be set by this preload. Therefore, by the preload, the position of the leading edge of the first stripe portion relative to the starting point of each scanning line can be set. Also,
When the enable pulse loadEn is transmitted, the state of the bistable flip-flop 213 is reset so that the positive and negative directions of the rectangular wave are correctly set at the start point of each scan line.
Further, in the EXOR gate 214, the square wave and the PAI
By combining the signal with the R_SENSE signal, the positive and negative directions of the rectangular wave can be reversed.

On the other hand, when creating a stripe pattern extending in the horizontal direction of the screen, the counter 211 is caused to count the signal pulse IP_H indicating the starting point of the scanning line. In other respects, the same operation as in the case of creating a stripe pattern extending in the vertical direction of the screen described above is performed.
The setting of the phase of the starting point of the stripe portion is performed by the count value PAIR
This is performed by preloading _PHASE. By using this preload, for example, 625/50 and 525 /
As in 60, the center of the stripe portion can be aligned between different video signal systems.

Here, a plurality of ramp function generating units are provided, all of them are supplied with the same stripe portion selection signal, and the first ramp functions generated by each of the ramp function generating units are connected to each other. Are combined to form a first composite solid function, and the second ramp function generated by each of these ramp function generation units is combined to form a second composite solid function. To combine the ramp functions, for example, a ramp function combiner having the same configuration as the ramp function combiner 209 shown in FIGS. 10, 11, and 12 may be used. By doing so, one ramp function combiner combines the first ramp function with another solid function, and another ramp function combiner forms the second ramp function combiner.
The solid function formed by combining ramp functions is a paired solid function.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a screen switching process by a wipe;

FIG. 2 is a diagram showing a solid function together with a keying signal.

FIG. 3 is a block circuit diagram of a known wipe generator.

FIG. 4 is a schematic diagram showing a solid function together with a clip plane.

FIG. 5 is a block circuit diagram of a specific example of a ramp function signal generator.

FIG. 6 is a diagram for describing the process of reversing the positive and negative of the ramp coefficient.

FIG. 7 is a diagram for explaining a specific example of a limit process for a ramp function signal.

FIG. 8 is a block circuit diagram (part 1) of a specific example of a solid function signal generator system.

FIG. 9 is a block circuit diagram (part 2) of a specific example of the solid function signal generator system.

FIGS. 10A to 10E are diagrams for explaining an absolute value process, a positive / negative inversion process, a vertical movement process, and a combination process;

FIG. 11 is a block circuit diagram of a ramp function combiner.

FIG. 12 is a block circuit diagram of a non-additive mixer of the ramp function combiner of FIG. 11;

FIG. 13 is a block circuit diagram of another ramp function signal generator used in the edge modification processing unit.

FIG. 14 is a block circuit diagram of an edge modification processing unit.

FIG. 15 is a schematic diagram showing an edge modification pattern.

FIGS. 16A to 16C are diagrams for explaining the operation of the edge modification processing unit.

17A and 17B are diagrams for explaining the operation of the edge modification processing unit.

FIG. 18 is a simple diagram showing a specific example of a solid function modification process.

FIG. 19 is a block circuit diagram of a circuit for generating a solid function modification processing waveform.

20A to 20C are schematic diagrams for explaining pairing.

FIG. 21 is a diagram showing a stripe pattern extending in a vertical direction and a stripe pattern extending in a horizontal direction of a screen.

FIG. 22 is a block circuit diagram of a pairing generator.

FIG. 23 is a block circuit diagram of a control signal generator of the pairing generator of FIG. 22;

[Explanation of symbols]

1 ‥‥ adder, 2 ‥‥ controller, 3 ‥‥ positive / negative reversal processing circuit, 4 ‥‥ limiter, 5 ‥‥ limiter,
6 computer, 201 first ramp function signal generator, 202 second ramp function signal generator, 203 first ramp function signal generator, 204 second ramp function signal generator,
205 ‥‥ selector, 206 ‥‥ state machine / decoder,
207 ‥‥ controller, 208 ‥‥ limiter,
209 {combiner, FB1, FB2} feedback registers, R1, R2, R3 {coefficient registers, REG1, REG2} registers, SEL1, S
EL2 @ selector

Claims (11)

[Claims] 1. A signal generator, comprising: a pair of ramp function signal generators comprising a first ramp function signal generator and a second ramp function signal generator; Of a set of scan lines vr1 (vr1 = 0 to m), each of a set of pixels consisting of a predetermined plurality of pixels hr1 (hr1 = 0 to n) present on each of the scan lines. For each pixel, the signal value Rr1 of the first ramp function signal, which is a video signal, is represented by Rr1 = A1 ·
hr1 + B1 · vr1 + C1, where A1, B1, and C1 are coefficients each of which can take a positive or negative value. The second ramp function signal generator performs a predetermined plurality of scans of the screen. For each pixel of the set of pixels hr2 (hr2 = 0-n) on a respective scan line of the set of scan lines consisting of line vr2 (vr2 = 0-m) , The signal value Rr2 of the second ramp function signal, which is a video signal, is represented by Rr2 = A
2 · hr2 + B2 · vr2 + C2, where A2, B2, and C2 are coefficients that can take positive and negative values, respectively. Further, in the screen, the first ramp function signal and the second
A signal generator comprising selection means for alternately selecting a ramp function signal. 2. The apparatus according to claim 1, wherein the selection unit alternately selects the first ramp function signal and the second ramp function signal along the scanning line of each of the screens. Signal generator. 3. The method according to claim 1, wherein when the selection unit sets p to be an integer of 2 or more, the first ramp function signal and the second 2. The signal generator according to claim 1, wherein the signal generator and the ramp function signal are alternately selected. 4. Each of the ramp function signal generators includes: a value of each of the coefficients A, B, and C; a first integrated value;
Storage means for storing a second integrated value; and incrementing the first integrated value by the value of the coefficient A;
An adding means for incrementing the second integrated value by the value of the coefficient B; and a control means, wherein the adding means adds the second integrated value to the adding means in correspondence with each of the plurality of scanning lines vr. The value is incremented by the value of the coefficient B to generate a value represented by C + Bvr, and the value C + Bvr is stored as both the first integrated value and the second integrated value. A value represented by C + Bvr + Ahr by causing the adding means to increment the first integrated value by the value of the coefficient A in correspondence with each of the plurality of pixels on each of the scanning lines. And the control means for storing the value C + Bvr + Ahr as the first integrated value and outputting the value as the signal value Rr. Any one of claims signal generator 1 to 3. 5. The storage means includes: a plurality of coefficient registers for storing respective values of the coefficients A, B, and C; and the first integrated value and the second integrated value, respectively. And a means for selectively coupling the registers to the summing means and for storing the output of the summing means in at least one of the plurality of feedback registers. 5. The signal generator according to claim 4, wherein: 6. The control means includes a selection means for selectively coupling the plurality of registers to the addition means, and an output of the addition means is provided for the plurality of feedback circuits.
6. The signal generator according to claim 5, wherein the signal generator is coupled to a register, and wherein the control means selectively enables the plurality of feedback registers to store the integrated value. 7. A means for selectively performing a positive / negative reversal process on the value of the coefficient before the value of the coefficient is a positive / negative value and supplied to the adding means. 7. The signal generator according to claim 4, 5 or 6, wherein: 8. The signal generator according to claim 3, further comprising means for selectively performing a limit process on the signal value Rr of the ramp function signal. 9. The apparatus according to claim 1, further comprising means for selecting respective values of the coefficients A, B, and C.
The signal generator according to 2, 3, 4, or 5. 10. The signal generator according to claim 1, further comprising: means for performing an edge modification process on the ramp function signal. 11. A solid function signal generator, comprising: a plurality of signal generators according to claim 1; and a plurality of ramp functions respectively generated by a plurality of said first ramp function signal generators. First combining means for generating a first solid function signal by combining signals; and further combining a plurality of ramp function signals respectively generated by the plurality of second ramp function signal generators. A solid function signal generator, comprising: a second combining means for generating a second solid function signal according to the following.