JP2000339224A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system in which no third party except a specified person is allowed to easily perform writing to a memory. SOLUTION: A writing mode signal WM is generated when potential of an input terminal 4 shows a specified state by a hardware setting circuit 5. A writing permission signal S5 is generated when a preset sequence is recognized by a sequence recognizing means 12. A writing signal WS is outputted to a flash memory 3 when the signal WM is generated by the hardware setting circuit 5 and the signal SS is generated by the sequence recognizing means 12 by a writing signal generating circuit 6A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory system including a memory and a memory control circuit for controlling writing to the memory.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of the configuration of a conventional memory system. The memory system 1 of FIG. 6 has a flash memory 3, a flash memory control circuit 7, and an input terminal 4. The input terminal 4 is a specific terminal exposed to the outside.

When writing data to the flash memory 3, first, a signal that changes in accordance with a predetermined sequence is given to a plurality of predetermined terminals such as a write enable terminal, a chip enable terminal, and an address terminal of the flash memory 3 to thereby write the data into the flash memory 3. 3 must be in a write-permitted state. Hereinafter, a signal given to a plurality of predetermined terminals to bring the flash memory 3 into a write-permitted state is referred to as a write signal WS. Thereafter, by applying an address signal to the address terminal of the flash memory 3 and applying data to the data input terminal, data can be written to a desired address.

In the memory system 1 shown in FIG.
Is set to a predetermined value or more, the flash memory control circuit 7 generates the write signal WS. Thereby,
The flash memory 3 enters a write permission state.

[0005]

Next, the use state of the memory system will be briefly described with reference to FIG. Here, for the sake of simplicity, a user who uses the memory system 1 is taken as an example of a specific person whose writing to the flash memory 3 is prohibited. In addition, a vendor who supplies the memory system 1 to a user is given as an example of a specific person permitted to write to the flash memory 3. For example, a user is a person who receives and pays for satellite broadcasting by a satellite broadcasting system,
The vendor supplies satellite broadcasting by a satellite broadcasting system to the user. The memory system 1 stores, for example, a program for determining a price to be paid by a user upon receiving a satellite broadcast supplied by a vendor.

FIG. 7A shows a state in which the vendor 9 writes data 10 to the flash memory 3 of the memory system 1 before the vendor 9 supplies the memory system 1 to the user 8. Here, the concept of data includes a program.

FIG. 7B shows that, after the vendor 9 supplies the memory system 1 to the user 8, the user 8 is prohibited from writing the data 10 to the flash memory 3 of the memory system 1. This shows a state where writing of data 10 to the flash memory 3 in the memory system 1 owned by the user 8 is permitted. For example, in the case of the above example, the vendor 9
10 indicating a program for determining the price set by the user
Is prohibited from being rewritten by the user 8 without the permission of the vendor 9, while rewriting the program by the vendor 9 is allowed.

As shown in FIGS. 7A and 7B, writing to the flash memory 3 is prohibited for the user 8 and writing to the flash memory 3 is enabled for the vendor 9. Function may need to be provided to the memory system 1 in some cases. As such an example, there is a case where the program stored in the memory system 1 needs to be rewritten by the vendor 9 due to a change in the price of the satellite broadcast.

As described above, in the conventional memory system 1, the flash memory 3 can be set in a write-permitted state by setting the potential of the input terminal 4 exposed to the outside. Not only those who are permitted to write data but also those whose writing is prohibited such as the user 8 can easily rewrite data in the flash memory 3.

An object of the present invention is to provide a memory system in which a third party cannot easily write to a memory except for a specific person.

[0011]

Means for Solving the Problems (1) First invention A memory system according to a first invention has a memory, an input terminal for receiving a predetermined signal, and an input terminal when the signal of the input terminal is in a predetermined state. First signal generating means for generating a first signal, second signal generating means for generating a second signal when sequence information indicating a preset sequence is input, and first signal generating means Write control means for controlling writing of data to the memory based on the first signal generated by the means and the second signal generated by the second signal generation means.

In the memory system according to the present invention,
When the signal at the input terminal is in a predetermined state, the first signal is generated by the first signal generating means. When sequence information indicating a preset sequence is input, a second signal is generated by the second signal generating means. The writing of data to the memory is controlled by the write control means based on the first signal generated by the first signal generation means and the second signal generated by the second signal generation means.

Therefore, it is possible to write into the memory only when the signal at the input terminal is in a predetermined state and when predetermined sequence information is input. Writing to the memory can be prevented. Thereby,
A third party cannot easily write to the memory except for a person who knows the sequence information.

(2) Second invention In a memory system according to a second invention, in the configuration of the memory system according to the first invention, the second signal generation means determines whether or not sequence information is given. And an arithmetic processing unit that executes a program to be executed.

In this case, the second signal generating means determines that the predetermined sequence information has been provided by the arithmetic processing unit which executes a program for determining whether or not the predetermined sequence information has been provided. Thus, a second signal can be generated. Therefore, it is possible to prevent a third party from easily writing data into the memory except for a person who knows the sequence information determined by the program.

(3) Third invention In the memory system according to the third invention, in the configuration of the memory system according to the first or second invention, the write control means includes a first signal generation means for controlling the first signal generation means. And a write signal generating means for generating a write signal permitting writing of data to the memory when the signal is generated and the second signal is generated by the second signal generating means.

In this case, even if the signal at the input terminal is in a predetermined state, the write signal generation means does not generate a write signal unless predetermined sequence information is input to the second signal generation means. Writing data to the disk is not allowed. Therefore, it is possible to prevent a third party from easily writing to the memory except for a person who knows the sequence information.

(4) Fourth Invention In a memory system according to a fourth invention, in the configuration of the memory system according to the first or second invention, the write control means includes a first signal generation means for controlling the first signal generation means. A write signal generating means for generating a write signal for allowing data to be written to the memory when the signal is being generated;
A memory reset signal generating means for generating a memory reset signal for interrupting writing to a memory when the first signal is generated by the signal generating means and the second signal is not generated by the second signal generating means; Is included.

In this case, even if the signal at the input terminal is in a predetermined state and the write signal generating means has generated a write signal permitting data to be written to the memory, the second signal generating means can transmit predetermined sequence information to the second signal generating means. Is not input and the second signal is not generated, the memory reset signal generating means generates a memory reset signal to interrupt writing to the memory. Therefore, it is possible to prevent a third party from easily writing to the memory except for a person who knows the sequence information.

(5) Fifth Invention The memory system according to the fifth invention is the same as the memory system according to the first or second invention, further comprising a processing system for performing a predetermined process using the memory. Control means for generating, when the first signal is generated by the first signal generation means, a write signal for permitting writing of data into the memory;
And a system reset signal generating means for generating a system reset signal for resetting the processing system together with the memory when the first signal is generated by the signal generating means and the second signal is not generated by the second signal generating means. It is a thing.

In this case, even if the signal at the input terminal is in a predetermined state and the write signal generating means has generated a write signal permitting writing of data to the memory, the second signal generating means has a predetermined sequence information. Is not input and the second signal is not generated, the system reset signal generating means generates a system reset signal for resetting the processing system together with the memory. Therefore, it is possible to prevent a third party from easily writing to the memory except for a person who knows the sequence information.

(6) Sixth invention In a memory system according to a sixth invention, in the configuration of the memory system according to the first or second invention, the write control means includes a first signal generation means for outputting the first signal. Write signal generation means for generating a write signal permitting data to be written to the memory when is generated, a first signal generated by the first signal generation means, and a second signal generated by the second signal generation means. A write-inhibit signal generating means for generating a write-inhibit signal for inhibiting data writing to the memory regardless of the write signal when no signal is generated.

In this case, even if the signal at the input terminal is in a predetermined state and the write signal generating means has generated a write signal permitting writing of data to the memory, the predetermined sequence information is transmitted to the second signal generating means. If the signal is not input and the second signal is not generated, the write inhibit signal generating means generates a write inhibit signal for inhibiting data writing to the memory. Therefore, it is possible to prevent a third party from easily writing to the memory except for a person who knows the sequence information.

(7) Seventh Invention A memory system according to a seventh invention comprises a memory, an input terminal for receiving a predetermined signal, and writing of data to the memory when the signal at the input terminal is in a predetermined state. Write signal generating means for generating an allowable write signal, a processing system for performing predetermined processing using a memory, and a processing system as a system reset signal for resetting the write signal generated by the write signal generating means together with the memory And a system reset signal assigning means which can be set to be given to

In the memory system according to the present invention,
When the signal at the input terminal is in a predetermined state, a write signal is generated by the write signal generating means. The write signal generated by the write signal generating means can be set by the system reset signal providing means so as to be provided to the processing system as a system reset signal for resetting the processing system together with the memory.

Thus, until the signal at the input terminal is in a predetermined state until the system reset signal applying means is set to give the write signal generated by the write signal generating means to the processing system as the system reset signal. Since the one signal generating means generates the first signal and the write signal generating means generates a write signal allowing writing of data to the memory, data can be written to the memory. On the other hand, after the system reset signal applying means is set to give the write signal as a system reset signal to the processing system, the write signal generated by the write signal generating means when the signal of the input terminal is in a predetermined state The signal is given to the processing system as a system reset signal, and the memory is reset together with the processing system. Therefore, it is possible to prevent a third party from easily writing to the memory.

[0027]

Embodiment 1 Hereinafter, a memory system according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration example of the memory system according to the first embodiment.

The memory system 1A shown in FIG. 1 includes a flash memory 3, an input terminal 4, and a flash memory control circuit 7A. The flash memory 3 is set in a write-permitted state by a write signal WS, similarly to the conventional flash memory 3. In the memory system 1A, the flash memory control circuit 7A outputs the write signal W
Generate S.

The flash memory control circuit 7A includes a hardware setting circuit 5, a sequence recognition means 12, and a write signal generation circuit 6A.

The hardware setting circuit 5 generates a write mode signal WM when the potential of the input terminal 4 is in a predetermined state. For example, the hardware setting circuit 5 has the input terminal 4
Is equal to or higher than 2.5 V, the write mode signal WM
And the write mode signal WM is not generated if the potential of the input terminal 4 is less than 2.5V.

On the other hand, the sequence recognizing means 12 is constituted by a central processing unit which executes a predetermined program, and outputs a write enable signal SS when recognizing a specific sequence set in advance to input sequence information SI. appear. The sequence information SI may be, for example, a character code. In this case, the sequence recognizing means 12 generates the write permission signal SS when a predetermined character code is input as the sequence information SI, and does not generate the write permission signal SS otherwise.

The write signal generation circuit 6A writes data to the flash memory 3 when the hardware setting circuit 5 generates the write mode signal WM and the sequence recognition means 12 generates the write enable signal SS. An allowable write signal WS is output. In other words, even if the hardware setting circuit 5 generates the write mode signal WM and the sequence recognition means 12 does not generate the write permission signal SS, the write signal generation circuit 6A outputs If the hardware setting circuit 5 has not generated the write mode signal WM even though the SS has been generated, or if the hardware setting circuit 5 has not generated the write signal WS and the sequence
Is not generated, the write signal WS is not generated.

As described above, according to the memory system 1A of the present embodiment, the potential of the input terminal 4 is set to a predetermined state and the sequence information SI is
When the data is input to the flash memory 3, writing to the flash memory 3 is permitted. Therefore, only a person who grasps the sequence information SI set in the sequence recognizing means 12 can perform writing to the flash memory 3, and can perform writing to the flash memory 3 only by setting the potential of the input terminal 4. Can not.

In this embodiment, the input terminal 4 corresponds to an input terminal for receiving a predetermined signal, and the hardware setting circuit 5
Corresponds to the first signal generation means, and the sequence recognition means 1
2 corresponds to a second signal generating means. The write signal generation circuit 6A corresponds to write control means or write signal generation means for generating a write signal when the first signal is generated and the second signal is generated.

In the situation shown in FIG. 7B, FIG.
(B) Instead of the memory system 1, the memory system 1
When using the memory system A, the user 8
In order for only the vendor 9 to perform the writing while prohibiting the writing of the data to the, only the vendor 9 should know the sequence set in the sequence recognition means 12.

The sequence recognizing means 12 may be configured so that a preset sequence can be changed.
Moreover, you may comprise so that it cannot be changed.

In the case where the sequence set in the sequence recognizing unit 12 cannot be changed, for example, the user 8 accidentally changes the sequence set in the sequence recognizing unit 12, and the vendor 9 knows it. It is possible to prevent the occurrence of a situation in which the existing sequence does not match the sequence set in the sequence recognition means 12. On the other hand, sequence recognition means 1
In a configuration in which the sequence set to 2 can be changed, the user 8 happens to
Even if the vendor 9 knows the sequence set to 2, the user 8 changes the sequence set by the sequence recognition means 12 so that the user 8
Can be recovered from the situation in which writing to the flash memory 3 is prohibited.

Second Embodiment Next, a memory system according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing one configuration example of the memory system according to the second embodiment.

The memory system 1B shown in FIG. 2 includes a flash memory 3, an input terminal 4, and a flash memory control circuit 7B.

The flash memory 3 of the memory system 1B
Also, similarly to the flash memory 3 of the memory system 1A of FIG. 1, the write permission state is set by the write signal WS. The flash memory 3 of the memory system 1B has a memory reset function. Therefore, the write signal W is sent to the flash memory 3 of the memory system 1B.
Even if S is given, if a memory reset signal MR described later is input and memory reset is performed, the writing process is interrupted. When the memory reset signal MR is not input and the memory reset is released, the flash memory 3 of the memory system 1B returns to the normal state.

The flash memory control circuit 7B includes a hardware setting circuit 5, a write signal generation circuit 6, a sequence recognition means 12, and a memory reset signal generation circuit 13.

The operations of the hardware setting circuit 5 and the sequence recognizing means 12 of the memory system 1B are the same as the operations of the hardware setting circuit 5 and the sequence recognizing means 12 of the memory system 1A.

When the write mode signal WM is input from the hardware setting circuit 5, the write signal generating circuit 6 outputs the write signal WS to the flash memory 3.

The memory reset signal generating circuit 13 is supplied with a write mode signal WM from the hardware setting circuit 5 and a write enable signal SS from the sequence recognizing means 12. Memory reset signal generation circuit 13
Is the write mode signal W from the hardware setting circuit 5.
When M is input and the write enable signal SS is not input from the sequence recognizing means 12, the memory reset signal MR is output to the flash memory 3. As a result, a memory reset is performed on the flash memory 3.

On the other hand, the memory reset signal generation circuit 13
Is the write mode signal W from the hardware setting circuit 5.
When M is input and the write enable signal SS is input from the sequence recognition means 12, the memory reset signal MR is not generated. In this case, writing to the flash memory 3 is not interrupted.

When the write enable signal SS is input from the sequence recognizing means 12 but the write mode signal WM is not input from the hardware setting circuit 5, or the write mode signal WM is input from the hardware setting circuit 5. Not performed and sequence recognition means 1
2, the memory reset signal generation circuit 13 does not generate the memory reset signal MR.

As described above, according to the memory system 1B of the present embodiment, when the potential of the input terminal 4 is set to a predetermined state, the write signal generation circuit 6
S is generated, and the flash memory 3 enters the write-permitted state.
Is not input to the flash memory 3, the memory reset is performed, and the writing to the flash memory 3 is interrupted. Therefore, only a person who grasps the sequence information SI set in the sequence recognizing means 12 can perform writing to the flash memory 3, and can perform writing to the flash memory 3 only by setting the potential of the input terminal 4. Can not.

In the present embodiment, the write signal generating circuit 6 corresponds to a write signal generating means for generating a write signal when the first signal is generated, and the memory reset signal generating circuit 13 corresponds to the memory reset signal generating means. Is equivalent to

(Embodiment 3) Next, a memory system according to an embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing one configuration example of the memory system according to the third embodiment of the present invention.

The memory system 1 C shown in FIG. 3 is a processing system 2 that performs a predetermined process using the flash memory 3.
And a flash memory control circuit 7C for controlling the flash memory 3 and an input terminal 4. The processing system 2 is, for example, a billing system that calculates a price for receiving a satellite broadcast in a satellite broadcast system.

The flash memory 3 included in the processing system 2 of the memory system 1C is set in a write-permitted state by a write signal WS. The processing system 2 is reset together with the flash memory 3 by a system reset signal SR described later.

The flash memory control circuit 7C includes a hardware setting circuit 5, a write signal generation circuit 6, a sequence recognition means 12, and a system reset signal generation circuit 14.

The operations of the hardware setting circuit 5, the write signal generation circuit 6 and the sequence recognition means 12 of the flash memory control circuit 7C correspond to the hardware setting circuit 5, the write signal generation circuit of the flash memory control circuit 7B shown in FIG. 6 and the operation of the sequence recognition means 12.

The system reset signal generation circuit 14 includes:
The write mode signal WM is supplied from the hardware setting circuit 5, and the system reset signal SR is supplied from the sequence recognition means 12. The system reset signal generation circuit 14 sends the system reset signal SR to the processing system 2 when the write mode signal WM is input from the hardware setting circuit 5 in a state where the write enable signal SS is not input from the sequence recognition unit 12. Output. As a result, the processing system 2
Reset with

On the other hand, when the write mode signal WM is input from the hardware setting circuit 5 and the sequence recognition means 1
When the write enable signal SS is input from the second circuit 2, the system reset signal generation circuit 14 does not generate the system reset signal SR. In this case, writing to the flash memory 3 is not interrupted.

Note that the write mode signal WM is not input from the hardware setting circuit 5 and the sequence recognition means 12
When the write enable signal SS is not input from the
Is input, but the write mode signal WM is not input from the hardware setting circuit 5, the system reset signal generation circuit 14
Does not generate R.

As described above, according to the memory system 1C of the present embodiment, when the potential of the input terminal 4 is set to a predetermined state, the write signal generation circuit 6
S is generated, and the flash memory 3 enters the write-permitted state.
Is not input, the processing system 2 is reset together with the flash memory 3 and writing to the flash memory 3 is not performed. Therefore, when the potential of the input terminal 4 is set to a predetermined state and the sequence information SI is input to the sequence recognizing means 12, writing to the flash memory 3 becomes possible. As a result, only a person who understands the sequence set in the sequence recognizing means 12 can perform writing to the flash memory 3, and can perform writing to the flash memory 3 only by setting the potential of the input terminal 4. Can not.

(Embodiment 4) Next, a memory system according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration example of a memory system according to Embodiment 4 of the present invention.

The memory system 1D shown in FIG. 4 includes a flash memory 3, an input terminal 4, and a flash memory control circuit 7D.
And

The flash memory 3 of the memory system 1D
Are set in a write-permitted state by the write signal WS. However, in the flash memory 3, even when the write signal WS is input, writing is not performed when the write inhibit signal WP is input.

The flash memory control circuit 7D includes a hardware setting circuit 5, a write signal generation circuit 6, a sequence recognition means 12, and a write inhibition control circuit 16.

The operations of the hardware setting circuit 5, write signal generation circuit 6 and sequence recognition means 12 of the memory system 1D are performed by the hardware setting circuit 5, write signal generation circuit 6, and write signal generation circuit 6 of the flash memory control circuit 7B shown in FIG. The operation is the same as that of the sequence recognition means 12.

The write prohibition control circuit 16 receives the write mode signal WM from the hardware setting circuit 5 and the write permission signal SS
Is given. The write prohibition control circuit 16 outputs the write prohibition signal WP to the flash memory 3 when the write mode signal WM is input from the hardware setting circuit 5 in a state where the write permission signal SS is not input from the sequence recognition unit 12. . As a result, no writing is performed on the flash memory 3.

On the other hand, when the write mode signal WM is input from the hardware setting circuit 5 and the write enable signal SS is input from the sequence recognizing means 12, the write inhibit control circuit 16 Does not generate WP. This allows
Writing is performed on the flash memory 3.

Note that the write prohibition control circuit 16 determines whether the write mode signal WM has been input from the hardware setting circuit 5 and the write enable signal SS has not been input from the sequence recognition When the write enable signal SS is input from the hardware setting circuit 5 but the write mode signal WM is not input from the hardware setting circuit 5,
Does not generate the write inhibit signal WP.

As described above, according to the memory system 1D of the present embodiment, when the potential of the input terminal 4 is set to a predetermined state, the write signal generating circuit 6 outputs the write signal WS to the flash memory 3. However, if the sequence information SI has not been input to the sequence recognizing means 12, the write prohibition control circuit 16 prohibits writing to the flash memory 3. Therefore, when the potential of the input terminal 4 is set to a predetermined state and the sequence information SI is input to the sequence recognizing means 12, writing to the flash memory 3 becomes possible. As a result, only a person who grasps the sequence information SI set in the sequence recognizing means 12 can perform writing to the flash memory 3, and performs writing to the flash memory 3 only by setting the potential of the input terminal 4. Can not do.

In this embodiment, the write inhibit control circuit 16 corresponds to a write inhibit signal generating means.

(Fifth Embodiment) Next, a memory system according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing one configuration example of the memory system according to the fifth embodiment of the present invention.

A memory system 1E shown in FIG. 5 includes a processing system 2 for performing predetermined processing using a built-in flash memory 3, an input terminal 4, and a flash memory control circuit 7E.
And

The flash memory 3 of the processing system 2
The write permission state is set by the write signal WS. However, even if the write signal WS is input to the flash memory 3, if the processing system 2 is reset by inputting a system reset signal SR to be described later, the flash memory 3 is reset together with the entire processing system 2. Since the reset of the memory 3 is performed, the writing of data to the flash memory 3 is interrupted.

The flash memory control circuit 7 E includes a hardware setting circuit 5, a write signal generation circuit 6, and coupling means 17. Hardware setting circuit 5 and write signal generation circuit 6 of flash memory control circuit 7E
Is performed by the hardware setting circuit 5 and the write signal generation circuit 6 of the flash memory control circuit 7A shown in FIG.
The operation is the same as that described above.

The coupling means 17 includes the write signal generation circuit 6
Is generated by the system reset signal S
R is input to the system reset terminal of the processing system 2. For example, the coupling means 17 includes the write signal generation circuit 6
Is a wiring that couples a signal line for transmitting the write signal WS output by the system reset terminal of the processing system 2.

The coupling between the signal line of the write signal WS and the system reset terminal of the processing system 2 by the coupling means 17 is performed after predetermined data is written in the flash memory 3. For example, in the manufacturing process of the memory system 1 E, After writing data to the flash memory 3,
This is performed before storing the memory system 1E in the housing.

As described above, according to the memory system 1E of the present embodiment, the write signal W
After the S signal line is coupled to the system reset terminal of the processing system 2, the write signal WS output from the write signal generating circuit 6 is output even if the potential of the input terminal 4 is set to a predetermined state. , The processing system 2 is reset together with the flash memory 3. Therefore, a third party cannot write to the flash memory 3 unless the coupling by the coupling unit 17 is released.

In this embodiment, the coupling means 17 corresponds to a system reset signal providing means.

[0076]

According to the memory system of the present invention, it is possible to write to the memory only when the signal of the input terminal is in a predetermined state and the preset sequence information is input, and the signal of the input terminal is It is possible to prevent writing into the memory only in the predetermined state. As a result, a third party cannot easily write to the memory except for a person who knows the preset sequence information.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a memory system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a memory system according to a second embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration example of a memory system according to a third embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration example of a memory system according to a fourth embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration example of a memory system according to a fifth embodiment of the present invention;

FIG. 6 is a block diagram showing one configuration example of a conventional memory system.

FIG. 7 is a conceptual diagram showing an example of use of a memory system.

[Explanation of symbols]

 1, 1A to 1E Memory system 2 Processing system 3 Flash memory 4 Input terminal 5 Hardware setting circuit 6, 6A Write signal generation circuit 7, 7A to 7E Flash memory control circuit 12 Sequence recognition means 13 Memory reset signal generation circuit 14 System reset Signal generation circuit 16 Write inhibit control circuit 17 Coupling means

Claims (7)

[Claims] A memory; an input terminal for receiving a predetermined signal; a first signal generating means for generating a first signal when the signal of the input terminal is in a predetermined state; and a preset sequence. Second when given information
A second signal generating means for generating a signal of the following type; and a signal to the memory based on a first signal generated by the first signal generating means and a second signal generated by the second signal generating means. A memory system, comprising: write control means for controlling data writing. 2. The memory system according to claim 1, wherein said second signal generation means includes an arithmetic processing unit which executes a program for determining whether or not said sequence information has been given. 3. The writing control means stores data in the memory when a first signal is generated by the first signal generation means and a second signal is generated by the second signal generation means. 3. The memory system according to claim 1, further comprising a write signal generating means for generating a write signal allowing writing of the data. 4. The write control unit includes: a write signal generation unit configured to generate a write signal that allows data to be written to the memory when the first signal generation unit generates a first signal; A memory for generating a memory reset signal for interrupting writing to the memory when a first signal is generated by the first signal generating means and a second signal is not generated by the second signal generating means 3. The memory system according to claim 1, further comprising reset signal generation means. 5. A processing system for performing a predetermined process using the memory, wherein the write control unit stores data in the memory when a first signal is generated by the first signal generation unit. Write signal generating means for generating a write signal permitting writing; and the processing when the first signal is generated by the first signal generating means and the second signal is not generated by the second signal generating means. 3. The memory system according to claim 1, further comprising: a system reset signal generating unit configured to generate a system reset signal for resetting a system together with the memory. 6. The write control unit includes: a write signal generation unit configured to generate a write signal for permitting data to be written to the memory when a first signal is generated by the first signal generation unit; When the first signal is generated by the first signal generating means and the second signal is not generated by the second signal generating means, writing of data to the memory is inhibited regardless of the write signal. 3. The memory system according to claim 1, further comprising: a write inhibit signal generating unit that generates a write inhibit signal. 7. A memory, an input terminal for receiving a predetermined signal, and write signal generating means for generating a write signal for permitting writing of data to the memory when the signal of the input terminal is in a predetermined state; A processing system that performs a predetermined process using the memory; and a system reset that can be set to give a write signal generated by the write signal generation unit to the processing system as a system reset signal that resets the processing system together with the memory. A memory system comprising: a signal providing unit.