JP2000339217A - Cache memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cope with a program part with high locality of data reference and to simultaneously save power consumption of a cache memory when it is not used. SOLUTION: A virtual address of data is transmitted to a judging part 13 when the data to be requested by an instruction in a program is fetched in an executing part 15 by a control part 11. The data is judged whether it exist either in a line buffer 2 or in the cache memory 3 based on the virtual address, when the data exists either in the line buffer 2 or the cache memory 3, the data is taken out from the memory in which the data exists, when the data exists neither in the line buffer 2 nor the cache memory 3, the data is taken out from an external storage means, stored in the cache memory 3 and transmitted to the executing part 15 as well by the judging part 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system, and more particularly to a cache memory system which is provided with a high-speed line buffer between a CPU core and a cache memory so as to cope with a program portion having high locality of data reference. The present invention relates to a power-saving cache memory system capable of saving unnecessary power consumption when a memory is not used.

[0002]

2. Description of the Related Art Conventionally, an information processing apparatus represented by a computer uses a large storage device as a means for assisting a physically limited core memory space, thereby obtaining a large virtual address space. Logically expands the memory space.

[0003] In the above-mentioned expanded memory space, a hierarchical structure of storage is usually constructed from indices such as the capacity and access speed of a memory device constituting the expanded memory space.

At the top of the hierarchical structure, there are registers installed in the CPU core. A cache memory system is generally adopted as a system for reducing a speed difference between the registers and the core memory. ing.

[0005] The operating principle of many hierarchical storage systems, not limited to cache memories, is the statistical locality of data references. This is, strictly speaking, the temporal locality of the data reference, a principle known as a rule of thumb.
On the other hand, the storage device has indices such as capacity and access speed, and thus, a hierarchical storage space is usually constructed. Therefore, it can be said that the role of the cache memory system is to rationally reflect the temporal locality of the data reference described above on the data arrangement of a partial hierarchy in the hierarchical storage space.

FIG. 3 is a block diagram showing a main part of a conventional direct mapped cache memory system.

The cache memory system shown in FIG.
When the processor including the CPU core 31 and the cache memory 33 executes an instruction which has been decoded or is in the process of being decoded by the processor including the cache memory system, the control unit 311 accesses the data necessary for executing the instruction. Address in the address bus (AB)
31).

As a result of accessing the cache memory 33 using the transmitted address in the cache, if the cache memory 33 contains data necessary for the execution of the instruction (at the time of HIT), Data
The data is sent to the execution unit 315 via the data bus (DB31).

The execution unit 315 executes the operation of the instruction using the transmitted data. (Note that the connection line between the control unit 311 and the execution unit 315 is not shown.) However, if there is no data required to execute the above instruction in the cache memory 33 (at the time of a miss HIT), The data is fetched from an external main storage device (not shown), and the cache memory is updated accordingly.

In a general cache memory system, a high-speed address translation unit called a TLB (high-speed translation buffering mechanism) is often used as a unit for selecting an entry of a cache memory from a virtual address.
Further, when converting the above-mentioned virtual address to the final physical address, other address conversion means covering the above-mentioned TLB may be installed.

The TLB is usually composed of a memory or a register faster than a cache memory, and achieves the above-mentioned means for converting a virtual address into a physical address by means of a table lookup means. By the way, conventional TL
In B, usually, only a translation pair from a virtual address to a physical address is placed, and the corresponding data is not stored.

Japanese Patent Application Laid-Open No. 4-338848 discloses the above TLB-related technology.

Incidentally, it can be pointed out that many of the applications related to the conventional cache memory system were summarized in a so-called cache memory replacement algorithm as disclosed in Japanese Patent Application Laid-Open Nos. 6-348595 and 7-28706. Like.

[0014]

The problem with the conventional cache memory system is that, at the time of instruction execution, even if the data area in the cache memory is unnecessary for the execution of the program at hand, the power supply is always on. Had been supplied.

More specifically, many programs include at least a portion where the locality of data reference is extremely high. To cope with such a tendency,
A method in which a high-speed buffer having a small capacity (the conventional TLB level described above) is installed and used as a data buffer is originally effective, and therefore, the use of the conventional large-scale cache memory is not necessarily required. May not be necessary.

Therefore, in devising the present invention, a high-speed buffer having a small capacity is used instead of the conventional cache memory for executing a portion having high locality of data reference in a program. It has been considered that the memory cells in the data area of the cache memory should be kept in an inactive state to save power consumption of the processor and to suppress heat generation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the conventional cache memory system, and addresses a program portion having high locality of data reference. It is an object of the present invention to provide a power-saving cache memory system capable of saving power consumption.

[0018]

According to an aspect of the present invention, to solve the above-mentioned problems, each instruction in a program to be executed by an information processing apparatus is sequentially analyzed, and each instruction is analyzed according to the analysis result. A cache memory having a standby function for forming a component of a virtual address space, storing a part of data of a data group necessary for execution of each instruction, In a cache memory system having a line buffer provided between a core and the cache memory for storing a part of data of a data group stored in the cache memory and an external storage unit, an instruction in the program requires When the data is processed by the execution means in the CPU core, the data is transferred to the line buffer and the key based on the virtual address of the data. And if the data exists in either the line buffer or the cache memory, the memory in which the data exists is determined. Fetching the corresponding data from the external buffer, and fetching the corresponding data from the external storage means if the data does not exist in any of the line buffer and the cache memory, and sending the fetched data to the execution means. A cache memory system is provided.

Here, in the CPU core, an instruction necessary for execution of the instruction is instructed to other components according to a result of analysis of the instruction in the program, and data required by the execution instruction is provided. Control means for sending out the virtual address of, and whether or not the data is present in the line buffer is determined based on the sent virtual address, and it is determined that the data is present in the line buffer. The address in the line buffer is configured based on the virtual address, data corresponding to the configured address in the line buffer is extracted from the line buffer and sent to the execution unit, and a standby instruction signal is transmitted. Placing the cache memory in a standby state, however, if it is determined that the data is not in the line buffer, The standby instruction signal is released, and all data or updated data in the line buffer is returned to the cache memory. Thereafter, data corresponding to an address in the cache memory configured based on the virtual address is stored in the cache memory. If the data can be retrieved from the memory, the data or the data stored in the vicinity of the data in addition to the data is retrieved, the retrieved data is sent to the line buffer, and the same as the retrieved data is transmitted. Is also sent to the execution means, however, when the data does not exist in the cache memory, the data is fetched from the external storage device, and the fetched data is stored in the cache memory, A case near the stored data or the data in addition to the data The data being sent to the line buffer, furthermore, it is possible to include a determination unit also sends the same data as the data stored in the cache memory to the output means.

Further, the cache memory can be a cache memory (n-way set associative cache memory) having a configuration divided into a plurality of ways.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an overall configuration of a cache memory system according to an embodiment of the present invention.

C included in a processor (not shown)
The PU core 1 issues a command to each unit in accordance with the decoding result of the execution instruction, and sends a virtual address included in the execution instruction to the determination unit 13 via the address bus (AB1). By analyzing the virtual address to determine the location where the data corresponding to the virtual address exists, read the data, and if necessary, put the cache memory in a standby state; An execution unit 15 that performs processing as instructed by the execution instruction is provided.

(In the above configuration, the illustration of the connection lines between the control unit 11 and the execution unit 15 and the description of the relationship between them are omitted because they are not essential to the present invention.) The line buffer 2 has a small capacity. It is composed of a high-speed memory, and temporarily stores data to be referred to by a program part having high locality.

The cache memory 3 is a direct-mapped cache memory with a standby function (standby function), and stores frequently referenced data in the line buffer 2.
Is stored including the data held by.

When the judging section 13 judges that the data exists in the line buffer 2, it sends an address in the line buffer 2 constructed based on the virtual address to the address bus (AB2), and The data in the line buffer 2 is fetched using the address in the buffer, the fetched data is sent to the execution unit 15 via the data bus (DB1), and the standby control signal (SCS) is sent to the execution unit 15. To put the cache memory 3 in a standby state.

However, when the determination unit 13 determines that the data does not exist in the line buffer 2,
The standby control signal (SCS) is released, and all data or only updated data in the line buffer is returned to the cache memory 3 via the data bus (DB3). After that, the address in the cache memory 3 configured based on the virtual address is transmitted to the address bus (AB3), and the corresponding data is extracted from the cache memory 3 using the address in the cache memory 3. , The extracted data is transferred to a data bus (DB
The data is transmitted to the line buffer via 2), and the same data as the transmitted data is transmitted to the execution unit 15 via the data bus (DB1).

However, when the data does not exist in the cache memory 3, the data is fetched from an external storage device (not shown) and stored in the cache memory 3, the line buffer 2, and the execution unit 15.

When the line buffer 2 has missed HIT, it is also possible to take in only the missed HIT data into the line buffer 2 or to store data in the cache memory 3 near the missed HIT data. It is also possible to take in data located in the line buffer 2 up to the capacity of the line buffer 2.

FIG. 2 is a flowchart for explaining the operation of the cache memory system according to the embodiment of the present invention.

Hereinafter, the operation of the cache memory system according to this embodiment will be described with reference to FIG. 1 and the flowchart shown in FIG.

First, in step S1, the judgment unit 13
It is determined whether or not data corresponding to the virtual address passed from the control unit 11 exists in the line buffer 2.

If it is determined that the data exists in the line buffer 2, the process proceeds to step S2 where
Issues a standby control signal (SCS) to put the cache memory 3 in a standby state.

Next, in step S3, the determination unit 13 sends the address of the data to the line buffer 2, fetches the corresponding data from the line buffer 2, and
To send to.

Finally, in step S4, the execution unit 15 executes an instruction based on the transmitted data.

If it is determined in step S1 that the data does not exist in the line buffer 2, the control unit 13 cancels the standby state of the cache memory 3 in step S5.

Next, at step S6, the control unit 13
A part or all of the contents of the line buffer 2 is written back to the cache memory 3.

Next, at step S7, after the data or the data corresponding to the capacity of the line buffer 2 near the data including the data is taken into the line buffer 2 from the cache memory 3, the flow of control is shifted to step S4.

In the above operation flow, the operation of the control unit 11, the operation when the cache memory 3 has missed HIT, and the transmission of the data to the execution unit 15 after the data is fetched into the line buffer 2 are described. The description of the operation is omitted.

In the above embodiment, the cache memory 3
Is further divided by a cache memory (n-way set associative cache memory) having a configuration divided into a plurality of ways.

[0041]

As described above, according to the cache memory system of the present invention, a small-capacity and high-speed storage is provided in a memory hierarchy higher than the cache memory in order to deal with a program portion having high locality of data reference. By installing the line buffer, it is possible to further improve the data access speed required for the instruction execution as compared with the conventional system.

Further, unnecessary power consumption can be suppressed by using only the standby power as the power consumption of the cache memory while the data hit in the line buffer continues. Theoretically, cache capacity 8
Under the condition of K bytes and a line buffer capacity of 1 Kbyte, about 30% of power is saved.

Further effects are expected when applied to a cache memory (n-way set associative cache memory) having a configuration divided into a plurality of ways.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a cache memory system according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining an operation of the cache memory system according to the embodiment of the present invention;

FIG. 3 is a block diagram showing a main part of a conventional direct mapped cache memory system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU core 2 Line buffer 3 Cache memory 11 Control part 13 Judgment part 15 Execution part AB1, AB2, AB3 Address bus DB1, DB2, DB3 Data bus SCS Standby control signal

Claims (3)

[Claims] 1. A CPU core for sequentially analyzing each instruction in a program to be executed by an information processing apparatus and performing a process according to the analysis result, and the CPU core constituting one element of a virtual address space. And a cache memory with a standby function for storing a part of data of a data group necessary for execution of, and a part of a data group which is installed between the CPU core and the cache memory and stored by the cache memory A cache memory system having a line buffer for storing the data of
Upon execution by the execution means in the core, based on the virtual address of the data, determines whether the data exists in the line buffer or the cache memory, or does not exist in any, If the data is present in either the line buffer or the cache memory, retrieve the relevant data from the memory in which the data is present, and do not exist in either the line buffer or the cache memory. In such a case, the cache memory system retrieves the relevant data from the external storage unit and sends the retrieved data to the execution unit. 2. In the CPU core, an instruction necessary for execution of the instruction is instructed to other components according to an analysis result of the instruction in the program, and data of the data requested by the execution instruction is provided. Control means for transmitting a virtual address; determining whether or not the data is present in the line buffer based on the transmitted virtual address; and determining that the data is present in the line buffer. Constructs an address in the line buffer based on the virtual address, retrieves data corresponding to the constructed address in the line buffer from the line buffer and sends it to the execution means, and transmits a standby instruction signal to transmit the standby instruction signal. Put the cache memory in a standby state; however, if it is determined that the data does not exist in the line buffer, While releasing the instruction signal, all data or updated data in the line buffer is returned to the cache memory, and then data corresponding to an address in the cache memory configured based on the virtual address is transferred from the cache memory. If the data can be extracted, the data or the data stored in the vicinity of the data in addition to the data is extracted, the extracted data is sent to the line buffer, and the same data as the extracted data is sent out. Is also sent to the execution means,
However, when the data does not exist in the cache memory, the data is fetched from the external storage device, the fetched data is stored in the cache memory, and the stored data or the data is additionally stored. And determining means for transmitting data stored near the data to the line buffer and transmitting the same data as the data stored in the cache memory to the output means. The cache memory system according to claim 1, wherein 3. The cache memory system according to claim 1, wherein the cache memory is a cache memory (n-way set associative cache memory) having a configuration divided into a plurality of ways. .