JP2000339213A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the quantity of hardware and to shorten time required for operation verification by installing judgement means judging the size relation of a count value and plural given setting values and outputting a control signal and a parameter register storing the respective setting values of the judgment means. SOLUTION: A counter 3 starting counting in accordance with the transfer request signal of a data processing means 1 is installed. Judgment means 20 to 24 outputting a first control signal showing that the value of the counter 3 is larger than the setting value '1' and the value of the counter 3 is not more than the setting value '2' and a second control signal showing that the value of the counter is equal to a setting value '3' and a timing parameter register 2 storing the setting values of the judgment means 20 to 24 are installed. The respective setting values of the judgment means 20 to 24 are appropriately set in accordance with the respective devices of a static random access memory(SRAM) and a dynamic random access memory(DRAM).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to data transfer, and more particularly to an apparatus for performing data transfer with an external device.

[0002]

2. Description of the Related Art In recent years, microcomputers have been used in various systems, and there is a demand for being directly connectable to various other external devices. External devices that require direct connection to a microcomputer often require external control signals for proper operation of these devices when accessed by the microcomputer. For example, a static random access memory (SRAM) requires chip enable, output enable and write enable control signals to control read / write access, and a dynamic random access memory (DRAM) requires a row address strobe and a column address strobe. , Output enable and write byte enable. In a device that accesses by multiplexing addresses and data in a time-division manner (hereinafter referred to as an address data multiplex device), in addition to the above-described control signals of the chip enable, the output enable, and the write enable, the address and the data are written. The need for multiplexing arises. Further, in a device that performs a handshake access using a data acknowledge signal (hereinafter referred to as a handshake device), in addition to the above-described control signals of chip enable, output enable, and write enable, the completion of access is controlled by a data acknowledge signal. You have to wait.

As described above, SRAMs and DRAMs, address data multiplex devices, and handshake devices differ in the types of external control signals required for their proper operation. The access method is also different.

Normally, in order to cope with different external devices as described above, the microcomputer side incorporates an interface circuit for each external device and performs data transfer by operating the corresponding interface circuit in response to access from the corresponding external device. I was Further, when the timing of the control signal is different, there is a data processor that dynamically controls the access timing relationship and corresponds to the different access timing.

As an example of the above-mentioned conventional data processor, a control register for dynamically controlling the timing relationship for read and write access to an external device is provided, and a first set of bits PA of the control register is an external device. There are ways to provide timing control for the amount of initial time needed to read a first data value from a device. For example, see JP-A-9-167148.

[0006]

However, in the configuration in which the interface circuit is built in each external device as described above, it is necessary to build the interface circuit in all the external devices required to be directly connected.
There was a problem that the amount of hardware required for data transfer on the microcomputer side increased. Furthermore, since it is necessary to perform operation verification for each interface circuit, there is a problem that it takes time to test interface state transitions.

On the other hand, Japanese Patent Application Laid-Open No. 9-167148 discloses a data transfer with an external device using a control register (FIG. 4) for dynamically controlling the timing relationship for read and write access to the external device. Although a part of a system integrated circuit (FIG. 3) for performing the above operation is disclosed, in such a configuration, the control circuit controls all external control signals related to data transfer, so that the circuit becomes complicated, and the operation verification is performed. It takes a long time.

Therefore, the present invention is obtained by newly focusing on the point that all timings relating to data transfer can be independently set, and providing a control circuit having the same function for each control signal.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to flexibly respond to the timing required by an external device in data transfer with the external device, to reduce the amount of hardware, and to perform operation verification. It is an object of the present invention to provide a semiconductor device capable of reducing the time required.

[0010]

In order to solve the above problems, a semiconductor device according to the present invention operates in response to a clock.
Data processing means for processing data in accordance with an instruction, control means for holding a request signal of the data processing means and outputting a control signal indicating a type of requested access, and starting operation by the request signal of the data processing means A counter; determining means for determining a magnitude relationship between a value of the counter and a given set value; and outputting a control signal; setting value storing means for storing a plurality of set values to be provided to the determining means; A control signal generating means for generating a control signal for an external device based on an output of the means, and a bus means serving as an address and data transfer path between the external device in accordance with the control signal output from the determining means. It is provided with.

Here, the determining means includes a first control signal indicating that the value of the counter is larger than a set value 1 and a value of the counter being equal to or less than a set value 2 and a value of the counter being set value 3 And outputting a second control signal indicating that this is the case.

Alternatively, the bus means may output one of a row address for DRAM access generated in response to an address output from the data processing means and an address output from the data processing means to an output of the determination means. Address selecting means for selecting based on the

Alternatively, the bus means includes an address selection means for selecting one of an address output from the data processing means and data output from the data processing means based on an output from the determination means; Address output control means for controlling the output of the address output selection means to be output to an address bus based on the output of the data output means, and data to select one of an address bus input and a data bus input and to output to the data processing means. Input selection means.

Data processing means which operates in response to a clock and processes data in accordance with an instruction; control means for holding a request signal of the data processing means and outputting a control signal indicating a type of requested access; Signal storage means for storing a data acknowledge signal output from an external device, a counter which starts operation by a request signal of the data processing means, and stops operation only when a stop signal is asserted; Determining means for determining a magnitude relationship between a plurality of given set values and outputting a control signal; setting value storing means for storing a plurality of set values to be provided to the determining means; A control signal generating means for generating a control signal for the device, and an address between an external device according to the control signal output from the determining means. And bus means for the transfer path of the fine data, is characterized in that a stop signal generating means for generating a stop signal of the counter from the output of said signal storage means and said determining means.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes data processing means for outputting a read / write request signal, an address, write data, a byte enable, and the like in response to a requested address. Reference numeral 2 denotes a parameter register that can be written by the data processing unit 1, and constitutes a set value storage unit that stores three set values input to the determination units 20 to 24, respectively. Reference numeral 3 denotes a counter which starts counting upon receiving a read / write request signal from the data processing means 1. Reference numeral 4 denotes a row address generation unit that receives the address output of the data processing unit 1 and generates a row address for accessing the DRAM. Reference numeral 5 denotes an address selecting means for selecting one of the address output of the data processing means 1 and the output of the row address generating means 4. Reference numeral 6 denotes an address register for storing the output of the address selecting means 5. Reference numeral 7 denotes a write data register for storing the write data output from the data processing means 1. 8
Is a tristate that controls output of the value of the write data register 7 to the data bus. 9 is a read data register for taking the value of the data bus into the semiconductor device. The row address generating means 4, the address selecting means 5, the address register 6, the write data register 7, the tristate 8, and the read data register 9 constitute a bus means. Reference numeral 10 denotes a first signal indicating an access period (either read / write), a first signal indicating a read access period, receiving a read / write request signal of the data processing unit 1 and an output of the determination unit 23. 2 is a status register that outputs a second signal and a third signal indicating that the period is a write access period, and constitutes control means. Reference numerals 20 to 24 denote a first control signal indicating that the value of the counter 3 is smaller than the set value 1 and a second control signal indicating that the value of the counter 3 is equal to the set value 3. The setting values 1, 2, and 3 used by the respective judging means are stored in the parameter register 2 for each judging means. Reference numeral 30 denotes a logic circuit that asserts an active signal to the terminal 1 only when both the first control signal of the determination means 20 and the first signal of the status register are asserted. Reference numeral 31 asserts an active signal to the terminal 2 only when the first control signal of the judging means 21, the third signal of the status register, and the three upper byte enable signals output by the data processing means 1 are both asserted. Logic circuit. 32 asserts an active signal to the terminal 3 only when the first control signal of the judging means 21, the third signal of the status register, and the three lower byte enable signals output by the data processing means 1 are both asserted. Logic circuit. 33
Is a logic circuit that asserts an active signal to the terminal 4 only when both the first control signal of the determination means 22 and the first signal of the status register are asserted. 34
Is a logic circuit that asserts an active signal when the read / write request signal of the data processing means 1 is asserted or the second control signal of the judging means 23 is asserted. Reference numeral 35 denotes a logic circuit that asserts an active signal to the terminal 5 only when both the first control signal of the determination unit 24 and the second signal of the status register are asserted. Reference numeral 36 denotes a logic circuit that asserts an active signal when the first control signal is asserted from the determination unit 23 or the second control signal is asserted.

The logic circuits 30 to 36 constitute control signal generation means.

The operation of the semiconductor device configured as described above will be described below with reference to FIGS. 1, 2 and 3.

FIG. 2 shows an example of an access timing diagram of the SRAM. The access timing of the SRAM is determined by the parameters CSS, CSE, R shown in FIG.
It is defined by ES, REE, WES, and WEE. In contrast to such an SRAM, the semiconductor device of FIG.
S, terminal 2 is WE1, terminal 3 is WE0, terminal 5 is R
E, the address is connected to the address bus, and the data is connected to the data bus. The parameter register 2 stores the respective set values of the determination means 20 to 24 from the data processing means 1 via the register write bus in the following Table 1.
Is given as Note that since the terminal 4 is not used, the set value of the determination means 22 is “not yet set” indicating that the terminal 4 has not been set.

[0020]

[Table 1]

At t0 in FIG. 2, when a read request signal is asserted from the data processing means 1, the status register 1
0 asserts the first signal and the second signal. Since the counter 3 has an initial value 0 and the second control signal of the judging means 23 is asserted, the address selecting means 5
6, an address output from the data processing means 1 is selected and output to the address register 6. The address register 6 uses the output of the logic circuit 34 as an update enable signal. The set value 1 of the judgment means 20 is 0 and the set value 2 is CS
E: Since the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie, CS. Similarly, terminals 2, 3, 5
No active signal is asserted. Next, FIG.
At t1, since the update enable was asserted in the previous cycle t0, the address register 6 is updated, and the address selected by the address selection means at t0 is output to the address bus. On the other hand, the counter 3 starts counting in response to a read request signal from the data processing means 1, so that the counter value becomes 1. As a result, the first control signal of the judging means 20 is asserted.
Is asserted. Next, at t2 in FIG. 2, the value of the counter 3 becomes 2, so that the first control signal of the determination means 24 is asserted. Since the second signal is asserted from the status register to the logic circuit 35, the terminal 5, ie, the RE signal of the SRAM, is asserted. At t3 in FIG. 2, the counter value becomes 3, but does not affect each terminal. At t4 in FIG. 2, the counter value becomes 4, and the third control signal of the determination unit 24 is asserted.
Since the third control signal enables the read data register 9 to be updated, the read data register 9 stores the data output to the data bus by the SRAM at t4 internally at t5 and outputs the data to the data processing means 1 at t5. I do. At t5 in FIG. 2, since the counter value becomes 5, the first control signal of the judging means 24 is negated, so that the terminal 5, ie, RE, is negated. Further, since the third control signal of the judging means 20 is asserted, the counter 3 is reset at t6 of the next cycle, and the read data transfer ends.

Next, at t7 in FIG. 2, when the write request signal is asserted from the data processing means 1, the status register 10 asserts the first signal and the third signal. Since the counter 3 has an initial value 0 and the second control signal of the judging means 23 is asserted, the address selecting means 5 selects an address output from the data processing means 1 based on the output of the logic circuit 36, and 6 is output. The address register 6 uses the output of the logic circuit 34 as an update enable signal. The set value 1 of the judgment means 20 is 0 and the set value 2 is CS
E: Since the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie, CS. Similarly, terminals 2, 3, 5
No active signal is asserted. Next, FIG.
At t8, since the update enable was asserted at the previous cycle t7, the address register 6 is updated, and the address selected by the address selecting means at t7 is output to the address bus. On the other hand, the counter 3 starts counting in response to the write request signal from the data processing means 1, so that the counter value becomes 1. As a result, the first control signal of the judging means 20 is asserted, so that an active signal is asserted at the terminal 1, that is, the CS terminal of the SRAM. Further, the third control signal of the judging means 21 is asserted and becomes an update enable signal for the write data register. Next, at t9 in FIG. 2, since the value of the counter 3 becomes 2, the judgment means 2
One first control signal is asserted. Logic circuit 31,
Since the third signal is asserted from the status register to the terminals 32 and 32, the terminals WE0 and WE1 of the SRAM, that is, the terminals WE0 and WE1 according to the upper and lower values of the byte enable.
The signal is asserted. Since the update enable of the write data register was asserted in the previous cycle t8, the write data register 7 is updated to store the output data of the data processing means. The assertion of the first control signal of the judging means 21 turns on the tristate 8, and outputs the value of the write data register 7 to the data bus. At t10 in FIG. 2, the counter value becomes 3, but does not affect each terminal. At t11 in FIG. 2, the counter value becomes 4, and the first control signal of the determination means 21 is negated.
The WE0 signal is negated. In addition, the tristate 8 is turned off accordingly, so that no data is output to the data bus. At t12 in FIG. 2, the counter value is 5
Since the third control signal of the judging means 20 is asserted, the counter 3 is reset at t13 of the next cycle, and the write data transfer ends.

FIG. 3 shows an example of an access timing diagram of the DRAM. The access timing of the DRAM is determined by the parameters AC, RASS, R shown in FIG.
ASE, CASS, CASE, OES, OEE, WE
S, WEE. For such a DRAM, the semiconductor device of FIG. 1 has terminal 1 at RAS and terminal 2 at W
At E1, terminal 3 is connected to WE0, terminal 4 is connected to CAS, terminal 5 is connected to OE, address is connected to the address bus, and data is connected to the data bus. The parameter register 2 is given the respective set values of the judging means 20 to 24 from the data processing means 1 via the register writing bus as shown in Table 2 below.

[0024]

[Table 2]

At t0 in FIG. 3, when the read request signal is asserted from the data processing means 1, the status register 2
Asserts a first signal and a second signal. Counter 3
Is an initial value 0, and the judging means 23 does not assert either control signal. Therefore, the address selecting means 5 selects an address output from the row address generating means 4 and outputs it to the address register 6. The address register 6 uses the output of the logic circuit 34 as an update enable signal. Judgment means 20
Since the set value 1 is RAS, the set value 2 is RASE, and the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie, RAS. Similarly, no active signal is asserted at terminals 2, 3, 4, and 5. Next, t1 in FIG.
Since the update enable is asserted in the previous cycle t0, the address register 6 is updated, and the address selected by the address selecting means at t0 is output to the address bus. On the other hand, the counter 3 starts counting in response to the read request signal from the data processing means 1, so that the counter value becomes 1, but does not affect the terminals 1, 2, 3, and 4. Next, at t2 in FIG. 3, the value of the counter 3 becomes 2. As a result, the first control signal of the judging means 20 is asserted, so that the terminal 1, ie, the RAS signal of the DRAM, is asserted. At t3 in FIG. 3, the counter value becomes 3. For this reason, the third control signal of the determination unit 23 is asserted,
It becomes an update enable signal for the address register. Also,
Since the first control signal of the determination means 23 is asserted,
The address selection means 5 selects an address output from the data processing means and outputs it to an address register. T4 in FIG.
Since the address update enable was asserted in the previous cycle t3, the address register 6 was updated to t3
The address selected by the address selection means is output to the address bus. Although the counter value is 4, it does not affect the terminals 1, 2, 3, 4, and 5. T5 in FIG.
Then, the counter value becomes 5, the first control signal of the determination means 22 is asserted, and the
The S signal is asserted. Further, since the first control signal of the judging means 24 is asserted and the second signal is asserted from the status register to the logic circuit 35, the terminal 5, ie, the OE signal of the DRAM, is asserted. FIG.
At t6, the counter value becomes 6, and the first control signal of the determination means 20 is negated.
The RAS signal of the RAM is negated. Further, the third control signal of the determination means 22 is asserted. Since the third control signal enables the read data register 9 to be updated, the read data register 9 stores the data output from the DRAM to the data bus at t5 and outputs the data to the data processing means 1 at t6. I do. Further, since the third control signal of the judging means 20 is asserted, the counter 3 is reset at t7 of the next cycle, and the read data transfer ends.

Next, at t8 in FIG. 3, when the write request signal is asserted from the data processing means 1, the status register 10 asserts the first signal and the third signal. Since the counter 3 has an initial value of 0 and the judging means 23 does not assert either control signal, the address selecting means 5 selects an address output from the row address generating means 4 and outputs it to the address register 6. The address register 6 uses the output of the logic circuit 34 as an update enable signal. Since the set value 1 of the determination means 20 is RAS, the set value 2 is RASE, and the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie, RAS. Similarly, no active signal is asserted at terminals 2, 3, 4, and 5. Next, at t9 in FIG. 3, since the update enable is asserted in the previous cycle t8, the address register 6 is updated, and at t8, the address selected by the address selecting means is output to the address bus. On the other hand, the counter 3 starts counting in response to the write request signal from the data processing means 1, so that the counter value becomes 1, but does not affect the terminals 1, 2, 3, and 4.
Next, at t10 in FIG. 3, the value of the counter 3 becomes 2. As a result, the first control signal of the judging means 20 is asserted, so that the terminal 1, ie, the RAS signal of the DRAM, is asserted. At t11 in FIG. 3, the counter value becomes 3. Therefore, the third control signal of the judging means 23 is asserted and becomes an update enable signal for the address register. Further, since the first control signal of the judging means 23 is asserted, the address selecting means 5 selects an address output from the data processing means and outputs it to the address register.
Further, the third control signal of the determination means 21 is asserted,
This becomes an update enable signal for the write data register. At t12 in FIG. 3, the value of the counter 3 becomes 4, and the first control signal of the determination means 21 is asserted. Logic circuit 3
Since the third signal is asserted from the status register to the terminals 1 and 32, the terminals 2 and 3, ie, WE0 and W of the DRAM, are set in accordance with the upper and lower values of the byte enable.
The E1 signal is asserted. Since the update enable of the write data register was asserted in the previous cycle t11, the write data register 7 is updated to store the output data of the data processing means. The tri-state 8 is turned on by the assertion of the first control signal of the judging means 21.
And the value of the write data register 7 is output to the data bus. At t13 in FIG. 3, the value of the counter 3 becomes 5, the first control signal of the determination means 22 is asserted, and the terminal 4, ie, the CAS signal of the DRAM, is asserted.
At t14 in FIG. 3, since the third control signal of the determination means 20 is asserted, the counter 3 is reset at t15 in the next cycle, and the write data transfer ends.

As described above, according to the present embodiment, the counter 3 which starts counting in accordance with the transfer request signal of the data processing means 1, the value of the counter 3 is larger than the set value 1 and the value of the counter 3 is the set value A plurality of determination means for outputting a first control signal indicating that the value is equal to or less than 2 and a second control signal indicating that the value of the counter 3 is equal to the set value 3 and each set value of the determination means are stored. By providing a parameter register 2 and appropriately setting each set value of the determination means according to each device of SRAM and DRAM, a control signal of each external device is output at a required timing and a specific interface is built-in. SRAM, DR without
Data transfer with AM can be performed. In addition, since access is performed according to each device of SRAM and DRAM only by the difference of each set value of the determination means, the external device can use the SR.
A signal for distinguishing between AM and DRAM is not required.

FIG. 4 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention. In FIG. 4, reference numeral 1 denotes data processing means for outputting a read / write request signal, an address, write data, a byte enable, and the like for a requested address. Reference numeral 2 denotes a parameter register which can be written by the data processing means 1, and constitutes a set value storage means for storing three set values which are inputs of the judgment means 20 to 24 and 26, respectively. Reference numeral 3 denotes a counter which starts counting upon receiving a read / write request signal from the data processing means 1. Reference numeral 5 denotes an address selecting means for selecting one of the address output and the write data output of the data processing means 1. 6 is an address selection means 5
Is an address register that stores the output of. Reference numeral 7 denotes a write data register for storing the write data output from the data processing means 1. Reference numeral 8 denotes a tristate for controlling output of the value of the write data register 7 to the data bus. Reference numeral 9 denotes a read data register for taking the value of the address bus or data bus as read data into the semiconductor device. Reference numeral 11 denotes a tri-state for controlling output of the value of the address register 6 to the address bus. Numeral 12 denotes a data input selecting means for outputting either the value of the address bus or the value of the data bus to the read data register 9 in accordance with the second control signal of the judging means 26. The address output selection means 5, the address register 6, the write data register 7, the tristates 8, 11, the read data register 9, and the data input selection means 12 constitute a bus means. Reference numeral 10 denotes a first signal indicating an access period (either read / write), a first signal indicating a read access period, receiving a read / write request signal of the data processing unit 1 and an output of the determination unit 23. 2 is a status register that outputs a second signal and a third signal indicating that the period is a write access period, and constitutes control means. Reference numerals 20 to 24 denote a first control signal indicating that the value of the counter 3 is smaller than the set value 1 and a second control signal indicating that the value of the counter 3 is equal to the set value 3. The setting values 1, 2, and 3 used by the respective judging means are stored in the parameter register 2 for each judging means. 26 is judgment means 20 to 24
Is a determination means in which "0" is input instead of the value of the counter 3. Reference numeral 30 denotes a logic circuit that asserts an active signal to the terminal 1 only when both the first control signal of the determination means 20 and the first signal of the status register are asserted. Reference numeral 31 asserts an active signal to the terminal 2 only when the first control signal of the judging means 21, the third signal of the status register, and the three upper byte enable signals output by the data processing means 1 are both asserted. Logic circuit. 32 is the judgment means 21
Terminal 3 only when both the first control signal, the third signal of the status register, and the three lower byte enable signals output by the data processing means 1 are asserted.
Is a logic circuit that asserts an active signal. 3
3 is a terminal 4 only when the first control signal of the judging means 22 and the first signal of the status register are both asserted.
Is a logic circuit that asserts an active signal. 3
Reference numeral 4 denotes a logic circuit that asserts an active signal when the second control signal of the determination unit 23 is asserted or the read / write request signal of the data processing unit 1 is asserted. Reference numeral 35 denotes a logic circuit that asserts an active signal to the terminal 5 only when both the first control signal of the determination unit 24 and the second signal of the status register are asserted. Reference numeral 36 denotes a logic circuit that asserts an active signal when the first control signal or the second control signal of the determination unit 23 is asserted. 37 asserts an active signal when the second control signal of the judging means 26 is asserted,
When the control signal is negated, the judgment means 23
Is a logic circuit that asserts an active signal when the first control signal is negated or the third signal of the status register 10 is asserted. 3
Reference numeral 8 denotes a logic circuit that asserts an active signal when the second control signal of the judging means 26 is asserted and the first control signal of the judging means 21 is asserted.
The logic circuits 30 to 38 constitute control signal generation means.

The operation of the semiconductor device configured as described above will be described below with reference to FIGS. 4, 2 and 5.

FIG. 2 shows an example of an access timing chart of the SRAM. The access timing of the SRAM is determined by the parameters CSS, CSE, R shown in FIG.
It is defined by ES, REE, WES, and WEE. In contrast to such an SRAM, the semiconductor device of FIG.
S, terminal 2 is WE1, terminal 3 is WE0, terminal 5 is R
E, the address is connected to the address bus, and the data is connected to the data bus. The parameter register 2 is given the respective set values of the judging means 20 to 24 and 26 from the data processing means 1 via the register write bus as shown in Table 3 below. Note that since the terminal 4 is not used, the set value of the determination means 22 is “not set” indicating not set.
And With this setting, the second control signal of the judging means 26 is always asserted, so that the tristate 11 is always turned on, and the address bus is provided with the address register 6.
Is output.

[0031]

[Table 3]

At t0 in FIG. 2, when the read request signal is asserted from the data processing means 1, the status register 1
0 asserts the first signal and the second signal. The counter 3 has an initial value 0, and the address selecting means 5
Since the second control signal of No. 3 is asserted, the address output from the data processing means 1 is selected based on the output of the logic circuit 36 and output to the address register 6. The address register 6 uses the output of the logic circuit 34 as an update enable signal. The set value 1 of the judgment means 20 is 0 and the set value 2 is CS
E: Since the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie, CS. Similarly, terminals 2, 3, 5
No active signal is asserted. Next, FIG.
At t1, the update enable is asserted in the previous cycle t0, the address register 6 is updated, and the address selected by the address selection means at t0 is output to the address bus. On the other hand, the counter 3 starts counting in response to a read request signal from the data processing means 1, so that the counter value becomes 1. As a result, the first control signal of the judging means 20 is asserted.
The CS signal of the RAM is asserted. Next, at t2 in FIG. 2, the value of the counter 3 becomes 2, so that the first control signal of the determination means 24 is asserted. Since the second signal is asserted from the status register to the logic circuit 35, the terminal 5, ie, the RE signal of the SRAM, is asserted. At t3 in FIG. 2, the counter value becomes 3, but does not affect each terminal. At t4 in FIG. 2, the counter value is 4
, And the third control signal of the determination means 24 is asserted. The third control signal enables the read data register 9 to be updated and the data input selecting means 12
Has selected the value of the data bus, the read data register 9 internally stores the data output from the SRAM to the data bus at t4 at t5 and outputs the data to the data processing means 1 at t5. At t5 in FIG. 2, since the counter value becomes 5, the first control signal of the judging means 24 is negated, so that the terminal 5, ie, RE, is negated. Further, since the third control signal of the judging means 20 is asserted, the counter 3 is reset at t6 of the next cycle, and the read data transfer ends.

Next, at t7 in FIG. 2, when the write request signal is asserted from the data processing means 1, the status register 10 asserts the first signal and the third signal. The counter 3 has an initial value 0, and the address selection means 5 selects an address output from the data processing means 1 based on the output of the logic circuit 36 because the second control signal of the determination means 23 is asserted, and 6 is output. The address register 6 uses the output of the logic circuit 34 as an update enable signal. The setting value 1 of the judgment means 20 is 0 and the setting value 2 is C
Since the value of SE and the counter 3 is 0, the first control signal is not asserted, so that an active signal is not asserted at the terminal 1, ie, CS. Similarly, terminals 2, 3,
5 is not asserted. Next, at t8 in FIG. 2, since the update enable was asserted in the previous cycle t7, the address register 6 is updated, and the address selected by the address selecting means at t7 is output to the address bus. On the other hand, the counter 3 starts counting in response to the write request signal from the data processing means 1, so that the counter value becomes 1. As a result, the first control signal of the judging means 20 is asserted.
An active signal is asserted to the CS terminal of the RAM. Further, the third control signal of the judging means 21 is asserted and becomes an update enable signal for the write data register. Next, at t9 in FIG. 2, the value of the counter 3 becomes 2, so that the first control signal of the determination means 21 is asserted.
Since the third signal is asserted from the status register to the logic circuits 31 and 32, the terminals 2 and 3, that is, the WE0 and WE1 signals of the SRAM are asserted according to the upper and lower values of the byte enable. Previous cycle t8
Since the update enable of the write data register has been asserted in step (5), the write data register 7 is updated to store the output data of the data processing means. The tristate 8 is turned ON and the value of the write data register 7 is output to the data bus by the second control signal of the judging means 26 being asserted and the first control signal of the judging means 21 being asserted. At t10 in FIG. 2, the counter value becomes 3, but does not affect each terminal. At t11 in FIG. 2,
Since the counter value becomes 4 and the first control signal of the judging means 21 is negated, the terminals 2 and 3, ie, the WE1 and WE0 signals of the SRAM are negated. In addition, the tristate 8 is turned off accordingly, so that no data is output to the data bus. At t12 in FIG. 2, the third control signal of the judging means 20 is asserted because the counter value has become 5, so that the counter 3 is reset at t13 of the next cycle and the write data transfer ends.

FIG. 5 shows an example of an access timing diagram of the address data multiplex device. The access timing is determined by the parameters ADE, CSS, CSE, ASS, ASE, and RE shown in FIG.
S, REE, WES, and WEE. With respect to such an address data multiplex device, the semiconductor device of FIG. 4 has a terminal 1 connected to CS, a terminal 2 connected to WE1, a terminal 3 connected to WE0, a terminal 4 connected to AS, and a terminal 5 connected to RE, and Is connected to the address bus, and data is connected to the data bus. The parameter register 2 is given the respective set values of the judging means 20 to 24 from the data processing means 1 via the register write bus as shown in Table 4 below. In this setting, the second control signal of the judging means 26 is always negated.
1 is the address register 6 when either the judgment means 23 or the first control signal of the judgment means 21 is asserted.
Is output to the address bus. Also, the tristate 8 is always turned off for the same reason, so that the data bus is not driven by the semiconductor device. Further, the data input selecting means 12 always selects the value of the address bus.

[0035]

[Table 4]

At t0 in FIG. 5, when the read request signal is asserted from the data processing means 1, the status register 1
0 asserts the first signal and the second signal. The counter 3 has an initial value 0, and the address selecting means 5
Since the second control signal of No. 3 is asserted, the address output from the data processing means 1 is selected based on the output of the logic circuit 36 and output to the address register 6. The address register 6 uses the output of the logic circuit 34 as an update enable signal. The set value 1 of the judgment means 20 is 0 and the set value 2 is CS
E: Since the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie, CS. Similarly, terminals 2, 3,
No active signal is asserted at 4,5. Next, at t1 in FIG. 5, since the update enable was asserted in the previous cycle t0, the address register 6 is updated. On the other hand, the counter 3 starts counting in response to a read request signal from the data processing means 1, so that the counter value becomes 1. Accordingly, the first control signal of the determination unit 20 is asserted, and thus the CS signal of the terminal 1, that is, the external device is asserted. Further, the tristate 11 is turned on because the first control signal of the judging means 23 is asserted.
And the address selected by the address selecting means at t0 is output to the address bus. Next, t2 in FIG.
Since the value of the counter 3 is 2, the first control signal of the determination means 22 is asserted. Since the first signal is asserted from the status register to the logic circuit 33, the terminal 4, that is, the AS signal of the external device is asserted. At t3 in FIG. 5, the counter value becomes 3,
It does not affect each terminal. At t4 in FIG. 5, since the counter value has become 4, the first control signal of the judging means 22 is negated, so that the terminal 4, ie, AS, is negated. At t5 in FIG. 5, the counter value becomes 5, the first control signal of the determination means 23 is negated, and the logic circuit 37
, The tristate 11 is turned off. Therefore, no address is output to the address bus.
At t6 in FIG. 5, since the counter value becomes 6, the first control signal of the judging means 24 is asserted. Logic circuit 35
Since the second signal is asserted from the status register, the terminal 5, that is, the RE signal of the external device, is asserted. At t7 in FIG. 5, the counter value becomes 7, and the third control signal of the determination unit 24 is asserted.
Since the first control signal enables updating of the read data register 9 and the data input selecting means 12 selects the value of the address bus, the read data register 9 is output from the external device to the address bus at t7. The stored data is stored internally at t8 and output to the data processing means 1. At t8 in FIG. 5, since the counter value has become 8, the first control signal of the judging means 24 is negated, so that the terminal 5, ie, RE, is negated. Further, since the third control signal of the judging means 20 is asserted, the counter 3 is reset at t8 in the next cycle, and the read data transfer ends.

Next, when the write request signal is asserted from the data processing means 1 at t9 in FIG. 5, the status register 10 asserts the first signal and the third signal. The counter 3 has an initial value 0, and the address selecting means 5 selects an address output from the data processing means 1 based on the first control signal of the judging means 23 and outputs it to the address register 6. The address register 6 uses the output of the logic circuit 34 as an update enable signal. Since the set value 1 of the judging means 20 is 0, the set value 2 is CSE, and the value of the counter 3 is 0, the first control signal is not asserted.
No active signal is asserted on S. Similarly, no active signal is asserted at terminals 2, 3, and 5. Next, at t10 in FIG. 5, since the update enable was asserted in the previous cycle t9, the address register 6 is updated. On the other hand, the counter 3 starts counting in response to the write request signal from the data processing means 1, so that the counter value becomes 1. Accordingly, the first control signal of the determination unit 20 is asserted, and an active signal is asserted at the terminal 1, that is, the CS terminal of the external device. Further, since the first control signal of the judging means 23 is asserted, the tristate 11 is turned on, and the address selected by the address selecting means at t9 is output to the address bus. Next, at t11 in FIG.
Therefore, the first control signal of the determination unit 22 is asserted. The logic circuit 33 has a first register from the status register.
Is asserted, the terminal 4, that is, the AS signal of the external device is asserted. At t12 in FIG. 5, the counter value becomes 3, but does not affect each terminal. At t13 in FIG. 5, since the counter value has become 4,
Since the first control signal of the determination means 22 is negated,
Terminal 4 or AS is negated. Judgment means 2
When the first third control signal is asserted, the address selecting means 5 selects the write data according to the output of the logic circuit 36, and the logic circuit 34 asserts the address register update enable signal. Next, at t14 in FIG. 5, the value of the counter 3 becomes 5, so that the first control signal of the determination means 21 is asserted. Since the third signal is asserted from the status register to the logic circuits 31 and 32, the terminals 2 and 3, ie, the WE0 and WE1 signals of the external device are asserted according to the upper and lower values of the byte enable. Since the update enable of the address register was asserted in the previous cycle t13, the address register 6 is updated and the write data of the data processing means 1 is stored. The assertion of the first control signal of the judging means 21 turns on the tristate 11 and outputs the value of the address register 6 to the address bus. FIG.
At t15, the counter value becomes 6, but does not affect each terminal. At t16 in FIG. 5, the counter value becomes 7, but does not affect each terminal similarly to t15. FIG.
At t17, the counter value becomes 8, and the first control signal of the judging means 21 is negated. Therefore, the signals WE1 and WE0 of the terminals 2 and 3, that is, the external device are negated. In addition, the tristate 11 is turned off in accordance with this, so that no data is output to the address bus. Further, since the third control signal of the judging means 20 is asserted, the counter 3 is reset and the write data transfer ends.

As described above, according to the present embodiment, the counter 3 which starts counting in accordance with the transfer request signal of the data processing means 1, the value of the counter 3 is larger than the set value 1 and the value of the counter 3 is the set value A plurality of determination means for outputting a first control signal indicating that the value is equal to or less than 2 and a second control signal indicating that the value of the counter 3 is equal to the set value 3 and each set value of the determination means are stored. A parameter register 2 is provided, and by appropriately setting each set value of the judging means according to each device of the SRAM and the address data multiplex device, a control signal of each external device is output at a necessary timing, and a specific signal is output. Data can be transferred between the SRAM and the address data multiplex device without incorporating an interface. Further, the determination means 26 can distinguish between the SRAM and the address data multiplex device based on the set value.

FIG. 6 is a configuration diagram of a semiconductor device according to the third embodiment of the present invention. In FIG. 6, reference numeral 1 denotes data processing means for outputting a read / write request signal, an address, write data, byte enable, and the like, and a mode signal indicating whether or not to perform handshake access to a requested address. 2 is a parameter register which can be written by the data processing means 1;
The set value storage means stores the three set values which are the inputs of the judgment means 20, 21, 23 to 25, respectively. 3
Is a counter which starts counting upon receiving a read / write request signal from the data processing means 1. Reference numeral 6 denotes an address register for storing an address output from the data processing means 1. Reference numeral 7 denotes a write data register for storing the write data output from the data processing means 1. Reference numeral 8 denotes a tristate for controlling output of the value of the write data register 7 to the data bus. 9 is a read data register for taking the value of the data bus into the semiconductor device. The address register 6, the write data register 7, the tristate 8, and the read data register 9 constitute a bus means. Reference numeral 10 denotes a first signal indicating an access period (either read / write), a first signal indicating a read access period, receiving a read / write request signal of the data processing unit 1 and an output of the determination unit 23. 2 signals,
These are status registers that output a third signal indicating that it is a write access period, and constitute control means. Reference numeral 13 denotes a signal storage unit that stores a data acknowledge signal output from an external device. 14 is
Set by the output of the logic circuit 38, the second
Is reset by the control signal of FIG.
20, 21, 23 to 25 indicate that the value of the counter 3 is the set value 1
The first control signal indicating that the value of the counter 3 is smaller than the set value 2 and the value of the counter 3 is smaller than the set value 3
And a setting value 1, 2, 3 used by each judgment means is stored in the parameter register 2 for each judgment means. Reference numeral 30 denotes a logic circuit that asserts an active signal to the terminal 1 only when both the first control signal of the determination means 20 and the first signal of the status register are asserted. Reference numeral 31 asserts an active signal to the terminal 2 only when the first control signal of the judging means 21, the third signal of the status register, and the three upper byte enable signals output by the data processing means 1 are both asserted. Logic circuit. 32 is the first of the determination means 21
Control signal, the third signal of the status register, and the lower byte enable signal 3 output by the data processing means 1.
This is a logic circuit that asserts an active signal to the terminal 3 only when both signals are asserted. 34 is a logic circuit for asserting an active signal when the second control signal of the judging means 20 and the first signal of the status register are both asserted or the read / write request signal of the data processing means 1 is asserted. It is. 35
Is a logic circuit that asserts an active signal at the terminal 5 only when both the first control signal of the determination means 24 and the second signal of the status register are asserted. The logic circuits 30 to 32, 34, and 35 constitute control signal generation means. Reference numeral 38 denotes a logic circuit that asserts a set signal to the flip-flop 14 when the first control signal of the judging means 25 is negated and the output of the signal holding means 13 is active. Reference numeral 39 denotes a logic circuit which indicates that the mode signal is a handshake access, and asserts an active signal when the flip-flop 14 is not set and the first control signal of the judging means 25 is negated. is there. The logic circuits 38 and 39 and the flip-flop 14 constitute stop signal generation means.

The operation of the semiconductor device configured as described above will be described below with reference to FIGS. 6, 2 and 7.

FIG. 2 shows an example of an access timing chart of the SRAM. The access timing of the SRAM is determined by the parameters CSS, CSE, R shown in FIG.
It is defined by ES, REE, WES, and WEE. In contrast to such an SRAM, the semiconductor device of FIG.
S, terminal 2 is WE1, terminal 3 is WE0, terminal 5 is R
E, the address is connected to the address bus, and the data is connected to the data bus. The parameter register 2 is provided with the respective set values of the determination means 20, 21, 23 to 25 from the data processing means 1 via the register write bus as shown in Table 5 below. When the SRAM is accessed, the output of the logic circuit 39 does not become active.
“X” representing re is used.

[0042]

[Table 5]

At t0 in FIG. 2, when a read request signal is asserted from the data processing means 1, the status register 1
0 asserts the first signal and the second signal. The counter 3 has an initial value of 0. The address register 6 is used for determining
The second control signal of No. 3 is an update enable signal. Since the set value 1 of the judging means 20 is 0, the set value 2 is CSE, and the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie, CS. Similarly, no active signal is asserted at terminals 2, 3, and 5. Next, at t1 in FIG.
Since the update enable is asserted in the previous cycle t0, the address register 6 is updated, and the value of the address register 6 is output to the address bus. On the other hand, the counter 3 starts counting in response to a read request signal from the data processing means 1, so that the counter value becomes 1. As a result, the first control signal of the determination means 20 is asserted, and the CS signal of the terminal 1, that is, the SRAM is asserted. Next, at t2 in FIG. 2, the value of the counter 3 becomes 2, so that the first control signal of the determination means 24 is asserted. Since the second signal is asserted from the status register to the logic circuit 35, the terminal 5, ie, the RE signal of the SRAM, is asserted. At t3 in FIG. 2, the counter value becomes 3, but does not affect each terminal. At t4 in FIG. 2, the counter value becomes 4, and the third control signal of the determination unit 24 is asserted. Since the third control signal enables the read data register 9 to be updated, the read data register 9 stores the data output to the data bus by the SRAM at t4 internally at t5 and outputs the data to the data processing means 1 at t5. I do. At t5 in FIG. 2, since the counter value becomes 5, the first control signal of the judging means 24 is negated, so that the terminal 5, ie, RE, is negated. Further, since the third control signal of the judging means 20 is asserted, the counter 3 is reset at t6 of the next cycle, and the read data transfer ends.

Next, at t7 in FIG. 2, when the write request signal is asserted from the data processing means 1, the status register 10 asserts the first signal and the third signal. The counter 3 has an initial value of 0, and the address register 6 uses the second control signal of the determination means 23 as an update enable signal. Since the set value 1 of the judging means 20 is 0, the set value 2 is CSE, and the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie, CS. Similarly, no active signal is asserted at terminals 2, 3, and 5. Next, at t8 in FIG. 2, since the update enable was asserted in the previous cycle t7, the address register 6 is updated. At t7, the value of the address register 6 is output to the address bus. On the other hand, the counter 3 starts counting in response to the write request signal from the data processing means 1, so that the counter value becomes 1. As a result, the first control signal of the judging means 20 is asserted, so that an active signal is asserted at the terminal 1, that is, the CS terminal of the SRAM. In addition, the third
Is asserted to become an update enable signal for the write data register. Next, at t9 in FIG. 2, the value of the counter 3 becomes 2, so that the first control signal of the determination means 21 is asserted. Since the third signal is asserted from the status register to the logic circuits 31 and 32,
Terminals 2 and 3 according to the upper and lower values of byte enable
3, that is, the WE0 and WE1 signals of the SRAM are asserted. Since the update enable of the write data register was asserted in the previous cycle t8, the write data register 7
Are updated to store the output data of the data processing means.
The assertion of the first control signal of the judging means 21 turns on the tristate 8, and outputs the value of the write data register 7 to the data bus. T10 in FIG.
In this case, the counter value becomes 3, but does not affect each terminal. At t11 in FIG. 2, the counter value becomes 4, and the first control signal of the determination means 21 is negated. Therefore, the signals WE1 and WE0 of the terminals 2, 3 or the SRAM are negated. In addition, the tristate 8 is turned off accordingly, so that no data is output to the data bus.
At t12 in FIG. 2, the counter value becomes 5, and the determination means 2
Since the third control signal of 0 is asserted, the counter 3 is reset at t13 in the next cycle, and the write data transfer ends.

Next, FIG. 7 shows an example of an access timing diagram of the handshake device. The access timing of the handshake device is determined by the parameters CSS, CSE, RES, REE, WES,
It is defined by WEE and MSK. For such a handshake device, the semiconductor device of FIG.
S, terminal 2 is WE1, terminal 3 is WE0, terminal 5 is R
E, the address is connected to the address bus, and the data is connected to the data bus. The data acknowledge signal of the handshake device is input to the signal storage unit 13. The parameter register 2 has a judgment means 2 from the data processing means 1 via a register write bus.
Each set value of 0, 21, 23 to 25 is given as shown in Table 6 below.

[0046]

[Table 6]

At t0 in FIG. 7, when the read request signal is asserted from the data processing means 1, the status register 1
0 asserts the first signal and the second signal. The counter 3 has an initial value of 0. The address register 6 is used for determining
The second control signal of No. 3 is an update enable signal. The set value 1 of the judgment means 20 is 0, the set value 2 is CSE + MSK,
Since the value of the counter 3 is 0, the first control signal is not asserted, so that no active signal is asserted at the terminal 1, ie CS. Similarly, no active signal is asserted at terminals 2, 3, and 5. Next, t in FIG.
At 1, the update enable is asserted in the previous cycle t0, so that the address register 6 is updated and the value of the address register 6 is output to the address bus. On the other hand, since the second control signal of the judgment means 25 is 0, the counter 3 starts counting by the read request signal of the data processing means 1 without stopping. Therefore, the counter value becomes 1. Accordingly, the first control signal of the determination unit 20 is asserted, and thus the CS signal of the terminal 1, that is, the external device is asserted. Next, at t2 in FIG.
5 is asserted, and the value of the counter 3 becomes 2, so that the first control signal of the determination means 24 is asserted. Since the second signal is asserted from the status register to the logic circuit 35, the terminal 5, that is, the RE signal of the external device, is asserted. At t3 in FIG. 7, the counter value becomes 3, but does not affect each terminal. Further, since the first control signal of the determination means 25 is asserted and the data acknowledge signal is not asserted, the counter 3 stops counting from t4 of the next cycle. At t4 in FIG. 7, the counter value remains at 3, and
Since the data acknowledge signal is asserted, the output of the signal storage unit 13 becomes active in the next cycle t5. At t5 in FIG. 7, although the counter value remains 3, the output of the signal storage means 13 becomes active, so that the flip-flop 14 is set and the output of the logic circuit 39 is negated. Thus, the counter 3 starts operating at t6 in the next cycle. At t6 in FIG. 7, the counter value becomes 4, and the third control signal of the determination unit 24 is asserted. Since the third control signal enables the update of the read data register 9, the read data register 9 stores the data output to the data bus by the handshake device at t4 internally at t4,
Output to the data processing means 1. At t7 in FIG. 7, since the counter value has become 5, the first control signal of the judging means 24 is negated, so that the terminal 5, ie, RE, is negated. Further, since the third control signal of the judging means 20 is asserted, the counter 3 is reset at t8 in the next cycle, and the read data transfer ends.

Next, at t9 in FIG. 7, when the write request signal is asserted from the data processing means 1, the status register 10 asserts the first signal and the third signal. The counter 3 has an initial value of 0, and the address register 6 uses the second control signal of the determination means 23 as an update enable signal. Set value 1 of the judgment means 20 is 0, set value 2 is CSE + MS
Since the value of K and the counter 3 is 0, the first control signal is not asserted, so that an active signal is not asserted at the terminal 1, ie, CS. Similarly, terminals 2, 3, 5
No active signal is asserted. Next, FIG.
At t10, since the update enable was asserted in the previous cycle t7, the address register 6 is updated, and at t7, the value of the address register 6 is output to the address bus. On the other hand, since the second control signal of the judging means 25 is 0, the counter 3 starts counting by the write request signal of the data processing means 1 without stopping. Therefore, the counter value becomes 1. Accordingly, the first control signal of the determination unit 20 is asserted, and an active signal is asserted at the terminal 1, that is, the CS terminal of the handshake device. Further, the third control signal of the judging means 21 is asserted and becomes an update enable signal for the write data register. Next, at t11 in FIG. 7, the first control signal of the determination unit 25 is asserted and the value of the counter 3 becomes 2, so that the first control signal of the determination unit 21 is asserted. Since the third signal is asserted from the status register to the logic circuits 31 and 32, the terminals 2 and 3, ie, the WE0 and WE1 signals of the external device are asserted according to the upper and lower values of the byte enable. Since the update enable of the write data register was asserted in the previous cycle t10, the write data register 7 is updated to store the output data of the data processing means. When the first control signal of the judging means 21 is asserted, the tristate 8 is turned on, and the write data register 7 is turned on.
Is output to the data bus. At t12 in FIG. 7, the counter value becomes 3, but does not affect each terminal. Further, since the first control signal of the determination means 25 is asserted and the data acknowledge signal is not asserted, the counter 3 stops counting from t13 of the next cycle. At t13 in FIG. 7, the counter value remains at 3 and the data acknowledge signal is asserted, so that the output of the signal storage unit 13 becomes active in the next cycle t14. At t14 in FIG. 7, although the counter value remains 3, the output of the signal storage means 13 becomes active, so that the flip-flop 14 is set and the output of the logic circuit 39 is negated. Thus, the counter 3 starts operating at t15 in the next cycle. At t15 in FIG. 7, the counter value becomes 4, and the first control signal of the judging means 21 is negated.
The E1 and WE0 signals are negated. In addition, the tristate 8 is turned off accordingly, so that no data is output to the data bus. Further, since the third control signal of the judging means 20 is asserted, the counter 3 is reset at t16 of the next cycle, and the write data transfer ends.

As described above, according to the present embodiment, the counter 3 which starts counting in accordance with the transfer request signal of the data processing means 1, the value of the counter 3 is larger than the set value 1 and the value of the counter 3 is the set value A plurality of determination means for outputting a first control signal indicating that the value is equal to or less than 2 and a second control signal indicating that the value of the counter 3 is equal to the set value 3 and each set value of the determination means are stored. A parameter register 2 is provided, and a stop signal generating means is provided to stop the operation of the counter 3 based on the data acknowledge signal of the handshake device. By appropriately setting each set value, the control signal of each external device is output at the required timing and a specific interface can be built. Without SRAM, it is possible to perform data transfer with the handshake device.

[0050]

As described above, the present invention provides a counter which starts counting in accordance with a transfer request signal of a data processing means,
A first control signal indicating that the value of the counter is greater than a set value 1 and a value of the counter is equal to or less than a set value 2 and a second control signal indicating that the value of the counter is equal to a set value 3 By providing a plurality of judging means for respectively outputting and a parameter register for storing each set value of the judging means, it is possible to provide a semiconductor device which requires a small amount of hardware and can perform operation verification in a short time.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a timing chart of the SRAM according to the embodiment;

FIG. 3 is a timing chart of the DRAM in the embodiment.

FIG. 4 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a timing chart of the address data multiplex device according to the embodiment;

FIG. 6 is a configuration diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a timing chart of the handshake device according to the embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data processing means 2 Parameter register 3 Counter 4 Row address generation means 5 Address selection means 6 Address register 7 Write data register 8,11 Tristate 9 Read data register 10 Status register 12 Data input selection means 13 Signal storage means 14 Flip-flop 20 ~ 26 Judgment means 30 ~ 39 Logic circuit

Claims (5)

[Claims] 1. A data processing means which operates in response to a clock and processes data in accordance with a command, a control means for holding a request signal of the data processing means and outputting a control signal indicating a type of requested access; A counter for starting an operation in response to a request signal from the data processing unit, a determination unit for determining a magnitude relationship between a value of the counter and a given set value and outputting a control signal, and a plurality of settings to be given to the determination unit A set value storage unit for storing a value, a control signal generation unit for generating a control signal for an external device based on an output of the determination unit, and an external device in accordance with a control signal output from the determination unit. A semiconductor device comprising: a bus unit serving as an address and data transfer path. A first control signal indicating that the value of the counter is greater than a set value and a value of the counter being equal to or less than a set value; 2. The semiconductor device according to claim 1, wherein a second control signal indicating the presence is output. 3. The bus means according to claim 1, wherein one of a row address for DRAM access generated in response to an address output from said data processing means and an address output from said data processing means is output from said determination means. 2. The semiconductor device according to claim 1, further comprising: an address selecting means for selecting based on the address. 4. An address selecting means for selecting one of an address output from the data processing means and data output from the data processing means based on an output from the judging means; Address output control means for controlling the output of the address output selection means to be output to an address bus based on the output of the data output means, and data to select one of an address bus input and a data bus input and to output to the data processing means. 2. The semiconductor device according to claim 1, further comprising: input selection means. 5. A data processing means which operates in response to a clock and processes data in accordance with an instruction, a control means for holding a request signal of said data processing means and outputting a control signal indicating a type of requested access; Signal storage means for storing a data acknowledge signal output from an external device, a counter which starts operation by a request signal of the data processing means, and stops operation only when a stop signal is asserted; Determining means for determining a magnitude relationship between a plurality of given set values and outputting a control signal; setting value storing means for storing a plurality of set values to be provided to the determining means; A control signal generating means for generating a control signal for the device, and an address and data between the external device according to the control signal output from the determining means. And bus means for the transfer path, the semiconductor device is characterized in that a stop signal generating means for generating a stop signal of the counter from the output of said signal storage means and said determining means.