JP2000332763A - Band controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a band by deciding an average bit rate even when the number of bits of packets is not constant. SOLUTION: A packet write circuit 11 writes received packet data to a first-in first-out memory FIFO 12. A read control circuit 14 is provided with a timer 16, that counts the time from start of operation and with a counter 15 that counts the number of already transmitted bits, so as to obtain an average bit rate from these values up to that time. This read control circuit 14 outputs an EN signal to the packet read circuit 11, when the average bit rate is lower than a reference bit rate BR 1 and generates a read signal of the FIFO 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a band control device for controlling a transmission band in packet transmission.

[0002]

2. Description of the Related Art Conventionally, a bandwidth control device is disclosed in
No. 7,802 and the like, it is used in an asynchronous transfer mode (hereinafter referred to as ATM). FIG. 7 shows a configuration of a conventional band control device. Reference numeral 61 denotes a first-in first-out type buffer, and reference numeral 62 denotes a read control circuit for generating a read signal of the buffer 61.

[0003] In the case of ATM, since the cell length is constant (53 bytes), the average bit rate of a transmission cell can be controlled only by manipulating the read interval. For example, if reading is performed every 10 ms, 53 × 8 bits / 10 ms = 42.4 kbit / s, so if it is desired to transmit at x bits / s, reading should be performed every 53 × 8 bits / xbit / s.

[0004]

However, the conventional bandwidth control device has a problem that it can handle only ATM cells, that is, packets of a fixed length, and cannot handle packets of a variable length.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a band control device capable of controlling a band even with a variable-length packet.

[0006]

In order to solve the above problem, the present invention provides means for calculating an average value of packet data transmitted in the past, so that the average value is close to a predetermined bit rate. It is configured to control reading from the buffer. This makes it possible to provide an excellent bandwidth control device that can control the bandwidth even for variable-length packets.

[0007]

The present invention according to claim 1 of the present invention obtains a first-in first-out type buffer for storing received packets and a bit rate of packet data transmitted in the past to obtain a predetermined value. A read control circuit for controlling reading from the buffer so as to approach a bit rate. Thereby, even if packets of various lengths are received, the operation can be performed such that the bit rate of the transmission packet data becomes close to the predetermined value by the read control.

According to a second aspect of the present invention, the read control circuit calculates an average bit rate based on the time from the start of the operation to the present and the number of bits of the packet data read from the start of the operation to the present. May be configured to include: a control for reading out one packet data when the calculated average bit rate is equal to or less than a predetermined first reference bit rate and there is packet data in the buffer. This is so that if the number of packets to be transmitted is sufficient in the buffer, the average bit rate can be equal to or higher than the first reference bit rate and approach the value.

According to a third aspect of the present invention, the read control circuit calculates an average bit rate based on the total number of packets read so far and the number of bits of the next packet, and reads from the buffer. Means for detecting the amount of data to obtain the number of bits of one power packet, reading the detected amount of data, the time required to transmit the data, the time from the start of operation to the present, and the next packet Is estimated based on the time required for the packet data and the number of bits of the packet data read so far from the start of the operation, and the estimated average bit rate is set to a predetermined first bit rate. When the bit rate is equal to or lower than the reference bit rate, control may be performed to read the packet data. Bit rate will be able to close to a and the value less than or equal to the first reference bit rate.

According to a fourth aspect of the present invention, the read control circuit calculates an average bit rate based on the time from the start of the operation to the present and the number of bits of the packet data read from the start of the operation to the present. Reading of packet data starts when the calculated average bit rate is equal to or less than a predetermined first reference bit rate and there is packet data in the buffer, and the calculated average bit rate When the rate becomes equal to or higher than a second reference bit rate set as a value larger than a predetermined first reference bit rate, control may be performed such that the next packet data is not read. If there are enough packets to be stored in the buffer, the average bit rate is equal to or higher than the first reference bit rate and the second reference bit rate It is possible to transition between:.

According to a fifth aspect of the present invention, the read control circuit determines that the calculated average bit rate is less than or equal to a third reference bit rate set as a value smaller than the first reference bit rate. In the case shown, the value of the second reference bit rate may be temporarily changed to a value at least larger than a set value only once immediately after that. Data transmission can be permitted.

The read control circuit may include means for counting the number of data bits of the transmission packet in a predetermined time range, and means for sequentially storing the number of bits of the transmitted packet data. Means for calculating an average bit rate from the number of bits of the stored latest n times of packet data,
The average bit rate within a finite time can be controlled.

Hereinafter, embodiments of the present invention will be described.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of Embodiment 1 of the present invention. The packet is received by the packet writing circuit 11. This packet is
First in first out memory (hereinafter FIFO)
). This FIFO 12 has a 2-bit width of input / output terminals Pin and Pout for packets and input / output terminals Din and Dout for delimiters.

The packet reading circuit 13 has a FIFO1
The second packet is read out at a predetermined time. The read control circuit 14 controls reading of the packet read circuit 13 and includes a counter 15 for counting the number of read signals.
And a timer 16 for counting the time from the start of the operation.

In the above configuration, when a packet is received, the packet writing circuit 11 immediately changes the content to F.
Write to Pin input of IFO12. At the same time, "0" is written to the delimiter input Din. When the last bit of the packet is written to the FIFO 12, "1" is simultaneously written to the delimiter input Din.

On the other hand, on the read side of the FIFO 12, the counter 15 in the read control circuit 14 counts the number of read signals from the start of operation up to now, that is, the number of transmitted bits. Further, the read control circuit 14 obtains the average bit rate so far by dividing the number of transmitted bits by the value of the timer 16. Read control circuit 14
Compares the obtained average bit rate value with a predetermined reference bit rate BR1 value for each fixed time dt, and determines that packet reading is possible when the average bit rate falls below the reference bit rate BR1. Then, a read enable signal EN is output to the packet read circuit 13.

When the read permission signal EN is input, the packet read circuit 13 confirms that the FIFO 12 is not empty, and starts reading. When reading is continued and "1" is read from the delimiter output Dout, reading of one packet is completed, and reading is temporarily ended.
Thereafter, when the read permission signal EN is input again, this operation is repeated. Even if the read permission signal EN is input, if the FIFO 12 is empty, the read is not performed.

Here, as a specific example, the packet data read speed is 10 Mbit / s, and the maximum packet length is 1518.
Byte. Then, the time required for transmission even for the longest packet is 1518 × 8 bits / 10 Mbit / s ≒ 1.2 ms.

FIG. 2 is a timing chart showing the operation of the above configuration. As a specific example, dt = 10 ms, reference bit rate BR1 = 10 kbit / s, the time from the start of operation to 10 s, and the number of bits transmitted from the start of operation to 110 kb. As shown in FIG. 2, the average bit rate at this time is 11 kbit / s, and exceeds the average bit rate reference bit rate BR1, so that the read enable signal EN is not output. At the next determination timing, ie, at 10.01 s, the average bit rate is [110 k / 10.01] bit / s (≒ 10.89 kbit /
s) and the read enable signal EN is not yet output.

Thereafter, when the average bit rate becomes 11.01 s, the read enable signal EN is output because the average bit rate becomes [110 k / 11.01] bit / s (≒ 9.99 kbit / s). Then, if a 1000-byte packet is sent, it is 11.02s
Since the total number of transmitted bits is 110 kbit + 8 kbit = 118 kbit, the average is about 10.7 kbit / s, which exceeds the reference bit rate BR1, so that the read enable signal EN is not output.

As described above, in the first embodiment, the read control circuit 24 is provided with the averaging function of calculating the average bit rate from the time from the start of the operation to the present and the number of bits of the packet data read from the start of the operation to the present. Have. Thus, when the FIFO 12 is not empty, it is possible to control the transmitted average bit rate to be equal to or higher than the reference bit rate BR1 preset by the read control circuit 14 and close to BR1. The reference bit rate BR1 can be set based on the amount of past packet data transmission, and the reference bit rate BR1 may be changed and set. Then, the read control circuit 14
Controls the next packet transmission timing so as to approach the set reference bit rate BR1, so that even a variable-length packet can approach a desired band.

Thus, for example, even when a plurality of packet transmission lines are bundled into one transmission line whose band is not sufficiently large, when the traffic of one transmission line is extremely large, other transmission lines are transmitted. It is possible to eliminate the influence on the packets on the transmission path and to stabilize the transmission of the packets on the other transmission paths.

(Embodiment 2) FIG. 3 is a block diagram showing a configuration of Embodiment 2 of the present invention. A packet writing circuit 21, a 1-bit wide FIFO 22 having packet input / output terminals Pin and Pout, a packet reading circuit 23,
The read control circuit 24 is roughly constituted by a FIFO 27 in which the number of bits of a packet is written and read. In the second embodiment, the packet writing circuit 21
When writing a packet to the FO 22, the bit number of the packet is written to the FIFO 27. The read control circuit 24 is provided with a counter 25 for counting the number of read signals and a timer 26 for counting time from the start of operation.

According to such a configuration, when a packet is received by the packet writing circuit 21, its contents are immediately written to the Pin input of the FIFO 22. At the same time, the number of bits of the packet is written to the Lin input of the FIFO 27.

On the other hand, on the read side of the FIFO 22, the counter 25 of the read control circuit 24 counts the number of read signals from the start of operation until now, that is, the number of transmitted bits. Then, the average bit rate up to now is obtained by dividing the number of transmitted bits by the value of the timer 26.

The read control circuit 24 reads the number of bits of a packet to be read next from the FIFO 27, and calculates an average bit rate when it is assumed that the packet is read every fixed time dt. When the result falls below a predetermined reference bit rate BR 1, it is determined that packet reading is possible, and a read permission signal EN is output to the packet reading circuit 23. When the read permission signal EN is input, the packet read circuit 23 confirms that the FIFO 22 is not empty and starts reading. When reading is performed for the number of bits of the packet previously read from the FIFO 27, the reading is temporarily terminated. Thereafter, when the read enable signal EN is input again, this operation is repeated. Even if the read permission signal EN is input, the read operation is not performed if the FIFO 22 is empty.

As a specific example, dt = 10 ms, BR1 = 1
0 kbit / s, the time from the start of operation until now is 10 s, the number of bits transmitted so far from the start of operation is 95 kbit,
The number of bits of the packet to be read next is 8 kbit. If the packet is read at the next determination timing, 103 kbits are transmitted in 10.01 s, and the average bit rate is about 10.29 kbit / s, exceeding the reference bit rate BR1. Therefore, in this case, the read permission signal EN is not output.

However, since the average of 10.31 s is 103 kbit / 10.31 s ≒ 9.99 kbit / s, which is lower than the reference bit rate BR1, the read enable signal EN is output.

As described above, in the second embodiment, the averaging function for calculating the average bit rate from the time from the start of the operation to the present and the number of bits of the packet data read from the start of the operation to the present, and the next read from the FIFO 22 A data amount detection function for obtaining the number of bits of one power packet is provided. The read control circuit 24 determines the detected data amount,
From the time required to transmit the data, the time from the start of the operation to the present, and the number of bits of the packet data read from the start of the operation to the present, the average bit rate when the packet data is transmitted is calculated. When the FIFO 22 is not equal to or less than a predetermined first reference bit rate, the packet data is read out. When the FIFO 22 is not empty, the average bit rate is equal to or less than BR 1 and BR 1
Can be controlled to be close to

(Embodiment 3) FIG. 4 is a block diagram showing a configuration of Embodiment 3 of the present invention. The basic configuration is the same as that of the first embodiment.
A t-width FIFO 32, a packet readout circuit 33, and a readout control circuit 34 are provided. The read control circuit 34
A counter 35 for counting the number of read signals and a timer 36 for counting time from the start of operation are provided. In the third embodiment, the read control circuit 34 includes first and second
Are set as reference bit rates BR1 and BR2. Second
Is equal to the first reference bit rate B.
R1 is set to a value larger than (BR1 <BR
2).

The operation of the above configuration will be described. As soon as a packet is received by the packet write circuit 31, its contents are written to the Pin input of the FIFO 32. At the same time, "0" is written to the delimiter input Din. When the last bit of the packet is written, "1" is simultaneously written to the delimiter input Din.

On the other hand, on the read side of the FIFO 32, the counter 35 in the read control circuit 34 counts the number of read signals from the start of operation up to now, that is, the number of transmitted bits. Then, the number of transmitted bits is counted by the timer 36.
The average bit rate up to now is obtained by dividing by the value of. The value of the average bit rate is compared with a value of a predetermined first reference bit rate BR1 at regular time intervals dt, and the average bit rate is set to the first reference bit rate BR.
When the value is smaller than 1, it is determined that the packet can be read, and the read permission signal EN is output to the packet read circuit 33.

When the read permission signal EN is input, the packet read circuit 33 confirms that the FIFO 32 is not empty and starts reading. When reading is continued and "1" is read from the delimiter output Dout, reading of one packet is completed, and reading is temporarily ended.

Here, at the next determination timing, if the average bit rate up to that time is lower than the second reference bit rate BR2 set higher than the first reference bit rate BR1, the read enable signal EN is output. afterwards,
Until the average bit rate exceeds the second reference bit rate BR2 or the FIFO 32 becomes empty, the read enable signal EN is output each time at a determination timing of every dt, and packets are transmitted one after another. And the average bit rate is 2nd
Is stopped when the average bit rate exceeds the first reference bit rate BR1.
No reading is performed until the value falls below.

As a specific example, dt = 10 ms, BR1 = 1
It is assumed that 0 kbit / s, BR2 = 12 kbit / s, the time from the start of the operation until now is 10 s, and the number of bits transmitted so far from the start of the operation is 110 kbit. Then, as described in the first embodiment, the read enable signal EN is output at 11.01 s, and the packet is transmitted. The average bit rate after transmission is about 10.7 kbit / s as described above, but is lower than the second reference bit rate BR2. Therefore, reading is performed also at the next determination timing. Assuming that all the packets written to the FIFO 32 are 8 kbits for the sake of simplicity, the number of bits of the packets transmitted up to this time is 110 kbit + 8 kbit + 8 kbit = 126 kbit. The average bit rate is 126 kbit / 11.02s ≒ 11.4 kbit / s, which is still below the reference bit rate BR2.

However, when the next packet is read, the average bit rate is (110 kbit + 8 kbit × 3) /11.03 s ≒ 12.1 k
bit / s, the read enable signal EN is not output thereafter.

As described above, in the third embodiment, the average function of the same bit rate as in the above-described embodiment, and the output of the average function indicates a predetermined first reference bit rate or less, and If packet data is present, reading of the packet data is started, and if the output of the averaging function is equal to or higher than a second reference bit rate higher than a predetermined first reference bit rate, the next packet data is not read. Control, and when the number of packets to be transmitted is sufficient in the FIFO 32, the average bit rate is equal to or more than the first reference bit rate BR1,
It acts so as to transition between the second reference bit rate BR2 and the second reference bit rate BR2.

Further, according to this embodiment, there is an effect that large short-term traffic can be passed without any restriction. As shown in the above specific example, 24 kbit data can be transmitted within 30 ms, and the bit rate at this time is as large as 800 kbit / s.

(Embodiment 4) FIG. 5 is a block diagram showing a configuration of Embodiment 4 of the present invention. The packet write circuit 41, 2-bit FIFO 42, packet read circuit 43, and read control 44 circuit have a counter 45 for counting the number of read signals and a timer 46 for counting the time from the start of operation. In the fourth embodiment, the read control circuit 44 includes the first reference bit rate BR1
A smaller third reference bit rate BR3 is set. That is, the third reference bit rate BR3 <the first reference bit rate BR1 <the second reference bit rate BR2 is set.

The basic operation of the above configuration is the same as that of the third embodiment. And the average bit rate is the first
Even if the reference bit rate BR1 becomes equal to or less than
Is not transmitted because the packet is empty, but when the average bit rate is equal to or less than the third reference bit rate BR3, the value of the second reference bit rate BR2 is increased by one degree from the set value. To perform temporary variable control. Thus, when the number of ordinary packet transmissions is small, a large amount of data can be transmitted in a short period of time, and the restriction on large traffic can be further reduced as compared with the third embodiment.

(Embodiment 5) FIG. 6 is a block diagram showing a configuration of Embodiment 5 of the present invention. It comprises a packet writing circuit 51, a FIFO 52 having a width of 2 bits, a packet reading circuit 53, and a reading control circuit 54. The read control circuit 54 of this embodiment is provided with a counter 55 for counting the number of read signals for each fixed time dt, that is, for counting the number of data bits of a transmission packet for each dt, and a memory 56 for sequentially recording the value of the counter 55. .

In the operation of the above configuration, the write operation of the FIFO 52 is the same as that of the above-described first embodiment.
The contents are immediately written to the Pin input of the FIFO 52.
At the same time, "0" is written to the delimiter input Din. When the last bit of the packet is written to the FIFO 52, "1" is simultaneously written to the delimiter input Din. On the other hand, on the reading side from the FIFO 52, the value counted by the counter 55 is written into the memory 56 one by one every dt.

The read control circuit 54 includes a memory 56
The average bit rate is calculated from the last n count values stored in the following equation.

The sum of the count values of n times / (n × dt) Then, the read control circuit 54 calculates the current average bit rate value and the predetermined reference bit rate B
The value of R1 is compared at regular time intervals dt, and if the average bit rate is lower than the reference bit rate BR1, it is determined that packet reading is possible, and a read permission signal EN is output to the packet reading circuit 53.

As a specific example, dt = 10 ms, BR1 = 1
It is assumed that 0 kbit / s is set, and the number of read signals for the last eight times has been recorded in the memory 56. For example, 0,2
40,0,80,0,160,80,256. The average bit rate at this time is (0 + 240 + 0 + 80 + 0 + 160 + 80 + 256) bit / (8
× 10 ms) = 10.2 kbit / s, which exceeds the reference bit rate BR1, so that the read enable signal EN is not output. At the next determination timing, the contents of the memory are 240, 0, 80, 0, 160, 80, 256, 0, and the read enable signal EN is not output because there is no change in the total value.

However, at the next judgment timing, the contents of the memory become 0,80,0,160,80,256,0,0 and the average bit rate becomes 7.2 kbit / s, which is lower than BR1, so that the read enable signal EN is Is output. According to the fifth embodiment, there is an effect that the average bit rate of a packet can be obtained by a memory having a finite size.

The configuration in which the memory 56 is provided in the read control circuit 54 to obtain the average bit rate as described in the fifth embodiment can be applied to any of the first, second, third and fourth embodiments. What is necessary is just to use it instead of the timer used in each embodiment, and the same effect can be obtained.

[0049]

As described above, according to the first aspect of the present invention, the next packet transmission timing is controlled based on the bit rate of packet data transmitted in the past so as to approach a predetermined bit rate. Therefore, there is an effect that even a variable-length packet can approach a desired band.

Thus, even if a plurality of packet transmission lines are bundled into one transmission line whose bandwidth is not sufficiently large, the influence on packet transmission of another transmission line when the traffic of one transmission line is extremely large. Has the effect of eliminating as much as possible.

Further, an effect is obtained that even if a user attempts to transmit a packet exceeding the contracted band on a paid transmission path, the packet transmission can be restricted.

According to a second aspect of the present invention, by setting the first reference bit rate, if there are enough packets to be transmitted in the buffer, the average bit rate is equal to or more than the first reference bit rate and its value Can be approached.

According to a third aspect of the present invention, the average bit rate immediately after the packet is transmitted is estimated by estimating the average bit rate when the packet data is transmitted and comparing it with the first reference bit rate. It becomes possible to approach the value at or below the reference bit rate.

According to the fourth aspect, by setting the first and second reference bit rates, if there are enough packets to be transmitted in the buffer, the average bit rate is equal to or higher than the first reference bit rate. The transition can be made between the second reference bit rate and the second reference bit rate.

According to the fifth aspect, by setting the third reference bit rate as a value smaller than the first reference bit rate, the number of packet transmissions is small and immediately after the packet transmission becomes equal to or less than the third reference bit rate. Will be able to temporarily send large amounts of data.

The average bit rate within a finite time is controlled by storing the number of bits of the packet data of the latest n times and calculating the clocked average bit rate according to this transition. become able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a bandwidth control device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the band control device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a bandwidth control device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a bandwidth control device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a band control device according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a bandwidth control device according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional band control device.

[Explanation of symbols]

 11, 21, 31, 41, 51 Packet writing circuit 12, 22, 32, 42, 52 FIFO memory 13, 23, 33, 43, 53 Packet reading circuit 14, 24, 34, 44, 54 Reading control circuit 15, 25 , 35, 45, 55 Counter 16, 26, 36, 46 Timer 27 FIFO memory 56 memory

Continued on the front page (72) Inventor Makoto Doguchi 2-45, Hikosancho, Kanazawa-shi, Ishikawa Prefecture F-term in Matsushita Communication Kanazawa Research Laboratories Co., Ltd. 5K030 HA08 KA03 LC03 LC09 LC09 MB09

Claims (6)

[Claims] A first-in first-out buffer for storing received packets; and a bit rate of previously transmitted packet data.
A band control device comprising: a read control circuit that controls reading from the buffer so as to approach a predetermined bit rate. 2. The read control circuit further comprises: means for calculating an average bit rate based on the time from the start of operation to the present and the number of bits of packet data read from the start of operation to now, The first rate is predetermined
2. The bandwidth control device according to claim 1, wherein when the packet data is less than or equal to the reference bit rate, and the packet data exists in the buffer, control is performed to read out one packet data. 3. The read control circuit includes: means for calculating an average bit rate based on the total number of bits of a packet read so far and the number of bits of the next packet; and the number of bits of one packet to be read from the buffer. Means for detecting the amount of data to obtain, the detected amount of data, the time required to transmit the data, the time from the start of operation until now and the time required to read the next packet, Estimating the average bit rate when transmitting packet data based on the number of bits of the packet data read so far from the start of operation, and setting the estimated average bit rate to be equal to or less than a preset first reference bit rate. 2. The bandwidth control device according to claim 1, wherein control is performed to read out the packet data in a certain case. 4. The read control circuit, comprising: means for calculating an average bit rate based on the time from the start of operation to the present and the number of bits of packet data read from the start of operation to now; Is the first predetermined
Start reading packet data when packet data is present in the buffer, and when the calculated average bit rate is greater than a predetermined first reference bit rate. 2. The bandwidth control device according to claim 1, wherein when the data rate is equal to or higher than the set second reference bit rate, control is performed so that the next packet data is not read. 5. The read control circuit according to claim 1, wherein the calculated average bit rate is equal to or less than a third reference bit rate set as a value smaller than the first reference bit rate. 5. The band control device according to claim 4, wherein only the second reference bit rate is temporarily changed to a value at least larger than a set value. 6. The read control circuit includes: means for counting the number of data bits of a transmission packet in a predetermined time range; means for sequentially storing the number of bits of the transmitted packet data; 6. The bandwidth control device according to claim 2, further comprising: means for calculating an average bit rate from the number of bits of the packet data of n times.