JP2000332098A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of forming trench-type isolations, without lowering the yield of a semiconductor integrated circuit device. SOLUTION: A first embedded insulation film 4 embedded in deep trenches 2 and a second embedded insulation film 5 embedded in shallow trenches 3 form trench type isolations TI wherein after filling the first embedded insulation film 4 in the deep trenches 2, the shallow trenches 3 are formed partly adjacent to the deep trenches 2 and then filling is made in the shallow trenches 3, thereby reducing the steps resulting on the top faces of the shallow trenches 3 and between the shallow trenches 3 and their peripheral regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a step of forming a trench isolation.

[0002]

2. Description of the Related Art Trench isolation is a device isolation for electrically isolating adjacent semiconductor elements from each other by filling a predetermined filling material in a groove formed between adjacent semiconductor elements in a semiconductor substrate. Department.

For example, Japanese Patent Laid-Open No. 326659 discloses that after forming a deep groove for forming a trench isolation having an aspect ratio larger than 1 in a semiconductor substrate, a shallow groove having an aspect ratio of 1 or less remains in the deep groove. After the first buried insulating film is buried, a second buried insulating film is deposited on the semiconductor substrate, and then the upper portion of the second buried insulating film buried in the shallow groove is placed on its upper surface. A method (first method) of flattening so that the position is equal to the plane position around the shallow groove is disclosed.

Further, a shallow groove is formed in a semiconductor substrate, and then a deep groove is formed in a partial region at the bottom of the shallow groove, and then both are buried simultaneously with the same buried insulating film to form an element isolation. (Second method) has been considered.

[0005]

However, in the above-mentioned prior art, the following problems were considered.

That is, in the first method, if the etching rate of the second buried insulating film buried in the upper portion of the deep groove is different from that of the insulator in the peripheral region, the region in which the deep groove is buried in the cleaning step and its peripheral portion are removed. There is a problem that a step is generated between the conductive pattern and the region, the conductive film remains on the step when the conductive pattern is formed thereafter, and the remaining conductive film causes a short circuit between the patterned conductive patterns.

Further, in the second method, when a shallow groove is formed and then a deep groove is formed in a partial region at the bottom of the shallow groove, the thickness of a resist film used for processing the deep groove varies near the shallow groove. Further, there is a problem that the dimension of the deep groove varies due to the influence of halation from the shallow groove side wall. For this reason, it is necessary to take a dimensional margin between the shallow groove and the deep groove,
Since the area occupied by the element isolation portion increases, it is not suitable for high integration.

An object of the present invention is to provide a technique capable of forming a trench isolation without lowering the yield of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of improving the degree of integration of a semiconductor integrated circuit device by using the trench isolation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The semiconductor integrated circuit device of the present invention has a groove-type isolation constituted by a buried insulating film buried in a deep groove and a buried insulating film buried in a shallow groove. The deep groove is formed in contact with a partial region at the bottom of the shallow groove, and the upper surface of the buried insulating film in the shallow groove has a flat surface.

(2) The semiconductor integrated circuit device of the present invention has a groove-shaped isolation constituted by a semiconductor film buried in a deep groove and a buried insulating film buried in a shallow groove. The deep groove is provided with an insulating film on its inner wall and is formed in contact with a partial region at the bottom of the shallow groove. The upper surface of the buried insulating film in the shallow groove has a flat surface.

(3) In the semiconductor integrated circuit device according to the present invention, the upper surface of the buried insulating film or the semiconductor film in the deep groove constituting the trench isolation is substantially at the same position as the bottom of the shallow groove.

(4) In the semiconductor integrated circuit device of the present invention, the upper surface of the buried insulating film or the semiconductor film in the deep groove constituting the trench isolation is lower than the upper surface of the buried insulating film in the shallow groove. It is.

(5) In the semiconductor integrated circuit device of the present invention, the upper surface of the buried insulating film or the semiconductor film in the deep groove constituting the trench isolation has an aspect ratio of 1 or less from the bottom of the shallow groove. The lower side.

(6) In the semiconductor integrated circuit device of the present invention, the trench isolation is formed on a semiconductor substrate having an SOI structure in which a semiconductor layer is provided on an insulating layer, and a deep groove reaches the insulating layer. It is formed in.

(7) In the semiconductor integrated circuit device according to the present invention, M
An IS transistor or a bipolar transistor is formed.

(8) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming a deep groove for forming a trench isolation having an aspect ratio larger than 1 in a semiconductor substrate, and a first buried insulating film in the deep groove And a step of forming a shallow groove in the semiconductor substrate, including a region where the deep groove is formed, and depositing a buried insulating film on the semiconductor substrate,
Flattening the upper part of the buried insulating film buried in the shallow groove so that the upper surface position thereof is substantially equal to the plane position around the shallow groove.

(9) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming a deep groove for forming a trench isolation having an aspect ratio larger than 1 in a semiconductor substrate, and forming an insulating film on an inner wall surface of the deep groove After that, a step of embedding a semiconductor film in the deep groove and a step of forming a shallow groove in the semiconductor substrate and the semiconductor film, including a part of the region where the deep groove is formed, and then removing the exposed insulating film After depositing the buried insulating film on the semiconductor substrate, the upper part of the buried insulating film buried in the shallow groove is flattened so that its upper surface position is substantially equal to the plane position around the shallow groove. And a process.

(10) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the upper surface of the buried insulating film or the semiconductor film in the deep groove may be positioned substantially at the same position as the bottom of the shallow groove. It is assumed that.

(11) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the buried insulating film in the deep groove or the buried insulating film in the shallow groove may be formed by using the buried insulating film in the deep groove. Below the upper surface of the.

(12) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing the trench isolation, the aspect ratio of the upper surface of the buried insulating film or the semiconductor film in the deep groove may be higher than that of the bottom of the shallow groove. The lower side is set in the range of 1 or less.

According to the above-described means, after a predetermined depth of the deep groove constituting the trench isolation is buried, a shallow groove including the region where the deep groove is formed is formed, and then the shallow groove is buried. By flattening the upper part of the embedded material in the inside, no step is formed in the shallow groove on the deep groove and the upper part of the shallow groove around the deep groove, and the steepness between the groove-shaped isolation and the surrounding area is reduced. It is possible to form the groove-shaped isolation without generating a significant step.

Further, since a shallow groove including the region where the deep groove is formed is formed after filling the deep groove constituting the groove isolation by a predetermined amount, a photolithography step in forming the deep groove or the shallow groove is performed. Since problems such as variations in the thickness of the resist film and halation can be reduced, the dimensional margin between the shallow groove and the deep groove can be reduced, and the shallow groove and the deep groove can be formed close to each other.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing a trench isolation according to an embodiment of the present invention.

A deep groove 2 and a shallow groove 3 are formed in an element isolation portion on the main surface of the semiconductor substrate 1, and the deep groove 2 is formed in a partial region at the bottom of the shallow groove 3. A first buried insulating film 4 made of, for example, a silicon oxide film is buried in the deep groove 2, and the upper surface of the first buried insulating film 4 in the deep groove 2 is located at substantially the same position as the bottom of the shallow groove 3. is there.

A second buried insulating film 5 made of, for example, a silicon oxide film is buried in the shallow groove 3 formed by the shallow groove 3a in the region above the deep groove 2 and the shallow groove 3b in the other region. The upper surface of the second buried insulating film 5 in the shallow groove 3 has a flat surface with no steps. First buried insulating film 4 buried in deep groove 2 and second buried insulating film 4 buried in shallow groove 3
The buried insulating film 5 forms a trench isolation TI.

Note that the upper surface of the first buried insulating film 4 in the deep groove 2 does not need to be located substantially at the same position as the bottom of the shallow groove 3, and if it is below the upper surface of the second buried insulating film 5. Alternatively, the depth may be lower than the bottom of the shallow groove 3 within the range of the aspect ratio of 1 or less.

Next, a method of manufacturing the trench isolation TI according to the first embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 2, a silicon oxide film 6 having a thickness of about 15 nm is formed on a surface of a semiconductor substrate 1 made of silicon single crystal by a thermal oxidation treatment, and then a CVD (Chemical Vapor Deposition) is formed on the upper layer. 2), a silicon nitride film 7 having a thickness of about 100 nm and a silicon oxide film 8 having a thickness of about 200 nm are sequentially deposited. The silicon nitride film 7 is a film that functions as an etching stopper as described later, and the silicon oxide film 8
Is a film that functions as an etching mask when forming a deep groove, as described later.

Next, using the photoresist pattern as a mask, the silicon oxide film 8, the silicon nitride film 7, and the silicon oxide film 6 are sequentially etched. The photoresist pattern is formed by a normal photolithography technique. That is, the photoresist pattern is patterned by applying a photoresist film and then performing exposure and development processing on the photoresist film.

Next, after the photoresist pattern is removed by ashing, the semiconductor substrate 1 is etched using the silicon oxide film 8 as an etching mask to form a deep groove 2. The depth of the deep groove 2 is, for example, about 3 μm, and the groove width is, for example, about 0.4 μm.

Next, as shown in FIG. 3, after removing the silicon oxide film 8 using a hydrofluoric acid-based solution, a first buried insulating film made of, for example, a non-doped silicon oxide film is formed on the semiconductor substrate 1. The first buried insulating film 4 is filled in the deep groove 2 by depositing the film 4 by the CVD method. This first
The thickness of the buried insulating film 4 is about 500 nm.

At this time, since the coverage of the first buried insulating film 4 is low, the center of the deep groove 2 is not completely filled with the first buried insulating film 4 and the cavity 9 is formed. The cavity 9 extends from near the bottom surface of the deep groove 2 to the upper surface of the semiconductor substrate 1.

Next, as shown in FIG. 4, the first buried insulating film 4 is etched back by, for example, a reactive ion etching method, and the first buried insulating film 4 deposited on the silicon nitride film 7 is formed. Is removed.

At this time, since the silicon nitride film 7 under the first buried insulating film 4 functions as an etching stopper,
Etching on the semiconductor substrate 1 outside the region where the deep groove 2 is formed is stopped at the surface of the silicon nitride film 7.

However, in the region where the deep groove 2 is formed, the silicon nitride film 7 is partially removed.
Etching of the first buried insulating film 4 proceeds therein. Therefore, the upper portion of the first buried insulating film 4 in the deep groove 2 is removed by etching. As a result, a groove 10 having, for example, an aspect ratio of 1 or less is formed in the deep groove 2.

Here, the depth d ₁ of the groove 10 is set so that the upper surface of the first buried insulating film 4 in the deep groove 2 is located at substantially the same position as the bottom of the shallow groove 3 to be formed later. For example, 0.3
It is about 5 to 0.4 μm. Note that the groove 10 may have an aspect ratio of 1 or more as long as a cavity is not formed in a second buried insulating film 5 described later that is buried in the shallow groove 3. In addition, the upper surface of the first buried insulating film 4 in the deep groove 2 does not need to be located at substantially the same position as the bottom of the shallow groove 3, but may be lower than the upper surface of the second buried insulating film 5 described later. Alternatively, the height may be lower than the bottom of the shallow groove 3 within the range of the aspect ratio of 1 or less.

Next, as shown in FIG. 5, a photoresist film 11a is applied on the semiconductor substrate 1. At this time, the groove 10
Since the aspect ratio is small, the photoresist film 11a is completely buried in the trench 10, and the surface becomes flat. Thereby, the thickness variation of the photoresist film 11a is suppressed, and the pattern of the photoresist film 11a can be formed without any problem by the ordinary photolithography technique.

Next, as shown in FIG. 6, the photoresist film 11a is patterned to form a photoresist pattern 11b from which the photoresist film 11a in a region where the shallow groove 3 is to be formed is removed.

Using the photoresist pattern 11b as a mask, the silicon nitride film 7, the silicon oxide film 6, and the semiconductor substrate 1 are sequentially etched. The semiconductor substrate 1
Etching is performed to the same depth as the upper surface of the first buried insulating film 5 buried in the deep groove 2, and as shown in FIG. 7, the shallow groove 3a in the region above the deep groove 2 and the shallow groove 3b in the other region as shown in FIG.
Is formed. The depth d2 of the shallow groove 3 is, for example, 0.35 to
It is about 0.4 μm.

The bottom of the shallow groove 3 does not need to be located at substantially the same position as the upper surface of the first buried insulating film 4 in the deep groove 2, and is located below the upper surface of the second buried insulating film 5 described later. Any height may be used, or the height may be higher than the upper surface of the first buried insulating film 4 in an aspect ratio of 1 or less.

Next, after removing the photoresist pattern 11b, a second buried insulating film 5 made of, for example, a non-doped silicon oxide film is deposited on the semiconductor substrate 1 by a CVD method as shown in FIG. Thereby, the second buried insulating film 5 is filled in the shallow groove 3.

At this time, the second buried insulating film 5 is also
Even in the case where the coverage is low as in the case of the buried insulating film 4, in this case, since the aspect ratio of the shallow groove 3 is small, the shallow groove 3
Completely without forming a cavity therein.
Can be embedded.

Next, as shown in FIG. 9, the surface of the first buried insulating film 4 is subjected to, for example, chemical mechanical polishing (Chemical Mechanica).
l Polishing (CMP) method to remove the second buried insulating film 5 deposited on the silicon nitride film 7 so that the second buried insulating film 5 having a flat surface is Embed.

At this time, since the silicon nitride film 7 below the second buried insulating film 5 functions as a stopper, the polishing of the second buried insulating film 5 is stopped at the surface of the silicon nitride film 7. This makes it possible to make the upper surface position of the second buried insulating film 5 in the shallow groove 3 substantially equal to the surface position of the silicon nitride film 7 around the shallow groove 3.

Thereafter, the silicon nitride film 7 is removed by, for example, hot phosphoric acid treatment, so that the silicon nitride film 7 is buried in the first buried insulating film 4 and the shallow groove 3 buried in the deep groove 2 shown in FIG. A trench isolation TI constituted by the second buried insulating film 5 is formed.

In the first embodiment, the CMP method is used to bury the second buried insulating film 5 in the shallow groove 3.
For example, when the second buried insulating film 5 is formed of an SOG (Silicon On Glass) film, the second buried insulating film 5 may be etched back by a reactive ion etching method.

Next, BiCMOS (Bipolor Compliment) to which the trench isolation TI of the first embodiment is applied.
FIG. 10 is a cross-sectional view of a main part of a semiconductor substrate (ary MOS).

The semiconductor substrate 12 is made of, for example, SOI (Silico
n On Insulator) structure and support substrate 12a
And an insulating layer 12b formed thereon and a semiconductor layer 12c formed thereon.

The support substrate 12a is made of, for example, silicon single crystal. The insulating layer 12b is made of, for example, a silicon oxide film, and has a thickness of, for example, about 0.5 to 1 μm.
The semiconductor layer 12c is made of, for example, n-type silicon single crystal, and the upper layer is an epitaxial layer. The thickness of the semiconductor layer 12c is, for example, about 1 to 1.5 μm. The thickness of the epitaxial layer is, for example, 0.5 to 1 μm.
It is about.

In the semiconductor layer 12c, the p-channel MI
SFET (Metal Insulator Semiconductor Field Effe
ct Transistor) formation region P includes a p-channel MISF
ETQp is formed. In the semiconductor layer 12c in the p-channel MISFET formation region P, a channel stopper region 13a and an element region 14a are formed in order from the lower layer. Channel stopper region 13a and element region 14
For example, phosphorus or arsenic as an n-type impurity is introduced into a.

A pair of p-type semiconductor regions 15a constituting the source and the drain of the p-channel MISFET Qp are formed in the element region 14a. Also, the gate electrode 16
Is a gate insulating film 1 between a pair of p-type semiconductor regions 15a.
7 are formed. Note that the pair of p-type semiconductor regions 15a are electrically connected to the electrodes 20a through connection holes 19a formed in the insulating film 18a.
The gate insulating film 17 and the insulating film 18a are made of, for example, a silicon oxide film. The electrode 20a is made of, for example, an aluminum (Al) -silicon (Si) -copper (Cu) alloy.

In the semiconductor layer 12c, the n-channel MI
The n-channel MISFET Qn
Are formed. n-channel MISFET formation region N
In the semiconductor layer 12c, a channel stopper region 13b and an element region 14b are formed in order from the lower layer. In the channel stopper region 13b and the element region 14b,
For example, p-type impurity boron is introduced.

A pair of n-type semiconductor regions 15b constituting the source and the drain of the n-channel MISFET Qn are formed in the element region 14b. Also, the gate electrode 16
Is a gate insulating film 1 between a pair of n-type semiconductor regions 15b.
7 are formed. Note that the pair of n-type semiconductor regions 15b are electrically connected to the electrodes 20b through connection holes 19b formed in the insulating film 18a.
The electrode 20b is made of, for example, an Al-Si-Cu alloy.

In the semiconductor layer 12c, an ECL (Emitter Co
For example, an npn-type bipolar transistor Qbi constituting an upled logic) is formed.

In the semiconductor layer 12c of the bipolar transistor formation region Bi, a collector buried region 21a, a collector region 21b, and a collector extraction region 21c are formed.

For example, antimony as an n-type impurity is introduced into the collector buried region 21a. Further, for example, phosphorus or arsenic as an n-type impurity is introduced into the collector region 21b and the collector extraction region 21c. The collector extraction region 21c is electrically connected to the collector electrode 20c through a connection hole 19c formed in the insulating film 18a. The collector electrode 20c is, for example, A
It is made of an l-Si-Cu alloy.

The base region 22 is formed above the collector region 21b. The base region 22 includes a central intrinsic base region 22a and a base extraction region 2 on the outer periphery thereof.
2b. For example, boron as a p-type impurity is introduced into the base region 22.

The base extraction region 22b is electrically connected to the base extraction electrode 23. The base extraction electrode 23 is made of, for example, p-type polycrystalline silicon, and is connected to the base electrode 20d through a connection hole 19d formed in the insulating films 18a and 18b. The base electrode 20d is
For example, it is made of an Al-Si-Cu alloy.

An emitter region 24 is formed above the intrinsic base region 22a. In the emitter region 24,
For example, phosphorus or arsenic as an n-type impurity is introduced.
The emitter region 24 is electrically connected to an emitter extraction electrode 25 through a connection hole 19e formed in the insulating film 18b.

The emitter extraction electrode 25 is made of, for example, n-type polycrystalline silicon, and is electrically connected to the emitter electrode 20e through a connection hole 19f formed in the insulating film 18a. The emitter electrode 20e is made of, for example, Al-Si
-It consists of a Cu alloy. The insulating film 18a is made of, for example, B
It consists of PSG (Boron Phospho Silicate Glass). The insulating film 18b is made of, for example, a silicon oxide film.

Between p-channel MISFET Qp and n-channel MISFET Qn and n-channel MISFET
The trench isolation TI is formed in an element isolation portion between Qn and bipolar transistor Qb.

A deep groove 2 and a shallow groove 3 are formed in the element isolation portion. The deep groove 2 is formed in a partial region at the bottom of the shallow groove 3, and the bottom reaches the insulating layer 12b. A first buried insulating film 4 is buried in the deep groove 2, and a second buried insulating film 5 is buried in the shallow groove 3.
The upper surface of the buried insulating film 5 has a flat surface with no steps.

As described above, according to the first embodiment, after the deep groove 2 constituting the trench isolation TI is buried by the first buried insulating film 4 by a predetermined amount, the region where the deep groove 2 is formed is removed. Then, the shallow groove 3 is formed, and then the shallow groove 3 is filled with the second buried insulating film 5, and the upper portion of the second buried insulating film 5 in the shallow groove 3 is flattened. Thereby, the shallow groove 3 on the deep groove 2
The groove-shaped isolation TI is formed without forming a step on the upper part of the groove-shaped isolation TI and the peripheral shallow groove 3b, and without generating a steep step between the groove-shaped isolation TI and its peripheral region. It becomes possible.

After the deep groove 2 constituting the trench isolation TI is buried by the first buried insulating film 4 by a predetermined amount, the shallow groove 3 including the region where the deep groove 2 is formed is formed. Alternatively, since problems such as variations in the thickness of the resist film and halation in the photolithography process when forming the shallow groove 3 can be reduced, the dimensional margin between the deep groove 2 and the shallow groove 3 can be reduced, and The grooves 3 can be formed close to each other.

(Embodiment 2) FIGS. 11 to 19 are cross-sectional views of a main part of a semiconductor substrate showing a method of manufacturing a trench isolation according to another embodiment of the present invention in the order of steps.

In the first embodiment, the case where the filling material of the deep groove 2 formed in the semiconductor substrate 1 is a silicon oxide film has been described. However, the filling material is not limited to this and can be variously changed. It is.

Therefore, in the second embodiment, the case where the filling material of the deep groove 2 is, for example, mainly a polycrystalline silicon film will be described.

First, as shown in FIG. 2, a silicon oxide film 8, a silicon nitride film and a silicon oxide film 6 are sequentially etched using the photoresist pattern as an etching mask by the same manufacturing method as in the first embodiment. I do. Next, after the photoresist pattern is removed by ashing, the semiconductor substrate 1 is etched using the silicon oxide film 8 as an etching mask to form a deep groove 2. The depth of the deep groove 2 is, for example, about 3 μm, and the groove width is, for example, about 0.4 μm.

Next, as shown in FIG. 11, after the silicon oxide film 8 is removed using a hydrofluoric acid-based solution, an insulating film 26 made of, for example, a non-doped silicon oxide film is formed on the semiconductor substrate 1 by CVD. After being deposited by a method or the like, the deep groove 2 is buried in the upper layer of the insulating film 26 by depositing a buried semiconductor film 27 of, for example, a polycrystalline silicon film by a CVD method or the like. The thickness of the insulating film 26 is, for example, 5
It is about 0 nm. The thickness of the embedded semiconductor film 27 is
For example, it is about 500 nm.

At this time, since the buried semiconductor film 27 has good coverage, the buried semiconductor film 27 can be completely buried without forming a cavity in the deep groove 2 even if the aspect ratio of the deep groove 2 is small. It has become.

Subsequently, the embedded semiconductor film 27 is etched back. At this time, the insulating film 26 under the buried semiconductor film 27 functions as an etching stopper, so that etching on the semiconductor substrate 1 other than the region where the deep groove 2 is formed is stopped at the upper surface of the insulating film 26. Become. As a result, as shown in FIG. 12, the insulating film 26 and the buried semiconductor film 27 are buried in the deep groove 2.

Thereafter, as shown in FIG. 13, a photoresist film 11a is applied on the semiconductor substrate 1. At this time, since the surface of the photoresist film 11a becomes flat and the variation in film thickness is suppressed, the pattern of the photoresist film 11a can be formed by a normal photolithography technique without any problem.

Next, as shown in FIG. 14, the photoresist film 11a is patterned to form a photoresist pattern 11b from which the photoresist film 11a in the region where the shallow groove 3 is to be formed is removed. Using the photoresist pattern 11b as a mask, the silicon nitride film 7 and the silicon oxide film 6 are sequentially etched, and then the semiconductor substrate 1 and the buried semiconductor film 27 buried in the deep groove 2 are simultaneously etched. Thereby, as shown in FIG. 15, the shallow groove 3a in the region above the deep groove 2 and the shallow groove 3b in the other region can be formed. The depth d ₂ of the shallow groove 3 is
For example, it is about 0.35 to 0.4 μm.

Thereafter, the photoresist pattern 11b is removed, and then, as shown in FIG. 16, the exposed insulating film 26 is removed using a hydrofluoric acid-based solution.

Next, as shown in FIG. 17, a buried insulating film 28 made of, for example, a non-doped silicon oxide film is deposited on the semiconductor substrate 1 by a CVD method.
The buried insulating film 28 is filled in the shallow groove 3.

At this time, although the buried insulating film 28 has a low coverage, the buried insulating film 28 can be completely buried without forming a cavity in the shallow groove 3 because the aspect ratio of the shallow groove 3 is small. It is possible.

Next, as shown in FIG.
8 is polished by, for example, a CMP method, and the buried insulating film 28 deposited on the silicon nitride film 7 is removed, so that the buried insulating film 28 having a flat surface is buried in the shallow groove 3.

At this time, since the silicon nitride film 7 under the buried insulating film 28 functions as a stopper, the buried insulating film 2
The polishing of 8 is stopped at the surface of the silicon nitride film 7. This makes it possible to make the upper surface position of the buried insulating film 28 in the shallow groove 3 substantially equal to the surface position of the silicon nitride film 7 around the shallow groove 3.

Thereafter, the silicon nitride film 7 is removed by, for example, hot phosphoric acid treatment, so that the insulating film 26 buried in the deep groove 2 and the buried semiconductor film 2 are formed as shown in FIG.
7, and a trench isolation TI formed by the buried insulating film 28 buried in the shallow trench 3 is formed.

As described above, also in the second embodiment,
A step is not formed above the shallow groove 3a on the deep groove 2 and the shallow groove 3b around the shallow groove 3a, and the groove is formed without a steep step between the groove isolation TI and its peripheral region. It becomes possible to form the isolation TI. In addition, since problems such as variations in the thickness of the resist film and halation in the photolithography process when forming the deep groove 2 or the shallow groove 3 can be reduced, the dimensional margin between the deep groove 2 and the shallow groove 3 can be reduced. The deep groove 2 and the shallow groove 3 can be formed close to each other.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0086]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, when the conductor pattern is formed after the trench isolation is formed, the conductor film is left on the upper surface of the trench isolation or between the trench isolation and its peripheral region. Therefore, it is possible to form the trench isolation without lowering the yield of the semiconductor integrated circuit device.

According to the present invention, the deep groove and the shallow groove can be formed close to each other, so that the degree of integration of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor substrate showing a trench isolation according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the trench isolation according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the trench isolation according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the trench isolation according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the trench isolation according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the trench isolation according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the trench isolation according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the trench isolation according to one embodiment of the present invention;

FIG. 10 is a cross-sectional view of a main part of a semiconductor substrate showing a BiCMOS to which a trench isolation according to an embodiment of the present invention is applied;

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

FIG. 17 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

FIG. 19 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a trench isolation according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 deep groove 3 shallow groove 3a shallow groove 3b shallow groove 4 first buried insulating film 5 second buried insulating film 6 silicon oxide film 7 silicon nitride film 8 silicon oxide film 9 cavity 10 groove 11a photoresist film 11b photo Resist pattern 12 Semiconductor substrate 12a Support substrate 12b Insulating layer 12c Semiconductor layer 13a Channel stopper region 13b Channel stopper region 14a Element region 14b Element region 15a P-type semiconductor region 15b N-type semiconductor region 16 Gate electrode 17 Gate insulating film 18a Insulating film 18b Insulating Film 19a Connection hole 19b Connection hole 19c Connection hole 19d Connection hole 19e Connection hole 19f Connection hole 20a Electrode 20b Electrode 20c Collector electrode 20d Base electrode 20e Emitter electrode 21a Collector buried area 21b Collector area 21c Collector pull Region 22 base region 22a intrinsic base region 22b base lead region 23 base lead electrode 24 emitter region 25 emitter lead electrode 26 insulating film 27 buried semiconductor film 28 buried insulating film TI trench isolation Qp p-channel MISFET Qn n-channel MISFET Qbi bipolar transistor P p-channel MISFET formation region N n-channel MISFET formation region Bi bipolar transistor formation region d ₁ groove depth d ₂ shallow groove depth

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Toshiyuki Kikuchi 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. 3 Hitachi, Ltd. Device Development Center (72) Inventor Hideaki Kurosaki 6-16, Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi Ltd. Device Development Center (Reference) 5F032 AA09 AA34 AA44 AA45 AA47 AA77 AA78 DA02 DA23 DA33 DA34

Claims (14)

[Claims] 1. A semiconductor integrated circuit device having a trench-type isolation constituted by a buried insulating film or a semiconductor film buried in a deep groove and a buried insulating film buried in a shallow groove. A semiconductor integrated circuit device formed in contact with a partial region at the bottom of the shallow groove, wherein the upper surface of the buried insulating film in the shallow groove has a flat surface. 2. A semiconductor integrated circuit device having a trench isolation constituted by a semiconductor film buried in a deep groove and a buried insulating film buried in a shallow groove,
The deep groove is provided with an insulating film on the inner wall thereof and is formed in contact with a partial region of the bottom of the shallow groove, and the upper surface of the buried insulating film of the shallow groove has a flat surface. A semiconductor integrated circuit device characterized by the above-mentioned. 3. The semiconductor integrated circuit device according to claim 1, wherein an upper surface of said buried insulating film or said semiconductor film in said deep groove is substantially at the same position as a bottom of said shallow groove. Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein an upper surface of said buried insulating film or said semiconductor film in said deep groove is lower than an upper surface of said buried insulating film in said shallow groove. A semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein the upper surface of the buried insulating film or the semiconductor film in the deep groove is lower than the bottom of the shallow groove by an aspect ratio of 1 or less. A semiconductor integrated circuit device located on the side. 6. The semiconductor integrated circuit device according to claim 1, wherein said groove-shaped isolation is formed on a semiconductor substrate having an SOI structure in which a semiconductor layer is provided on an insulating layer, and said deep groove is formed on said insulating substrate. A semiconductor integrated circuit device, which is a groove formed so as to reach a layer. 7. The semiconductor integrated circuit device according to claim 1, wherein M is formed in an element formation region surrounded by said deep groove.
A semiconductor integrated circuit device comprising an IS transistor or a bipolar transistor. 8. A step of forming a deep groove for forming a trench isolation having an aspect ratio larger than 1 in a semiconductor substrate; and (b) a step of burying a buried insulating film in the deep groove by a predetermined amount. (C) partially including a region in which the deep groove is formed, and forming a shallow groove in the semiconductor substrate; and (d) depositing a buried insulating film on the semiconductor substrate. A step of flattening an upper portion of the buried insulating film buried in the shallow groove so that an upper surface position thereof is substantially equal to a plane position around the shallow groove. Manufacturing method. 9. A step of forming a deep groove for forming a trench isolation having an aspect ratio larger than 1 in a semiconductor substrate; and (b) forming an insulating film on an inner wall surface of the deep groove. (C) burying a semiconductor film in the deep groove, and (c) including partially forming a region in which the deep groove is formed, forming a shallow groove in the semiconductor substrate and the semiconductor film, and then exposing the insulating film. (D) depositing a buried insulating film on the semiconductor substrate, and then placing the upper surface of the buried insulating film buried in the shallow groove at an upper surface position around the shallow groove. Flattening the substrate so as to be substantially equal to the plane position of the semiconductor integrated circuit device. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein an upper surface of said buried insulating film or said semiconductor film in said deep groove is located at substantially the same position as a bottom of said shallow groove. A method for manufacturing a semiconductor integrated circuit device, comprising: 11. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein an upper surface of said buried insulating film in said deep groove or an upper surface of said semiconductor film is an upper surface of said buried insulating film in said shallow groove. A method for manufacturing a semiconductor integrated circuit device, which is located on a lower side. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein an upper surface of the buried insulating film or the semiconductor film in the deep groove has an aspect ratio of 1 or less than a bottom of the shallow groove. A method for manufacturing a semiconductor integrated circuit device, comprising: 13. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein said buried insulating film is a silicon oxide film. 14. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein said buried insulating film is a silicon oxide film, and said semiconductor film is a polycrystalline silicon film. Manufacturing method.