JP2000331493A - Semiconductor memory which can quickly access - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable writing data in an arbitrary physical address region being already erased by comparing a theoretical address value registered for each region with a theoretical address value given by an address signal line and accessing a region in which coincidence is detected. SOLUTION: A theoretical address value storing region 103 stores a theoretical address value of stored data of a data storing region 102. A theoretical address input 104 inputs a theoretical address value access-required by a host. An address value comparing circuit 105 compares a theoretical address value stored in the theoretical address value storing region 103 with a theoretical address value access-required by a host. A data storing region 102 in which coincidence is detected by the address value comparing circuit 105 is always one or less. Also, a flag register 111 sets a flag indicating that invalid data is stored and a flag indicating that erasing invalid data is finished and the region is in a writable state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device using a semiconductor memory as a storage medium, and more particularly to an address conversion and data transfer system for speeding up access, and a configuration for realizing the system.

[0002]

2. Description of the Related Art An electrically rewritable nonvolatile memory, particularly a flash memory, has attracted attention as a storage medium that can be replaced with a magnetic disk because of its characteristics such as resistance to shock and vibration, low power consumption, and high-speed access. .

However, a disadvantage of the semiconductor memory device is a capacity price ratio. Although the degree of integration of semiconductors has been improving year by year, the cost required for one bit is required for a semiconductor memory that requires at least one transistor for every one bit of storage and a magnetic disk that is simply magnetized on a magnetic plane. There is a big gap. Furthermore, the occurrence rate of defective bits in a semiconductor memory is higher than that in a magnetic disk, which causes a decrease in yield and makes it difficult to reduce the price. Therefore, conventionally, a defect relief process that can be used even in a semiconductor memory having a defect is performed in a storage device,
It improves the yield of memory chips and promotes price reduction.

As a method of relieving a defect, Japanese Patent Laid-Open No. 3-310848
Is disclosed. According to this, when a defective non-volatile memory is used as a storage medium, an area for replacing a defective area is provided, and information for identifying a defective location and its replacement location is stored. When accessing stored data to be performed, control is performed so that an alternative location is accessed without accessing a defective location. In this case, if a control unit such as a microprocessor exists, it is determined whether the area to be accessed does not correspond to the defective area, and if the area corresponds to the defective area, the assigned area is searched for and accessed. Control. For that purpose, it is necessary to provide an address conversion table indicating a defective area and its replacement area, and the microprocessor specifies an access location based on the address conversion table. Also, at the time of writing, check that the area to be written does not correspond to a defective area,
If the area is defective, writing is performed in another alternative area. At that time, in the flash memory, the erasing process of the sector to be written is necessary, and after the erasing process is completed, the stored data is transferred to the memory and the writing process is performed.

[0005]

In the above-mentioned prior art, the judgment and the address conversion processing are required by a control unit such as a microprocessor, and the processing time is required. In addition, at the time of write access, an operation of erasing previously stored data and then writing is required, regardless of whether the area is an available area or a defective area. In view of the above, the issue of high-speed access has not been considered,
Was a problem.

[0006]

SUMMARY OF THE INVENTION The object of the present invention is to increase the speed by determining whether or not there is a defect and performing a replacement process inside the memory chip. In addition, since it is not necessary to set an address in consideration of the correlation between the logical address specified by the host and the physical address indicating the actual storage location of the storage medium, it is possible to write in any erased physical address area in writing. Become like

More specifically, the memory device is divided into a plurality of areas each assigned a physical address, and data can be stored and read in a specific area according to an address value given from an address signal line. In a nonvolatile semiconductor memory electrically rewritable, a storage area in which a logical address value can be registered for each area, and an address for comparing the registered logical address value with a logical address value given from the address signal line And comparing means for accessing an area in which a match is detected by the address comparing means.

In the semiconductor memory device having the above-described nonvolatile semiconductor memory, when rewriting of a certain area is instructed, writing is performed in an area where erasing is performed, and at that time, the logical address value is set. The logical address value of the stored data is registered in an area where the logical address value can be registered.
Delete the registration of the stored data and the logical address value.

Further, in the semiconductor memory device having the above-described nonvolatile semiconductor memory mounted thereon, the total amount of the storage capacity of the mounted nonvolatile semiconductor memory is always larger than the storage capacity of the semiconductor memory device. An area where no stored data exists is secured, and when rewriting of a certain area is instructed, writing to an area where no stored data exists is performed.

In the semiconductor memory device having the nonvolatile semiconductor memory described above, the erasure of the stored data and the registered value of the logical address previously stored by rewriting a certain area can be performed by a host which has issued a rewriting instruction. On the other hand, after the completion of rewriting is reported.

Further, in the semiconductor memory device equipped with the above-mentioned nonvolatile semiconductor memory, it is necessary to rewrite a certain area so that previously stored data and registered values of logical addresses are to be erased. , A flag indicating that erasing has been performed is provided in each area, and a writing area selecting means for selecting an area indicating that erasing has been completed in new writing is provided.

[0012] Further, one or more nonvolatile semiconductor memories are provided.
It is also a semiconductor storage device provided with magnetic disk interface means.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of a mobile phone according to an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 shows an example of the configuration inside a semiconductor memory for realizing the present invention. In the figure, 101 is a memory chip,
102 is a data storage area divided into a plurality of areas inside the memory chip, 103 is a logical address value storage area for storing a logical address value of data stored in the data storage area 102, and 104 is a logical address value requested by the host to access. , An address comparison circuit for comparing the logical address value stored in the logical address storage area 103 with the logical address value 104 requested to be accessed by the host, and 106 for accessing the data storage area 102 A control circuit 107 is an access control signal output from the access control circuit 106. Usually, one is selected from a plurality of data storage areas, and the selected data storage area outputs stored data. 108, an access control signal applied to the memory chip; 109, a selection circuit for applying an access control signal 107 only to a data storage area that matches the result of the comparison circuit 105; 110, access data of the selected data storage area 102 Output.

It should be noted that the logical address value stored in the logical address storage area 103 is always unique in the same chip, and therefore, the address comparison circuit 105 always detects one or less data storage areas for matching ( None may be selected). If two logical address values stored in the logical address storage area 103 are the same in the same chip and the address is selected by the address bus line 104, a plurality of data storage areas are accessed. Priority is given to the size of physical address to prevent data collision due to
It is necessary to take measures such as preventing the current from flowing even when data outputs of different levels collide with open drains. In such a case, it is also effective to set a status register indicating an error, a signal output, and the like.

A flag register 111 includes a flag indicating that invalid data is stored,
Two flags are set to indicate that the erasure of invalid data has been completed and is in a writable state. The value of the flag register 111 is determined by the selection circuit 107 based on the address comparison.
In, when invalid data is stored, the access is masked. Further, in selecting a region to be written, it can be used to select only the region where erasing has been completed. A memory chip having the above configuration is realized, and according to the procedure shown in FIG. 2, high-speed access is possible. (1) is a data storage state in the memory chip at a certain point in time.
02, data of logical addresses 1 and 2 are stored in a and b, respectively, and the logical address storage area 103 stores address values of 1 and 2 respectively. Also
No data is stored in c and d, and they have been erased in advance. (2) indicates that the data of the logical address 3 which has not been written so far has been written in the state of (1), and 3 is stored in the data storage area of c.
Indicates that 3 has been written to the logical address storage area. At this time, since c has been erased in advance, it is only necessary to perform a write operation. (3) is (2)
Indicates that the already written 1 has been rewritten. The writing is performed on the area d where nothing is written. At this time, only the writing is performed without performing the erasing operation. (4) is an operation performed subsequent to (3), in which data written to a, which has become invalid by writing the logical address 1 to d, is erased. This operation is performed in parallel with (3) if it can be performed in parallel with the writing of the data of the logical address 1 to d. For this purpose, if a plurality of chips are used, a and d may be assigned to be different chips.

If this is not done, the process is performed after the writing of the data at the logical address 1 to d has been completed and the host has been notified of the end of the processing. On the other hand, at the time of reading, an address storage area 103 storing an address value matching the access logical address value specified by the address bus line 104 is detected, and the corresponding data storage area 10 is detected.
2 is output. By the above operation, the time required for the erasing operation does not affect the writing performance in the writing, so that the writing performance is improved, and at the same time, the physical address where the data is stored is calculated by a microprocessor or the like in the reading. Since reading and searching time is not required, read performance is improved.
Even if a memory including a defective bit is used, no problem occurs unless the area is selected at the time of writing, so that the yield of the memory is also improved.

FIG. 3 is an overall configuration diagram of a storage device using the present memory chip. In the figure, reference numeral 301 denotes a storage device using the memory chip of the present invention as a storage medium, and 302 denotes a storage device 301.
303, a control bus and signals of an information device to be a host
Is an interface circuit that sends and receives registers and signals for interfacing with the host.For example, a general ATA interface as a magnetic disk interface and a general SC as a peripheral device interface
Interfaces such as SI and serial USB are conceivable. 304 is a memory chip shown in FIG. 1, 305 is a buffer memory for temporarily storing data from the host and data read from the storage device, 306 is access data of the buffer memory 305 and the interface circuit 303, and the memory chip 304 307 is a transfer control circuit for controlling the transfer of the memory chip 30 storing the data of the logical address designated by the host.
4 is a chip selection circuit for specifying and controlling access. Next, the read operation will be described with reference to FIG.

The host specifies a logical address corresponding to data to be accessed by the control signal 302 (a).
The interface circuit 301 receiving this sends the logical address to the chip selection circuit 307. Chip selection circuit 3
In 07, the chip is specified from the logical address value (b)
However, in the simplest method, the memory chip is identified by decoding the upper bits of the logical address value. However, as described above, when rewriting for the purpose of speeding up, when assigning a memory chip different from the memory chip that had been stored so far, it is necessary to provide a chip selection function inside the memory chip. In such a case, the chip selection circuit 307 becomes unnecessary. Of course, the chip circuit 307 is unnecessary in an apparatus using only one chip. In order to provide the function of chip selection inside the memory chip, it can be realized by providing the number of address input bits and the number of bits of the logical address storage area extra by the encode bits of the number of chips to be used.

For example, if one memory chip has a capacity of 1K data areas, the number of address bits is 1
0 bits is necessary and sufficient, but when considering simultaneous use of 4 chips, 12 address bits are provided. The number of bits of the logical address storage area is also 12 bits, and is registered as a 12-bit address value when storing data. This allows 4 bits for 12-bit logical addressing.
One data storage area can be specified from the 4K data storage area for chips. In this case, the logical address values of the logical address storage areas of all the areas of the memory chip used must be different. As described above, when the data storage area to be accessed is specified rather than selected, the data in the data storage area is accessed. This access is performed by the memory chip automatically specifying the storage area internally (c). Then, the automatically read data is transferred from the memory chip 304 to the buffer memory 305 under the control of the data transfer control circuit 306 (d).

At this time, adding a function of performing error detection and correction to improve data reliability is an effective method as a storage device. Of course, in this case, it is necessary to secure an area for storing error correction and detection codes in addition to the data storage area of the memory chip, and to store the code calculated at the time of data storage. The read data transferred to and stored in the buffer 305 is transferred to the host through the interface circuit by the transfer control circuit (e).

Thus, the reading process is completed. On the other hand, in the write processing, designation of a logical address value to be accessed from the host (f) and write data are transferred (g).
The transferred data is stored in the buffer memory 305,
During that time, the chip selection circuit 307 specifies a chip from the logical address value (h). However, when the chip selection cannot be simply performed based on the address value as in the case of the read access, a method of selecting a memory chip based on a certain rule is preferable. For example, if the memory chips are sequentially circulated and assigned in the writing order, it is possible to prevent the rewriting from being concentrated on some of the memory chips and the deterioration to progress unevenly. The memory chip is specified, and the selected memory chip selects one of the erased areas (i) and stores the data sent from the buffer 305 (j). If possible, in parallel with this, an erasing operation is performed on the data storage area where the previous data of the same logical address value has been written (k). If the parallel operation is not possible, the erase operation is performed after the previous write operation is completed (m). In this case, by notifying the host of the end of the write operation when the write operation is completed (l), it is possible to reduce the time required for the erase operation of the write processing. In order to ensure that writing is performed on the previously erased portion, a setting is made so that the storage capacity actually present on the storage medium is larger than the storage capacity recognized by the host, Even if writing is performed for the entire capacity from the host, when rewriting is performed, by ensuring that an area that has already been erased exists, the writing can be speeded up reliably.

However, the problem here is that the host may perform termination processing such as shutting off the power supply when the writing processing is completed during the erasing processing. . If the power is cut off during the erasing operation, the stored data is in an ambiguous state, and it is unclear what data will be read next time.

This is particularly serious for data stored in the logical address storage area. In other words, there is a possibility that the reliability of the logical address value is lost, and the logical address value coincides with the address value of another normal area, thereby causing an access obstacle. For this reason, if the power was shut down during the erase operation or something similar occurred and the erase was not completed, the flag indicating this was set in that area, and the stored data was rewritten and invalidated The above problem can be solved by combining the flag with a flag indicating that is used as an identifier for subsequent access (see FIG. 7). As shown in FIG. 7, for example, an area where a flag is set is not subjected to address coincidence detection, and erasure is performed again at the time of initial processing at power-on so that erasure is completely performed. The method is effective.

It is also necessary to consider the specification of the writing location. In other words, at the time of writing, it is necessary to select an area that is different from the previous storage area, and in which other data has not been written and that has already been erased.
A simple method is to set a flag in an area where erasing is performed, use the flag for selection of a writing area, and search and select from a smaller physical address.

However, according to this method, a region having a small physical address is frequently selected, and the progress of deterioration due to the frequency of use is biased. Therefore, for example, if the search is started from the area where the data of the logical address value has been stored before, it can be expected that the data is used uniformly.

In the memory chip of the present invention, if the minimum unit of erasable data is assumed to be equal to the unit capacity of data handled by the host with respect to the storage device, the control is very simple and the control is simplified. In this case, the present invention can be applied. In particular, for the purpose of reducing the memory chip area, it is conceivable that the minimum unit of data that can be erased in the memory is larger than the data unit handled between the hosts. However, although the control becomes complicated, only a part of the area that can be erased is rewritten. That is enough. FIG. 5 shows a configuration assuming such a memory. 501
Is a memory chip whose capacity is four times as large as the data capacity handled between the hosts, 502 is the smallest erase unit of the memory chip 501, 503 is the smallest unit of data handled between hosts, and 504 is the smallest unit of data handled between hosts. This is a logical address storage area provided for each minimum unit 503. In the data write from the host, the write is performed with the capacity of the data unit 503, so it is necessary to register the logical address value for each write unit. Therefore, the address comparison at the time of read access must also be performed in this unit. When rewriting is performed, since the rewriting is performed in the host unit 503, only a part of the minimum erasing unit 502 is erased. However, since the data cannot be partially erased, the data stored in the minimum erasing unit 502 is temporarily read out and saved, and the area is erased. Must be written back.

FIG. 6 shows an example of the processing. In the figure, since the logical address 3 has been rewritten and newly written in another area, the data at the address 3 of this block is invalid and unnecessary, and only this part is erased. Thereafter, the writable area is used as a new writing area when rewriting another logical address. For this reason, it is premised that a memory chip capable of partially performing writing a plurality of times at different locations when one entire erasing area is in an erasing state.

[0028]

According to the present invention, even when a memory having a defective bit or a defective area is used as a storage medium, the time required for erasing can be saved in writing, and a sector in which a defect has occurred can be accessed in reading. You can access data without any time-consuming processing such as address conversion and address search without performing
Performance can be improved. Further, in the address conversion, since complicated processing is not required, there is no need for an external means for executing complicated processing such as a microprocessor, and there is an effect that the configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is an example of the internal configuration of a memory chip of the present invention.

FIG. 2 shows an example of a writing procedure to a block in a memory chip.

FIG. 3 is a block diagram of a storage device using a flash memory chip of the present invention.

FIG. 4 is a time chart at the time of access between hosts.

FIG. 5 is a configuration example of a chip in which a minimum erasing capacity unit of a memory chip is larger than a minimum unit of data handled between hosts;

FIG. 6 is a diagram illustrating a rewriting process when one erasing unit of a memory corresponds to four units handled by the host;

FIG. 7 is an example of using a flag provided for each area.

[Explanation of symbols]

101: memory chip, 102: data storage area, 10
3 ... Logical address storage area, 104 ... Logical address input, 105 ... Address value comparison circuit, 107 ... Memory control signal, 109 ... Access selection circuit, 110 ... Read data, 301 ... Storage device, 304 ... Memory chip, 30
5 data buffer 306 transfer control circuit 307
Chip selection circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Katsumi Ouchi 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside System Development Laboratory, Hitachi, Ltd. (72) Takayuki Tamura 1099 Ozenji Temple, Aso-ku, Aso-ku, Kawasaki City, Kanagawa Prefecture Hitachi, Ltd. System Development Laboratory (72) Inventor Kazuo Nakamura 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5B025 AD01 AD04 AD05 AD08 AE05 5B060 AA02 AA14 AB28 AC11 5L106 AA10 CC09 CC16

Claims (5)

[Claims] A plurality of areas each of which is assigned a physical address, wherein data can be stored and read in a specific area in accordance with an address value given from an address signal line; A rewritable nonvolatile semiconductor memory, comprising: a storage area in which a logical address value is registered for each of the areas; and an address comparing means for comparing the registered logical address value with a logical address value given from the address signal line. A nonvolatile semiconductor memory, comprising: accessing a region where a match is detected by said address comparing means. 2. The semiconductor memory device according to claim 1, wherein when rewriting is instructed to said area, writing is performed in an area where erasing is performed. The logical address value of the storage data is registered in the area where the logical address value can be registered. In the area where the storage data of the logical address value has been stored before, the storage data and the registration of the logical address value are deleted. A semiconductor memory device characterized by the following. 3. The semiconductor memory device according to claim 2, wherein the total amount of storage capacity of said non-volatile semiconductor memory mounted is larger than the storage capacity of said semiconductor storage device, so that an area where stored data does not exist. Is secured, and when rewriting to the area is instructed,
Semiconductor memory device for writing data in an area where the stored data does not exist 4. A semiconductor memory device having a nonvolatile semiconductor memory according to claim 2, wherein the rewriting of the area causes the previously stored data and the registered value of the logical address to be erased. A semiconductor memory device, which is performed after reporting completion of rewriting to a host that has performed rewriting. 5. The semiconductor memory device according to claim 2, wherein the stored data and the registered value of the logical address stored previously are to be erased by rewriting the area, and erasing is performed. Semiconductor memory mounted with a non-volatile semiconductor memory, wherein a flag indicating that the erasure has been completed is provided in each area, and an area indicating that erasure has been completed is selected in a new writing operation. apparatus.