JP2000330955A - Multiprocessor system and multiprocessor initializing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To securely actuate a radio communication device even if a fault occurs to an initialization flag. SOLUTION: In case of fault occurrence to a initialization flag, the multiprocessor system is provided with multiple initialization flags. If a fault occurs to an initialization flag A107, a flag fault detection part 104 detects the fault, a flag switching part 105 instructs each processor 101 to refer to an initialization flag B108, and each processor 101 switches the initialization flag to be referred to from the initialization flag A107 where the fault is occurring to the initialization flag B108 which operates normally according to the indication.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system and a multiprocessor system initialization method used for a wireless communication device.

[0002]

2. Description of the Related Art In recent years, as the limit of speeding up by a single processor becomes clear in wireless communication devices and the like,
Multiprocessor systems using parallel processing are becoming mainstream.

In a conventional multiprocessor system, initial processing for initial setting of a register, activation of an operation program, and the like when the power of a wireless communication device or the like is turned on is performed as follows.

Hereinafter, an initial process performed in a conventional multiprocessor system will be described with reference to FIG. FIG. 3 is a main block diagram showing a schematic configuration of a conventional multiprocessor system.

[0005] In FIG. 3, each processor 11 of processors 1 to n controls a wireless communication device by parallel processing. Further, the initial processing is performed by one of the processors 11.
It is done by one.

The control unit 12 assigns the right to use the common bus 13 to each processor 11. The shared memory 14 has an initialization flag 15 and the like, and stores data for controlling and operating the wireless communication device. The initialization flag 15
This is a flag for determining the processor that performs the initial processing, and takes a state of, for example, “OFF” or “ON”.

Next, the operation of the initial processing in the multiprocessor system having the above configuration will be described with reference to FIG. When the power of the wireless communication apparatus is turned on, each processor 11 sets the initialization flag 15
See In this case, each processor 11 outputs a request signal to the control unit 12 before using the common bus 13. The control unit 12 assigns the right to use the common bus 13 to each processor 11 in accordance with a predetermined priority according to the input of the request signal.

Since only one processor is required for the initial processing, one processor for performing the initial processing is determined. This determination method is performed as follows by each processor 11 referring to the initialization flag 15.

When the power of the wireless communication apparatus is turned on, the initialization flag 15 is "OFF" as an initial state.
Once referenced from the processor, it will be “ON” thereafter
Will remain.

Each processor 11 refers to the initialization flag 15 twice in the order in which the right to use the common bus 13 is assigned. And the first reference result is “OFF”
And the processor whose second reference result is "ON" performs the initial processing. In both cases, the reference result is "O"
The other processors that have become "N" do not perform the initial processing.

As described above, instead of determining the processor that performs the initial processing in accordance with the result of one reference,
The processor that performs the initial processing according to the reference result of the first time is determined by a plurality of processors when a failure occurs in the initialization flag 15 and the initialization flag 15 does not switch from “OFF” to “ON”. Is to prevent the initial processing from being performed.

As described above, according to the conventional multiprocessor system, by using the initialization flag, one processor for performing the initial processing is determined and the initial processing is performed.

[0013]

However, in the conventional multiprocessor system, a failure occurs in the initialization flag, and the initialization flag is changed from "OFF" to "ON".
, The reference results from all processors are both turned off twice. Further, a failure occurs in the initialization flag in the “ON” state, and after the power is turned off, the initialization flag is in the initial state “O”.
If it does not return to "FF", the reference results from all processors will be "ON" both times.

As described above, when a failure occurs in the initialization flag and the switching between “OFF” and “ON” is not performed, the processor for performing the initial processing cannot be determined. Since the process is not performed, there is a problem that the wireless communication device does not start even when the power is turned on.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a multiprocessor system and a multiprocessor system initialization method capable of reliably starting a wireless communication device even when a failure occurs in an initialization flag. The purpose is to provide.

[0016]

The gist of the present invention is to provide a multiprocessor system with a plurality of initialization flags in preparation for the occurrence of an initialization flag failure.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multiprocessor system according to a first aspect of the present invention is referred to by each processor in a system having a plurality of processors, and when first referred to, from a first state to a second state. Storage means for storing a plurality of flags that transits to a state, detection means for detecting the occurrence of a failure in the plurality of flags, Switching control means for performing switching control so that each of the processors refers to the flag.

According to this configuration, the multiprocessor system has a plurality of flags in preparation for the occurrence of a flag failure, so that the initial processing can be reliably performed even when a failure occurs in the flag.

[0019] In the multiprocessor system according to the second aspect of the present invention, in the first aspect, each processor refers to the reference flag a plurality of times, and the detecting means determines when the reference results are all in the same state. A configuration for detecting that a failure has occurred in the reference flag is employed.

According to this configuration, in preparation for the occurrence of a flag failure, the multiprocessor system includes a plurality of flags, and when a reference result indicating that a failure has occurred in the flag is notified from the processor, the flag is set to the flag. Since the occurrence of a failure is detected and the flag is switched and used, the initial processing can be reliably performed even when a failure occurs in the flag.

[0021] The multiprocessor system according to the third aspect of the present invention is the multiprocessor system according to the first aspect, wherein the processor notifies the reference flag that the reference flag operates normally before a given time elapses. The detection means employs a configuration for detecting that a failure has occurred in the reference flag when the notification has not been received at the time when the predetermined time has elapsed.

According to this configuration, in preparation for the occurrence of a flag failure, the multiprocessor system includes a plurality of flags, and when a reference result indicating that the flags are operating properly is not notified from the processor, the flags are set. Since the failure is detected and the flag is switched and used, the initial processing can be reliably performed even when the failure occurs in the flag.

A mobile communication base station apparatus according to a fourth aspect of the present invention employs a configuration including the multiprocessor system according to any one of the first to third aspects.

A mobile communication base station controller according to a fifth aspect of the present invention employs a configuration including the multiprocessor system according to any one of the first to third aspects.

According to these configurations, since the multiprocessor system is provided which can reliably perform the initial processing, the mobile communication base station apparatus and the mobile communication base station control apparatus can be reliably started. .

According to a sixth aspect of the present invention, there is provided a multiprocessor system initializing method, wherein one of a plurality of flags which transits from the first state to the second state when first referred to by one processor. A detection step of detecting the occurrence of a failure in the reference flag in accordance with a reference result of the reference flag, and a switching control step of performing control to switch a flag other than the reference flag to the reference flag when the failure is detected And each processor refers to the reference flag to determine one processor that performs the initial processing.

According to this method, the flag is switched and referred to when a failure occurs in the flag. Therefore, even when a failure occurs in the flag, the initial processing can be reliably performed.

In the multiprocessor system initialization method according to a seventh aspect of the present invention, in the sixth aspect, each processor refers to the reference flag a plurality of times and detects when all the reference results are in the same state. In the step, the occurrence of a failure in the reference flag is detected.

According to this method, when a reference result indicating that a failure has occurred in the flag is notified from the processor, the occurrence of the failure in the flag is detected, and the flag is switched to be referred to. In this case, the initial processing can be performed reliably.

[0030] In the multiprocessor system initialization method according to an eighth aspect of the present invention, in the sixth aspect, in the detection step, the reference flag may operate normally before a given time elapses in the detection step. When the notification is not received from the processor, it is detected that a failure has occurred in the reference flag.

According to this method, when a reference result indicating that the flag is operating normally is not notified from the processor, the occurrence of a flag failure is detected and the flag is switched to be referred to. Even in the case of occurrence, the initial processing can be reliably performed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Embodiment 1) The multiprocessor system according to Embodiment 1 of the present invention has a plurality of initialization flags, and a case where a reference result indicating that a failure has occurred in the initialization flag is output from each processor. Then, the occurrence of a failure in the initialization flag is detected, and the initialization flag is switched and used.

Hereinafter, the initial processing performed in the multiprocessor system according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a main block diagram showing a schematic configuration of a multiprocessor system according to Embodiment 1 of the present invention.

In FIG. 1, each processor 101 of the processors 1 to n controls the radio communication device by parallel processing. The initial processing is performed by one of the processors 101.

The control unit 102 assigns the right to use the common bus 103 to each processor 101. The control unit 10
2 is a flag failure detection unit 104 and a flag switching unit 10
5 for detecting the occurrence of a failure in the initialization flag and instructing the switching of the reference flag. The flag failure detection unit 104 detects occurrence of a failure in the initialization flag based on a signal output from each processor. When a failure occurs in one initialization flag, the flag switching unit 105 issues a reference switching instruction to each processor 101 so as to refer to another initialization flag.

The shared memory 106 stores a plurality of initialization flags (here, an initialization flag A 107 and an initialization flag B).
108, and also stores data for controlling and operating the wireless communication device.

The initialization flag A 107 and the initialization flag B 108 are flags for determining a processor that performs an initialization process, and assume, for example, "OFF" and "ON". Here, each processor refers to the initialization flag A107 as a reference flag.

Next, the operation of the initial processing in the multiprocessor system having the above configuration will be described with reference to FIG. When the power of the wireless communication apparatus is turned on, each processor 101 first refers to the initialization flag A107 of the shared memory 106. In this case, each processor 1
01, before using the common bus 103,
Outputs a request signal to

The control unit 102 assigns the right to use the common bus 103 to the processors 1 to n in the order in which the request signals are output. Now, here, a request signal is output from the processor 1 in the order of the processor n, and the common bus 10
The right to use 3 is assigned in the order of processor 1 to processor n. When request signals are simultaneously output from a plurality of processors, the control unit 1
In step 02, the right to use the common bus 103 is assigned to each processor 101 in accordance with the priority set in the control unit 102 in advance. Here, it is assumed that the priorities are set in the order of processor 1 to processor n. Therefore, here, the initialization flag A107 is referred to in order from the processor 1 to the processor n.

Since only one processor is required for initial processing, one processor for initial processing is determined. This determination method is performed as follows by each processor 101 by referring to the initialization flag A107.

The initialization flag A107 and the initialization flag B108 are "OFF" as an initial state when the power of the wireless communication apparatus is turned on, and once referred to by the processor, remain "ON" thereafter. Become. This operation is a normal operation of the initialization flag.

Each processor 101 first sets an initialization flag A107 in the order of processor 1 to processor n.
Refer to it twice. And the first reference result is “OF
The processor 1 which is the processor whose F is “ON” and whose second reference result is “ON” performs the initial processing.
Processors 2 to n, which are other processors whose reference result is "ON" at all times, do not perform the initial processing.

Further, each processor 101 outputs a signal indicating the reference result of the initialization flag A 107 to the flag failure detection unit 104 in the reference order.

Here, a failure occurs in the initialization flag A107, and the initialization flag A107 is changed from "OFF" to "ON".
, The reference results from all processors are both turned off twice. In this case, if at least one of the processors has a reference result “OFF” twice,
It can be determined that a failure has occurred in the initialization flag A107. Therefore, when the processor 1 first outputs the signal indicating the reference result of the initialization flag A107, the flag failure detection unit 104 determines that the reference result is “2 times”.
If “OFF”, it is detected that a failure has occurred in the initialization flag A 107, and a detection signal is output to the flag switching unit 105.

In the "ON" state, the initialization flag A10
7 has failed, and after the power is turned off, the initialization flag A10
If 7 does not return to the initial state of "OFF", the reference results from all processors will be "ON" both times. Therefore, even when the reference results from all the processors are both turned "ON" twice, it can be determined that a failure has occurred in the initialization flag A107. Therefore, the flag failure detection unit 10
Reference numeral 4 denotes an initialization flag A if the signals indicating the reference results output from the processors 1 to n are both "ON" twice.
It detects that a failure has occurred in 107 and outputs a detection signal to flag switching section 105.

When the detection signal is output from the flag failure detection unit 104, the flag switching unit 105 instructs each processor 101 to refer to the initialization flag B108. In accordance with this instruction, each processor 101 changes the initialization flag to be referenced from the initialization flag A 107 in which the failure has occurred to the initialization flag B which operates normally.
Switch to 108.

Each processor 101 refers to the initialization flag B108 in the same operation as referring to the initialization flag A107, and the first reference result is "OFF".
Then, the processor 1 which is the processor whose second reference result is "ON" performs the initial processing.

In the first embodiment, the occurrence of a failure in the reference flag is detected in accordance with the result of two references to the reference flag. However, this merely indicates the most efficient number of times. Therefore, the number of times is not limited to two and may be any number of times.

As described above, according to the present embodiment, in preparation for the occurrence of a failure in the initialization flag, the multiprocessor system has a plurality of initialization flags, and the reference result indicating that the failure has occurred in the initialization flag. Is output from each processor, the occurrence of a failure in the initialization flag is detected, and the initialization flag is switched and used. Therefore, even when a failure occurs in the initialization flag, the initial processing can be performed reliably. .

(Second Embodiment) A multiprocessor system according to a second embodiment of the present invention has substantially the same configuration as that of the first embodiment, and indicates that the initialization flag is operating normally. The difference is that when a result is not output from each processor, the occurrence of a failure in the initialization flag is detected.

Hereinafter, a multiprocessor system according to the second embodiment of the present invention will be described with reference to FIG.
FIG. 2 is a main block diagram showing a schematic configuration of a multiprocessor system according to Embodiment 2 of the present invention. However, components having the same configuration as in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

The control unit 102 includes a timer 201, a flag failure detection unit 202, and a flag switching unit 105, and detects the occurrence of a failure in the initialization flag and instructs the switching of the reference flag. The timer 201 is a timer that starts when the power of the wireless communication apparatus is turned on, and has an arbitrary fixed time. The flag failure detection unit 202 detects occurrence of a failure in the initialization flag based on a signal output from each processor.

Next, a method for detecting the occurrence of a failure in the initialization flag in the multiprocessor system having the above configuration will be described with reference to FIG. Each processor 101
Among them, the processor 1 in which the first reference result is “OFF” and the second reference result is “ON”, the flag failure detection unit 2 notifies that the processor for performing the initial processing has been determined.
02 is notified. Based on this notification, the flag failure detection unit 202 determines that a failure has not occurred in the initialization flag A107, and resets and restarts the timer 201.

Here, a failure occurs in the initialization flag A107, and the initialization flag A107 is changed from "OFF" to "ON".
, The reference results from all processors are both turned off twice. If a failure occurs in the initialization flag A107 in the “ON” state and the initialization flag A107 does not return to the initial state “OFF” after the power is turned off, the reference result from all processors is returned. But twice "O"
N ”. In these cases, since the processor that performs the initial processing is not determined, the flag failure detection unit 202 does not receive the above notification.

In the absence of the above notification, the flag failure detection unit 202 determines that the initialization flag A10 has expired upon expiration of the timer 201 that is started when the power of the wireless communication apparatus is turned on.
7 is detected as having failed, and a detection signal is output to the flag switching unit 105. Further, the flag failure detection unit 202
Resets the timer 201 and restarts it.

As described above, according to the present embodiment, in preparation for the occurrence of a failure in the initialization flag, the multiprocessor system has a plurality of initialization flags, indicating that the initialization flag is operating normally. When the reference result is not output from each processor, the occurrence of the initialization flag failure is detected,
Since the initialization flag is switched and used, even when a failure occurs in the initialization flag, the initialization process can be reliably performed.

In the first and second embodiments, the multiprocessor system has two initialization flags. However, the present invention is not limited to this. Depending on the frequency,
A configuration having three or more initialization flags may be adopted.

Further, in the first and second embodiments, for convenience, the initialization flags are referred to in the order from the processor 1 to the processor n, but the present invention is not limited to this reference order. In the first embodiment and the second embodiment, the priorities are set in order from the processor 1 to the processor n for the sake of convenience. However, the priorities are not limited to the priorities.

Further, the multiprocessor system of the above embodiment can be applied to a base station device or a base station control device in a mobile communication system. In this case, since the mobile communication base station device and the mobile communication base station control device are equipped with a multiprocessor system capable of reliably performing the initial processing, it is possible to surely start those devices.

[0060]

As described above, according to the present invention,
Even when a failure occurs in the initialization flag, it is possible to reliably start up the wireless communication device.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing a schematic configuration of a multiprocessor system according to a first embodiment of the present invention;

FIG. 2 is a main block diagram showing a schematic configuration of a multiprocessor system according to a second embodiment of the present invention;

FIG. 3 is a main block diagram showing a schematic configuration of a conventional multiprocessor system.

[Explanation of symbols]

 Reference Signs List 101 processor 1 to n 102 control unit 103 common bus 104 flag failure detection unit 105 flag switching unit 106 shared memory 107 initialization flag A 108 initialization flag B 201 timer 202 flag failure detection unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Masafumi Yamaguchi 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Tomonori Kumagai 4-1-1 Kamikodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Fujitsu Co., Ltd. (72) Inventor Seiya Yamazaki 4-1, 1-1 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside (72) Inventor Ken Yonekura 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu F term in reference (reference) 5B045 AA00 HH01 HH06 JJ01 JJ12 JJ25 JJ44

Claims (8)

[Claims] 1. A storage means for storing a plurality of flags which are referred to by each processor in a system having a plurality of processors and transition from a first state to a second state when first referenced, and Detecting means for detecting the occurrence of a flag failure, and performing switching control so that each processor refers to a flag other than the reference flag when a failure occurs in the reference flag referenced by each processor. And a control means. 2. The method according to claim 1, wherein each processor refers to the reference flag a plurality of times, and the detecting means detects that a failure has occurred in the reference flag when all the reference results are in the same state. The multiprocessor system according to claim 1, wherein 3. A timer means for stopping when a processor informs that a reference flag operates normally before a given time elapses, and wherein the detecting means comprises: 2. The multiprocessor system according to claim 1, wherein when the time has elapsed, when the notification is not received, it is detected that a failure has occurred in the reference flag. 4. A mobile communication base station apparatus comprising the multiprocessor system according to claim 1. Description: 5. A mobile communication base station controller comprising the multiprocessor system according to claim 1. Description: 6. A failure of the reference flag according to a reference result of one of a plurality of flags that transitions from the first state to the second state when first referenced by one processor. And a switching control step of performing control to switch a flag other than the reference flag to a reference flag when the occurrence of the failure is detected, wherein each processor sets the reference flag. A multiprocessor system initialization method for determining one processor that performs initial processing by referring to the processor. 7. Each processor refers to a reference flag a plurality of times, and when all reference results are in the same state, detects in the detection step that a failure has occurred in the reference flag. The method for initializing a multiprocessor system according to claim 6. 8. The detecting step detects that a failure has occurred in the reference flag when there is no notification from the processor that the reference flag operates normally before a given time elapses. 7. The method for initializing a multiprocessor system according to claim 6, wherein: