JP2000324403A - Solid-state image pickup unit and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate much time for restart in the case of releasing a stand-by operation mode. SOLUTION: A frequency dividing circuit 8 and a decoder 11 are provided in a driving timing generation circuit 6. A serial data generating part 13 is provided in a signal processing circuit 5. In stand-by operation mode, the circuit 8 frequency-divides an oscillation clock from an oscillation circuit 7 into eight, based on a frequency dividing ratio control signal obtained by decoding serial data from the part 13 by the decoder 11 to make a reference clock. Thus, power consumption is suppressed by operating by 1/4 frequency in normal operation mode. When the stand-by operation mode is released, the part 13 generates such serial data as equalizes electric charge storing times before and after releasing the stand-by operation mode. Thus, the exposure and white balance of a video signal at the time of releasing the stand-by operation mode are stabilized to unnecessitate much time for restart.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device using a solid-state imaging device such as a CMOS (complementary metal oxide semiconductor) image sensor.

[0002]

2. Description of the Related Art In a camera system using a solid-state imaging device such as a CCD (Charge Coupled Device) or a CMOS image sensor, low power consumption is an important issue. In particular, it is a particularly important issue in a camera system used for a portable device driven by a battery, an electronic still camera, a camera-integrated VTR (video tape recorder), and the like.

In the case of a camera system for portable equipment,
For example, a state in which it is not necessary to operate the solid-state imaging device, such as a state in which an image is being confirmed, a state in which a video signal is being captured, or a state in which the captured video signal is being processed by a subsequent device, in other words, For example, there is a standby state in which the process waits until another process ends.

Conventionally, in order to reduce power consumption in the above-described standby state, the operation of the solid-state imaging device is stopped to cope with the problem. That is, a camera system using a solid-state imaging device such as the CCD or CMOS image sensor includes a sensor unit having the solid-state imaging device, a driving pulse timing generation unit that generates a sensor driving pulse for driving the sensor unit, And a signal processing unit for converting an output signal from the video signal into a video signal. The operation of the solid-state imaging device is stopped by stopping the operations of the timing generation unit and the signal processing unit.

[0005]

However, in the camera system using the above-mentioned conventional solid-state imaging device, in order to reduce the power consumption in the standby state, the operations of the timing generation unit and the signal processing unit are stopped (that is, the operation of the signal processing unit is stopped). To stop the camera system), there are the following problems.

That is, even if the operation of the solid-state imaging device is stopped, electric charges continue to be accumulated in the photodiodes constituting the solid-state imaging device. Therefore, the level of the output signal from the solid-state image sensor eventually saturates,
If you restart the camera system in such a state, the screen will be distorted (for example, the screen will be blank white)
It is. Therefore, when the camera system is restarted, it takes time for the control of the exposure amount and the white balance to stabilize, so that the output video signal cannot be used immediately. That is, in the conventional camera system, there is a problem that it takes time to restart.

SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device which does not require a long time to restart when switching from a standby operation mode to a normal operation mode.

[0008]

According to a first aspect of the present invention, a solid-state imaging device is driven by a drive pulse generated by a drive timing generation circuit.
In a solid-state imaging device that processes an imaging signal obtained by the solid-state imaging device by a signal processing circuit, control data for a normal operation mode is generated during a normal operation mode,
A control data generating unit for generating control data for the standby operation mode during the standby operation mode; an oscillation circuit; and a normal operation mode, for generating the original clock from the oscillation circuit based on the control data for the normal operation mode. On the other hand, in the standby operation mode, the original clock from the oscillation circuit is divided by the second division ratio larger than the first division ratio based on the control data for the standby operation mode. A frequency dividing circuit for generating a reference clock for the drive timing generating circuit and the signal processing circuit, wherein the control data includes shutter data, and the shutter data is used in the normal operation mode and the standby operation mode. The solid-state imaging device is set so that the charge accumulation time is the same between the two. Based on the data, a drive pulse is generated such that the same charge accumulation time is obtained in the normal operation mode and in the standby operation mode.

According to the above configuration, in the standby operation mode, the frequency dividing circuit divides the original clock by the second frequency division ratio larger than the first frequency division ratio in the normal operation mode to generate the reference clock. . Thus, in the standby operation mode, the drive timing generation circuit and the signal processing circuit are driven by the reference clock having a lower frequency than the reference clock in the normal operation mode, and power consumption in the standby operation mode is suppressed.

Further, a drive pulse for the solid-state image sensor is generated by a drive timing generation circuit based on shutter data set so that the charge accumulation time of the solid-state image sensor in the two operation modes is equalized. . Thus, the solid-state imaging device is driven such that the charge accumulation time in both operation modes is the same.

According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the frequency dividing circuit is built in the drive timing generating circuit.

According to the above configuration, since the frequency dividing circuit is built in the drive timing generating circuit, the number of components is smaller than when the frequency dividing circuit is provided alone.

According to a third aspect of the present invention, there is provided a solid-state imaging device that drives a solid-state imaging device by a driving pulse generated by a driving timing generation circuit and processes an imaging signal obtained by the solid-state imaging device by a signal processing circuit. A driving method of the device, wherein in a normal operation mode, the drive timing generation circuit and the signal processing circuit are operated based on a first reference clock; First
Operate based on the second reference clock set lower than the frequency of the reference clock, and make the charge accumulation time of the solid-state imaging device the same in both the normal operation mode and the standby operation mode. A drive pulse is generated by the drive timing generation circuit to suppress power consumption in the standby operation mode.

According to the above configuration, in the standby operation mode, the drive timing generation circuit and the signal processing circuit are operated based on the second reference clock set lower than the frequency of the first reference clock in the normal operation mode. In addition, power consumption in the standby operation mode can be suppressed. Further, the drive pulse generated so as to make the charge accumulation time of the solid-state imaging device in the both operation modes the same is driven so that the charge accumulation time in the both operation modes is the same. You.

According to a fourth aspect of the present invention, in the method of driving a solid-state imaging device according to the third aspect of the present invention, the first and second reference clocks are divided by dividing the original clock by a frequency dividing circuit. It is characterized by generating.

According to the above configuration, the first reference clock for the normal operation mode and the second reference clock for the standby operation mode are easily generated by dividing the frequency of the original clock.

According to a fifth aspect of the present invention, in the method for driving a solid-state imaging device according to the fourth aspect of the present invention,
The frequency of the reference clock is arbitrarily set by selecting the frequency division ratio of the frequency dividing circuit.

According to the above configuration, the power consumption in the standby operation mode is appropriately changed by appropriately selecting the frequency dividing ratio of the frequency dividing circuit. In that case, the lower the frequency division ratio, the lower the power consumption.

According to a sixth aspect of the present invention, in the driving method of the solid-state imaging device according to the fourth or fifth aspect, the charge storage period of the solid-state imaging device is represented by a horizontal scanning period. Is changed in accordance with the frequency division ratio of the first and second reference clocks to obtain the drive pulse that makes the charge accumulation time in the standby operation mode and that in the normal operation mode the same. I have.

According to the above configuration, the driving for driving the solid-state imaging device based on the frequency division ratio of the first and second reference clocks so that the charge accumulation time in the two operation modes is the same. Pulses are generated accurately and easily.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a block diagram of a camera system as a solid-state imaging device according to the present embodiment. This camera system includes an imaging lens 1, a CMOS
Image sensor unit 2, AGC (automatic gain control) circuit 3, A /
D converter 4, signal processing circuit 5, drive timing generation circuit 6
And an oscillation circuit 7.

An image of a subject is formed on the imaging surface of the CMOS image sensor unit 2 by the imaging lens 1, and an imaging signal obtained by the CMOS image sensor unit 2 is converted into an AGC circuit 3 and an A / D converter 4. Is supplied to a signal processing circuit 5 having a serial data generation unit (corresponding to the above-described control data generation unit) 13 and an output detection unit 14.

On the other hand, the drive timing generation circuit 6 includes a sensor drive pulse for driving the CMOS image sensor of the CMOS image sensor unit 2 and an AGC signal.
An AGC clamp pulse for the circuit 3 and control signals for the AGC circuit 3 and the A / D converter 4 are generated. Then, the sensor drive pulse is supplied to the CMOS image sensor unit 2, the AGC clamp pulse is supplied to the AGC circuit 3, and the control signal is supplied to the AGC circuit 3 and the A / D converter 4. Here, the drive timing generating circuit 6 includes a frequency dividing circuit 8, a horizontal counter 9, a vertical counter 10, a decoder 11, and a driving pulse shaping circuit 12.

The camera system having the above configuration operates as follows. That is, in the normal operation mode in which the CMOS image sensor unit 2 operates, the standby operation mode signal input to the signal processing circuit 5 is, for example, “0”.
Becomes Then, serial data for the normal operation mode (corresponding to the control data) including the frequency division ratio data, the shutter data, and the gain data is generated and output by the serial data generation unit 13. Then, the serial data is decoded by the decoder 11 and a frequency division ratio control signal for instructing “divide by 2” and a charge accumulation period
(A charge accumulation time of the CMOS image sensor represented by a horizontal scanning period H) is obtained, and the frequency division ratio control signal is output to the frequency dividing circuit 8, while the shutter signal is output from the sensor. Drive pulse shaping circuit 12
Is output to

The frequency dividing circuit 8 divides the frequency of the original clock generated by the oscillation circuit 7 by 2 based on the frequency dividing ratio control signal, and uses the signal processing circuit 5, the horizontal counter 9 and the decoder 11 as reference clocks. To supply. Then, the signal processing circuit 5 generates a horizontal reference pulse HD and a vertical reference pulse VD according to the reference clock, and
The data is sent to the horizontal counter 9 and the vertical counter 10.

The reference clock is counted by the horizontal counter 9 using the horizontal reference pulse HD as a trigger, and the count value is sent to the drive pulse shaping circuit 12. On the other hand, the vertical counter 10 counts the horizontal reference pulse HD from the horizontal counter 9 using the vertical reference pulse VD as a trigger, and sends the count value to the drive pulse shaping circuit 12. The horizontal counter 9 and the vertical counter 1 are driven by the drive pulse shaping circuit 12.
A sensor drive pulse and an AGC clamp pulse are generated based on the count value from 0 and the shutter signal from the decoder 11. Then, the sensor drive pulse is supplied to the CMOS image sensor unit 2, while the AGC clamp pulse is transmitted to the AGC circuit 3.

A control signal obtained as a result of decoding the serial data by the decoder 11 is an AGC signal.
The signal is output to the circuit 3 and the A / D converter 4. And A
A signal from the drive pulse shaping circuit 12 is output by the GC circuit 3.
Gain control is performed based on the GC clamp pulse and the control signal from the decoder 11. A / D converter 4
A / A based on a control signal from the decoder 11
D conversion is performed.

At this time, the intensity of the output signal from the A / D converter 4 (that is,
(Light quantity of the image) is detected, and a detection signal indicating the output intensity is output to the serial data generation unit 13. Then, the serial data generation unit 13 determines the necessity of changing the shutter speed based on the received detection signal. When the shutter data is changed, the shutter data (charge accumulation period of the CMOS image sensor) corresponding to the intensity (light amount) is obtained with reference to the table 15 and the serial data for the normal operation mode including the shutter data and the gain data is obtained. It is generated and output to the decoder 11. As a result, CMO
A sensor drive pulse or an AGC clamp pulse corresponding to a change in the amount of light is output to the S image sensor unit 2 and the AGC circuit 3.

Thus, in the normal operation mode, the CMOS image sensor unit 2, AGC circuit 3, A
The / D converter 4 and the signal processing circuit 5 operate based on a reference clock obtained by dividing the original clock generated by the oscillation circuit 7 into two by the frequency dividing circuit 8.

On the other hand, in the standby operation mode in which the CMOS image sensor unit 2 is not operated, the standby operation mode signal input to the signal processing circuit 5 is, for example, "1". Then, the serial data generation unit 1
3, serial data for the standby operation mode is generated and output. Then, the serial data is decoded by the decoder 11 and, for example, “divide by 8”
Is obtained and output to the frequency dividing circuit 8 and the sensor drive pulse shaping circuit 12.

The frequency dividing circuit 8 divides the frequency of the original clock from the oscillation circuit 7 by 8 based on the frequency dividing ratio control signal.
The reference clock is supplied to the signal processing circuit 5, the horizontal counter 9, and the decoder 11. Then, the signal processing circuit 5 generates a horizontal reference pulse HD and a vertical reference pulse VD according to the reference clock obtained by dividing the original clock by 8, and sends the generated signals to the horizontal counter 9 and the vertical counter 10. The horizontal counter 9, the vertical counter 10, and the drive pulse shaping circuit 12 generate a sensor drive pulse and supply it to the CMOS image sensor unit 2 in the same manner as in the normal operation mode.
A GC clamp pulse is generated and supplied to the AGC circuit 3.

A control signal corresponding to the reference clock obtained as a result of decoding the serial data by the decoder 11 is supplied to the AGC circuit 3 and the A / D converter 4.
Is output to Then, the gain control is performed by the AGC circuit 3 based on the AGC clamp pulse from the drive pulse shaping circuit 12 and the control signal from the decoder 11. The A / D converter 4 performs A / D conversion based on a control signal from the decoder 11.

Here, even in the standby operation mode, the intensity (light amount) obtained by the serial data generation unit 13 with reference to the table 15 based on the detection signal from the output detection unit 14 of the signal processing circuit 5 ), The serial data for the standby operation mode including the shutter data and the gain data according to (1) is generated and output to the decoder 11. Then, the CMOS image sensor unit 2 and A
A sensor drive pulse or an AGC clamp pulse corresponding to a change in light amount is output to the GC circuit 3. Thus, the shutter speed of the CMOS image sensor, that is, the charge storage time is optimally changed according to the light amount.

As described above, in the standby operation mode, the CMOS image sensor 2, AG
The C circuit 3, the A / D converter 4, and the signal processing circuit 5 operate based on a reference clock obtained by dividing the original clock generated by the oscillation circuit 7 into eight by the frequency dividing circuit 8. . Therefore, the entire camera system operates at a quarter of the frequency in the normal operation mode, and power consumption can be suppressed.

However, in this case, the charge storage time of the CMOS image sensor unit 2 is four times that in the normal operation mode. As a result, the level of the output signal from the CMOS image sensor unit 2 increases, and in some cases, the output signal is saturated. When switching to the normal operation mode in such a state, the screen is disturbed (for example, the screen becomes white). Therefore, it is necessary to make the charge storage time (shutter speed) of the CMOS image sensor the same as in the normal operation mode.

The above-described change of the shutter speed is performed as follows. That is, the serial data generation unit 13 of the signal processing circuit 5 sets the standby operation mode signal to “1”.
In this case, the shutter data immediately before the switching of the operation mode is converted into shutter data corresponding to the frequency division ratio (frequency division by 8) of the original clock with reference to the table 15. Then, serial data including the converted shutter data is generated. By doing so, even if the operation speed of the CMOS image sensor unit 2 becomes １ of the normal operation mode due to the operation mode switching, the CMO
The charge storage time of the S image sensor can be made equal to the charge storage time immediately before switching the operation mode.

Thereafter, the signal processing circuit 5 operates at one-fourth the speed in the normal operation mode to control the shutter speed, the gain and the white balance with respect to the change in the light amount. When the standby operation mode signal becomes “0” and the standby operation mode is released,
As described above, the serial data for the normal operation mode is output, and the dividing ratio by the dividing circuit 8 is returned to “divide by 2”. In that case, the serial data generation unit 13 converts the shutter data immediately before the operation mode switching into the shutter data corresponding to the frequency division by 2 with reference to the table 15. Then, serial data including the converted shutter data is generated. By doing so, the frequency division ratio becomes "2
The CMOS image sensor charge accumulation time before and after returning to "frequency division" can be made equal.

As described above, the signal processing circuit 5 operates even in the standby operation mode. When switching to the normal operation mode is instructed, the serial data generating unit 13 converts the shutter data so that the charge accumulation time becomes equal before and after the operation mode switching, and includes the changed shutter data. The serial data for the normal operation mode is generated. Therefore, when the standby operation mode is canceled, the exposure amount and the white balance of the video signal output from the signal processing circuit 5 are stable, and the output does not disturb.

FIG. 2 shows a case where the relationship between the charge accumulation period and the charge accumulation time in the standby operation mode and the normal operation mode in this embodiment is applied to the NTSC system.

In FIG. 2, for example, the optimum charge accumulation period according to the current light amount in the normal operation mode is 2
In the case of 40H (H: one horizontal scanning period), in the standby operation mode (divided by 8), by setting the charge accumulation period to 60H, the charge accumulation time is set to 1 which is the same as the optimal charge accumulation time in the normal operation mode. / 66 seconds. Therefore, in that case, when switching to the standby operation mode, the serial data generation unit 13 sets the shutter data in the normal operation mode to 240 H to store the shutter data in the charge accumulation period in the standby operation mode. Is converted to shutter data such that the shutter data is set to 60H, and serial data including the shutter data after the conversion is generated.

When the brightness of the subject changes in the standby operation mode and the charge accumulation period is changed from the set value 60H to, for example, 41H as described above, the normal operation mode (divided by 2) is set. When switching, the charge accumulation period in the standby operation mode is set to “41H”.
Is converted into shutter data that sets the charge accumulation period in the normal operation mode to "164H", and serial data including the converted shutter data is generated. By doing so, the charge storage time is set to 1 / the same as the charge storage time immediately before returning to the divide by 2.
It can be 96 seconds and does not cause image distortion.

That is, by storing the relationship shown in FIG. 2 in the table 15 of the signal processing circuit 5 in the present embodiment, the power consumption in the standby operation mode is suppressed and the standby operation mode is released. NTSC with no video signal disturbance and no time required for restart
In addition, the camera system of the above-described type can be realized.
When the MOS image sensor unit 2 is, for example, a low pixel type image sensor used for a CIF (Common Screen System) format, the reference clock may be the same as the original clock. In that case, if the original clock from the oscillation circuit 7 is frequency-divided by 8 in the frequency dividing circuit in the standby operation mode, the signal processing circuit 5 operates at 1/8 the speed. Therefore, since the charge storage time is eight times that in the normal operation mode, the shutter speed needs to be changed accordingly.

As described above, in the present embodiment,
A decoder 11 and a frequency divider 8 are provided in a drive timing generator 6 that generates a sensor drive pulse for driving the CMOS image sensor unit 2. Further, the signal processing circuit 5 that controls the drive timing generation circuit 6 includes a serial data generation unit 13 and an output detection unit 14.

Then, in the standby operation mode,
When the serial data generator 13 outputs the serial data for the standby operation mode, the decoder 11 decodes the serial data and divides a frequency division ratio control signal indicating, for example, “divide by 8”. Output to the circuit 8. The frequency dividing circuit 8 divides the frequency of the original clock from the oscillating circuit 7 by 8 and supplies it to the signal processing circuit 5 as a reference clock.

Therefore, thereafter, the CMOS image sensor unit 2, the AGC circuit 3, the A / D converter 4, and the signal processing circuit 5 operate in the normal operation mode based on the reference clock obtained by dividing the original clock by eight. It operates at a quarter of the frequency, so that power consumption can be reduced.

In this case, the serial data generator 13 converts the shutter data immediately before the operation mode switching into serial data including the shutter data obtained by converting the shutter data in accordance with the frequency division ratio (divided by 8) of the original clock. Generate. Therefore, the charge storage time immediately after the operation mode switching can be made equal to the charge storage time immediately before the switching. Thereafter, based on a detection signal from the output detection unit 14, serial data including shutter data corresponding to a change in intensity is generated to control the shutter speed and the gain corresponding to the light amount. In addition, the white balance is controlled.

When the standby operation mode is released, the serial data generator 13 converts the shutter data immediately before the frequency division ratio returns to “divide by 2” into the shutter data according to the frequency division by two. It generates serial data including it. In this way, the charge storage time in the normal mode is made equal to the charge storage time immediately before the division ratio returns to “divide by 2”.

Therefore, when the standby operation mode is released, the exposure amount and the white balance of the video signal output from the signal processing circuit 5 are stable, and the output does not disturb. As a result, no time is required for restarting when the standby operation mode is released.

Although the frequency dividing circuit 8 is provided in the drive timing generating circuit 6 in the above embodiment, the frequency dividing circuit may be formed in the oscillation circuit 7. Further, the frequency division ratio of the frequency dividing circuit 8 in the standby operation mode is not limited to the above-described frequency division, and may be appropriately changed as needed. At this time, a frequency division ratio designation signal can be input to the signal processing circuit 5 from the outside,
The serial data generation unit 13 may set the frequency division ratio data based on the input frequency division ratio designation signal, and generate serial data including the frequency division ratio data.

Further, in the above embodiment, the serial data for controlling the operation of the drive timing generation circuit 6 is supplied from the serial data generation unit 13 of the signal processing circuit 5. However, the present invention is not limited to this, and the operation of the drive timing generation circuit 6 may be controlled by a control microcomputer.

Further, in the above-described embodiment, a CMOS image sensor is used as the solid-state imaging device, but another device such as a CCD may be used. Also, the case where the present invention is applied to a camera system has been described as an example.
Etc. may be applied.

[0052]

As apparent from the above description, in the solid-state imaging device according to the first aspect of the present invention, in the standby operation mode, the frequency division is performed based on the control data for the standby operation mode generated by the control data generator. The circuit divides the original clock from the oscillation circuit to generate a reference clock having a lower frequency than the reference clock in the normal operation mode. Therefore, in the standby operation mode, a frequency lower than that in the normal operation mode is used. The drive timing generation circuit and the signal processing circuit can be driven by the reference clock. Therefore, power consumption in the standby operation mode can be suppressed.

At this time, the drive timing generation circuit generates a drive pulse based on the shutter data included in the control data so that the same charge accumulation time is obtained in the normal operation mode and in the standby operation mode. So
When the standby operation mode is released, the exposure amount and the white balance of the video signal output from the signal processing circuit are stable, and the video signal is not disturbed. Therefore, according to the present invention, no time is required for restarting when the standby operation mode is released.

Further, in the solid-state imaging device according to the second aspect of the present invention, since the frequency dividing circuit is built in the drive timing generating circuit, the number of components can be reduced as compared with the case where the frequency dividing circuit is provided alone. Thus, costs can be reduced.

According to a third aspect of the present invention, in the driving method of the solid-state imaging device according to the third aspect, in the standby operation mode, the second operation of the second reference clock having a lower frequency than the first reference clock for the normal operation mode is performed.
Since the drive timing generation circuit and the signal processing circuit are operated based on the reference clock, power consumption in the standby operation mode can be suppressed.

At this time, a drive pulse for driving the solid-state imaging device is generated by the drive timing generation circuit so that the electric charge accumulation time in the two operation modes is the same, so that the standby operation mode is released. In addition, the exposure amount and white balance of the video signal output from the signal processing circuit are stable, and the video signal is not disturbed. Therefore, according to the present invention, no time is required for restarting when the standby operation mode is released.

In the driving method for a solid-state imaging device according to a fourth aspect of the present invention, the first and second reference clocks are generated by dividing the original clock by a frequency dividing circuit. The first reference clock for the standby operation mode and the second reference clock for the standby operation mode can be easily generated.

In the driving method for a solid-state imaging device according to a fifth aspect of the present invention, the frequency of the second reference clock is arbitrarily set by selecting a frequency dividing ratio of the frequency dividing circuit. By appropriately selecting the frequency division ratio of the frequency division circuit, the power consumption in the standby operation mode can be appropriately changed according to the situation. Therefore, it can be applied to various television broadcasting systems.

According to a sixth aspect of the present invention, in the driving method of the solid-state imaging device, the driving pulse for driving the solid-state imaging device is set to the first and second driving modes so that the charge accumulation time in both operation modes is the same. Since the charge accumulation period of the solid-state imaging device is obtained by changing the division ratio of the second reference clock, the drive pulse can be generated accurately and easily.

[Brief description of the drawings]

FIG. 1 is a diagram of a camera system as a solid-state imaging device according to the present invention.

FIG. 2 is a diagram illustrating a relationship between a charge accumulation period and a charge accumulation time in a standby operation mode and a normal operation mode.

[Explanation of symbols]

1: imaging lens, 2: CMOS image sensor unit, 5
... Signal processing circuit, 6 ... Drive timing generation circuit, 7 ... Oscillation circuit, 8
... frequency divider, 11 ... decoder, 1
2 ... Drive pulse shaping circuit, 13 ... Serial data generator 14 ... Output detector, 15 ... Table.

Claims (6)

[Claims] 1. A solid-state imaging device that drives a solid-state imaging device by a driving pulse generated by a driving timing generation circuit and processes an imaging signal obtained by the solid-state imaging device by a signal processing circuit. A control data generating section for generating control data for the standby operation mode in the standby operation mode while generating control data for the operation mode, an oscillation circuit, and a control data for the normal operation mode in the normal operation mode. The original oscillation clock from the oscillation circuit is
While dividing by the dividing ratio, in the standby operation mode,
The original clock from the oscillation circuit is frequency-divided at a second frequency division ratio larger than the first frequency division ratio based on the control data for the standby operation mode, and a reference of the drive timing generation circuit and the signal processing circuit is obtained. A frequency dividing circuit for generating a clock, wherein the control data includes shutter data, and the shutter data has the same charge accumulation time of the solid-state imaging device in the normal operation mode and in the standby operation mode. Wherein the drive timing generation circuit generates a drive pulse based on the shutter data so that the same charge accumulation time is obtained in the normal operation mode and in the standby operation mode. Solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein said frequency dividing circuit is built in said drive timing generation circuit. 3. A method for driving a solid-state imaging device, wherein a solid-state imaging device is driven by a driving pulse generated by a driving timing generation circuit, and an image signal obtained by the solid-state imaging device is processed by a signal processing circuit. In the normal operation mode, the drive timing generation circuit and the signal processing circuit are operated based on the first reference clock. In the standby operation mode, the drive timing generation circuit and the signal processing circuit are operated at a frequency higher than the frequency of the first reference clock. The operation is performed based on a second reference clock set low, and the drive timing is set so that the charge accumulation time of the solid-state imaging device is the same in both the normal operation mode and the standby operation mode. Generated by the generator circuit to suppress power consumption in the standby operation mode. A method for driving a solid-state imaging device, comprising: 4. The solid-state imaging device according to claim 3, wherein the first and second reference clocks are generated by dividing an original clock by a frequency dividing circuit. How to drive the device. 5. The method for driving a solid-state imaging device according to claim 4, wherein the frequency of the second reference clock is arbitrarily set by selecting a frequency dividing ratio of the frequency dividing circuit. For driving a solid-state imaging device. 6. The driving method of a solid-state imaging device according to claim 4, wherein a charge accumulation period of the solid-state imaging device, which is represented by a horizontal scanning period, is defined by the first and second reference values. A method for driving a solid-state imaging device, characterized in that by changing the frequency in accordance with a frequency division ratio of a clock, the drive pulse that makes the charge accumulation time in the standby operation mode equal to that in the normal operation mode is obtained.