JP2000315947A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit with excellent responsiveness. SOLUTION: A 1st frequency divider 103 receives a reference frequency signal 102 frequency, divides the signal 102 and gives the result to a phase difference detector 113 and a phase comparator 114. A 2nd frequency divider 107 receives an output signal 106 of a voltage controlled oscillator 104 to divide it and the resulting signal is similarly given to a phase difference detector 113 and a phase comparator 114. The phase difference detector 113 discriminates a phase lead, a phase lag, and coincidence and gives the result to a 1st integration device 117, which outputs a voltage in response to the phase to a 2nd integration device 121. The 2nd integration device 121 integrates the received voltage in a form of correcting a comparison output 119 of the phase comparator 114 and gives a 2nd integration output to a voltage controlled oscillator 104. The PLL circuit whose frequency response is enhanced by the correction can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL circuit in which responsiveness is considered.

[0002]

2. Description of the Related Art FIG. 11 shows a configuration of a conventional PLL circuit. In this PLL circuit, a reference frequency signal 12 input to an input terminal 11 is input to a first frequency divider 13 to divide the frequency. The frequency-divided reference signal 14 is input to a phase comparator 17 together with a dependent frequency signal 16 as a frequency-divided output of a second frequency divider 15 so that the phases of these signals 14 and 16 are compared. I have. The comparison output 18 of the phase comparator 17 is input to an integrator 19, and its value is temporally integrated. An integrated output 21 of the integrator 19 is input to a voltage controlled oscillator (VCO) 22, and an output signal 23 having a frequency corresponding to a voltage value as the integrated output 21 is output. This output signal 23 is output from the output terminal 24 and fed back to the second frequency divider 15. As a result of this feedback control, the output signal 23 is output at a frequency that eliminates the phase difference between the signals 14 and 16 input to the phase comparator 17 with respect to the frequency of the reference signal 14 output from the first frequency divider 13. Will be output.

In the PLL circuit shown in FIG. 11, control is performed such that the phase difference between the two signals 14 and 16 disappears under a constant operating environment. However, when the operating temperature changes as an example of the operating environment, the frequency of the dependent frequency signal 16 changes even if the frequency of the reference frequency signal 12 is constant. As a result, a phase difference fluctuation occurs in the comparison output 18 of the phase comparator 17. Therefore, when the frequency is switched at high speed in synchronization with the reference frequency signal 12, the output signal 2
As a result of the fluctuation of the frequency in No. 3, a data error may occur when data is sampled in synchronization with the output signal. Some proposals have conventionally been made to solve such inconveniences.

FIG. 12 shows, as a first proposal, a PLL circuit which uniquely determines a pull-in operation at the time of loss of synchronization. In this figure, the same parts as those in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
This PLL disclosed in JP-A-7-162301 is disclosed.
In the circuit, the reference frequency signal 1 input to the input terminal 11
2 and the dependent frequency signal 1 output from the second frequency divider 15
6 is input to the output side of the phase comparator 17,
1 is arranged. In this PLL circuit, the phase comparator 1
The comparison output 18 output from 7 is input to the synchronization detector 31 and the active filter 33, and the output 34 is input to the voltage controlled oscillator (VCO) 22.

The active filter 33 includes an operational amplifier (not shown), a resistor, and a capacitor (not shown). By turning on and off a switch 35, the active filter 33 is realized by switching between a characteristic as a low-pass filter and a characteristic as an amplifier circuit. ing. The on / off control signal 36 output from the synchronization detector 31 selects a low-pass filter characteristic during synchronization, and selects an amplification circuit characteristic during non-synchronization.

In this PLL circuit, it is determined whether or not a synchronization state is established at the frequency as the comparison output 18 of the phase comparator 17, and when the out-of-synchronization occurs as in the case where the frequency of the output signal 23 fluctuates. The switch 35 is turned off by the on / off control signal 36, and the integration function of the active filter 33 is temporarily stopped. As a result, when the synchronization is lost, the operation always starts from the same condition and shifts to the pull-in operation, so that a reliable pull-in operation can be obtained.

FIG. 13 shows a main part of a PLL circuit provided with two systems of integration circuits as a second proposal.
13, the same parts as those in FIG. 11 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

This proposal (Japanese Patent Laid-Open No. 9-98028)
Now, the first and second phase comparison circuits 41 and 42 are
While being arranged in the L circuit, the reference frequency signal 12 and the dependent frequency signal 16 are input to the first phase comparison circuit 41,
Signal 44 obtained by inverting reference frequency signal 12 by inverting circuit 43
And the dependent frequency signal 16 are input to the second phase comparison circuit 42. Then, first or second integration circuits 45, 46 are arranged on the output side of the first and second phase comparison circuits 41, 42, and the first and second control voltages as integration results of the phase error signal are arranged. 47 and 48 are created. Then, these control voltages 47 and 48 are input to the phase difference / offset conversion circuit 49 to obtain an offset voltage 51, which is input together with the first control voltage 47 to the offset addition circuit 52 to output the offset addition control voltage 53. , The detectable input phase difference is increased. That is, in this proposal, phase synchronization is prevented from being lost even for a large input phase difference.

FIG. 14 shows, as a third proposal, a PLL circuit in which the phase locking performed when the phases of the inputs of the phase comparator coincide with each other is improved. In FIG. 14, the same portions as those in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

In the PLL circuit of this proposal (JP-A-1-231430), a logical gate circuit 61, an integrating circuit 62, and a Schmitt circuit 63 are provided on the output side of a phase comparator 60.
An N-stage counter 64 having at least a two-stage configuration or more is arranged in this order, and the output shaped by the Schmitt circuit 63 is used as the reset (R) input of the N-stage counter 64. Then, while the reference frequency signal 12 is used as an input to the counter frequency division input controller 66, the reference frequency signal 12 is output by the signal 67 output from the final stage of the N-stage counter 64.
Of the N-stage counter 64 is controlled.

That is, in this PLL circuit, when the phase of the reference frequency signal 12 and the phase of the dependent frequency signal 16 deviate from each other, two outputs 68 of the phase comparator 60,
As a result, the output of the logical gate circuit 61 becomes low level as a result of the outputs 69 corresponding to the phase differences of the inputs,
A reset signal 71 is supplied to the N-stage counter 64 to reset it. As a result, the N-stage counter 64 is unlocked, and the unlocked state is maintained as long as the phase of the reference frequency signal 12 and the dependent frequency signal 16 does not match.

Next, when the phases of the reference frequency signal 12 and the dependent frequency signal 16 match, the reset state is released, but the signal 67 output from the last stage of the N-stage counter 64 remains at the high level, and State is maintained,
This state continues until the reference frequency signal 12 is input to the N-stage counter 64 as a clock for N stages. Thereby, an erroneous lock state generated during the transient response of the PLL circuit can be avoided.

[0013]

As described above, various types of PLL circuits have been conventionally proposed in order to prevent inconvenience due to phase difference fluctuation on the dependent frequency side. However, the conventionally proposed first to third proposals have a problem that the phase difference is not quickly detected.

An object of the present invention is to provide a highly responsive PL.
An L circuit is provided.

[0015]

According to the first aspect of the present invention, (a) a first frequency dividing means for inputting a reference frequency;
(B) voltage-controlled transmitting means for outputting an output signal having a frequency corresponding to the input voltage; (c) second frequency-dividing means for dividing the output signal of the voltage-controlled transmitting means; Phase comparing means for receiving the output of the frequency dividing means and the output of the second frequency dividing means and comparing the phases; (e) the output of the first frequency dividing means and the output of the second frequency dividing means Phase difference discriminating means for discriminating the coincidence of the phases of both outputs upon input, and the advance or delay of the phase of the latter output with respect to the former output; Correction signal output means for outputting a correction signal of a level corresponding to the state of
(G) The PLL circuit is provided with integrating means for correcting and integrating the comparison result of the phase comparing means with the correction signal output from the correction signal output means and inputting the result to the voltage control transmitting means.

That is, according to the first aspect of the present invention, a configuration is provided in which a phase difference determining means and a correction signal output means are added to a normal PLL circuit. Here, the phase difference determining means inputs the reference frequency and a signal obtained by dividing the output signal output from the voltage control transmitting means, and determines whether the phase is coincident or the phase is advanced or delayed. Determine. The correction signal output means outputs a correction signal for performing a correction based on the determination result to the integration means so that the voltage control transmitter can respond quickly. As a result, a PLL circuit having good responsiveness to a change in frequency can be realized.

According to a second aspect of the present invention, in the PLL circuit according to the first aspect, the correction signal output means includes:
It is characterized in that a correction signal whose signal level changes stepwise in the order of progress is output.

That is, the invention according to claim 2 specifies that the correction signal output means outputs a correction signal whose signal level changes stepwise in the order of phase delay, coincidence, and advance. For example, if the signal level output with a phase delay is aV
In this case, if the values match, the voltage becomes 2 aV, and if the value advances, the voltage becomes 3 aV.

According to the third aspect of the present invention, there are provided (a) a first frequency dividing means for inputting a reference frequency, and (b) a voltage control transmitting means for outputting an output signal having a frequency corresponding to the input voltage.
(C) a second method for dividing the output signal of the voltage control transmitting means.
(D) phase comparing means for receiving the output of the first frequency dividing means and the output of the second frequency dividing means and comparing the phases, and (e) the frequency dividing means of the first frequency dividing means. Phase difference discriminating means for inputting the output and the output of the second frequency dividing means to determine the coincidence of the phases of the two outputs, and to determine either the advance or the delay of the phase of the latter output with respect to the former output; A correction signal output means for outputting a correction signal of a level corresponding to the state of the phase in accordance with the result of the determination by the phase difference determination means; (H) inputting the output of the first and second frequency dividers and the output signal of the voltage control transmitting means, and integrating them according to the phase difference. A pulse generating means for generating a pulse and inputting the pulse to a phase difference determining means; To be provided.

That is, the invention according to claim 3 has a configuration in which pulse generating means is further added to the PLL circuit according to claim 1. The pulse generating means inputs the outputs of the first and second frequency dividers and the output signal of the voltage control transmitting means in order to determine the phase difference and the advance or delay of the phase. Then, a pulse is generated for early matching in accordance with the state of the phase, and this pulse is input to the phase difference determining means.

According to a fourth aspect of the present invention, in the PLL circuit of the third aspect, the pulse generation means generates a pulse having a pulse width proportional to the magnitude of the phase difference.

In other words, according to the fourth aspect of the present invention, the output pulse width is changed to quickly correct the state without a phase difference.

According to a fifth aspect of the present invention, in the PLL circuit of the third aspect, the pulse generating means increases the number of pulses of a fixed width generated in proportion to the magnitude of the phase difference.

That is, according to the fifth aspect of the present invention, the number of pulses to be output is changed to quickly correct the state without a phase difference.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows a PLL circuit according to an embodiment of the present invention. The PLL circuit of the present embodiment is connected to an input terminal 101 and receives a reference frequency signal 102 from the first frequency divider 103 and a voltage controlled oscillator (VC
O) Output signal 1 output from 104 to output terminal 105
The second frequency divider 107 is provided with two frequency dividers for inputting 06. Each of these frequency dividers 103 and 107 outputs a frequency that matches at the least common multiple. A first frequency-divided output 111 output from the first frequency divider 103 and a second frequency-divided output 112 output from the second frequency divider 107 are provided by a phase difference detector 113 and a phase comparator 114.
Are input together. Phase difference detector 11
No. 3 outputs the result of the phase difference detection as a 2-bit value. Among them, the upper digit signal 115 and the lower digit signal 116 are input to the first integrator 117. First
The first integration output 118 output from the integrator 117 and the comparison output 119 from the phase comparator 114 are input to the second integrator 121. The second integration output 122 output from the second integrator 121 is input to the voltage controlled oscillator 104.

FIG. 2 shows a waveform change of each part in a state where the PLL circuit itself shown in FIG. 1 is synchronized (section A). FIG. 3A shows a first frequency-divided output 111 output from the first frequency divider 103.
FIG. 7B shows a second frequency-divided output 112 output from the second frequency divider 107. These frequency dividers 10
At 3 and 107, the first frequency-divided output 111 and the second frequency-divided output 1 are synchronized with the PLL circuit itself (section A).
12 is in phase synchronization. As described above, when the first and second frequency-divided outputs 111 and 112 match, the signal 115 (FIG. 2 (g)) of the upper digit of the phase difference detector 113 is high (H) level and low The digit signal 116 (FIG. 2)
(H)) is at the low (L) level.
In this state, when the input voltage of the voltage controlled oscillator 104 rises, the frequency of the output signal 106 rises, and conversely, when the input voltage of the voltage controlled oscillator 104 falls, the frequency of the output signal 106 falls. ing.

FIG. 3 specifically shows a circuit configuration of a phase difference detector that performs such a circuit operation. The phase difference detector 113 includes a first flip-flop circuit 131 having the first frequency-divided output 111 as a clock (CK) input.
It has. The second frequency-divided output 112 is inputted to a data input terminal (D) of the first flip-flop circuit 131. First flip-flop circuit 1
The output signal 132 output from the output terminal Q of the input terminal 31 is input to the level generation circuit 133. As a result, the first
Of the first frequency-divided output 111
Is more advanced than the second divided output 112,
A high-level signal is output as the output signal 132, which is input to the level generation circuit 133. Conversely, if the signal is delayed, a high-level signal is output as the output signal 132, and this is output to the level generation circuit 133. 133.

The first frequency-divided output 111 and the second frequency-divided output 112 are input to an exclusive-OR circuit 134 to perform an exclusive-OR operation, and an exclusive-OR signal 135 as a result is obtained. The count input signal of the counter 136 is provided.

The counter 136 is supplied with a clock signal 138 from a clock generation source (not shown), and receives the second frequency-divided output 112 as a reset signal. Here, the clock signal 138 is a signal whose cycle is sufficiently shorter than the second frequency-divided output 112. Therefore, the counter 13
Numeral 6 performs counting indicating the number of rising edges of the clock signal 138 when the exclusive OR signal 135 is at a high level. The count value signal 139 composed of a plurality of bits representing the count value output from the counter 136 is output from the level generation circuit 1.
33.

The level generating circuit 133 is enabled only when the second frequency-divided output 112 is at a high level. If the count value represented by the count value signal 139 is “0” in a section where the second frequency-divided output 112 is at a high level, it is determined that there is no phase difference.
As shown in the section A, a signal in which the upper digit signal 115 is at a high level and the lower digit signal 116 is at a low level is output. When the count value represented by the count signal 139 is other than “0”, the upper digit signal 115 and the lower digit signal 115 are output according to the signal level of the output signal 132 output from the output terminal Q of the first flip-flop circuit 131. The signal in the signal state indicating the phase advance or the signal in the signal state indicating the phase delay is output by the digit signal 116.

Returning to FIG. 2, the case where the phases are synchronized will be described. As shown in the section A, when the phases of the first frequency-divided output 111 (FIG. 7A) and the second frequency-divided output 112 (FIG. 6B) almost coincide with each other, The exclusive OR signal 135 becomes low level during the matching period, and the exclusive OR signal 135 (FIG. 7 (f)) becomes high level only in other small sections. If the phase shift is negligible and the period during which the exclusive OR signal 135 is at the high level is within one cycle of the clock signal 138, the counter 136 does not perform counting and the count value signal 139 becomes "0". ". As a result, the higher-order signal 115 is output from the level generator 133 at the high level and the lower-order signal 1 is output.
16 also outputs a high level signal. This means that there is no phase difference.

FIG. 4 shows a state in which the phase is advanced as section B. In this case, the first divided output 11
1 (FIG. 9A) and the second OR output 112 (FIG. 9B) by an amount corresponding to the phase shift of the exclusive OR signal 135.
The time of the high level shown in FIG. 9F becomes longer, and the count signal 139 output from the counter 136 becomes “1”.
It becomes a value larger than. The level generation circuit 133
The output signal 132 ((e) in FIG. 3) output from the flip-flop circuit 131 of FIG. 1 is at a high level due to the advance of the phase, and it is detected that the phase is advanced by a certain range or more by this signal level. Then, the level generation circuit 133 outputs a signal in which the upper-order signal 115 is at a high level and the lower-order signal 116 is at a low level. This means phase advance.

FIG. 5 shows a state in which the phase is delayed as section C. In this case, the first divided output 11
1 (FIG. 9A) and the second OR output 112 (FIG. 9B) by an amount corresponding to the phase shift of the exclusive OR signal 135.
The time of the high level in (f) of FIG. 4 is similarly increased, and the count signal 139 output from the counter 136 becomes a value larger than “1”. Level generation circuit 133
Indicates that the output signal 132 ((e) in the figure) output from the first flip-flop circuit 131 is at a low level due to the phase delay, and that the signal level delays the phase by a certain range or more. To detect. And
From the level generation circuit 133, a signal is output in which the upper-order signal 115 is at a low level and the lower-order signal 116 is also at a low level. This means a phase delay.

FIG. 6 shows a specific configuration of the first integrator. The first integrator 117 includes a first resistor 141 for inputting the upper-order signal 115 of the first phase difference detector 113, and a first resistor 141 having the other end of the first resistor 141 connected to an inverting input terminal. , The first capacitor 143 connected between the inverting input terminal and the output terminal of the first operational amplifier 142, and the lower-order signal 116 of the first phase difference detector 113 are input to one end. A second resistor 145; a first Zener diode 146 having the other end of the second resistor 145 connected to the cathode side and a grounded anode side; The third resistor 147 is connected to the other end and one end of the third resistor, and is connected to the non-inverting input terminal of the first operational amplifier 142 and the other end is grounded.
And the capacitor 148 of the first embodiment.

In such a first integrator 117, the first integrator 117
The voltage as the integrated output 118 of the operational amplifier 142 is represented by e₀
And the voltage of the signal 115 of the upper digit is e₁And Also,
Let the voltage of the lower-order signal 116 be e_TwoAnd Further, this embodiment
In the case of single power supply operation of + 5V, the high level means + 5V.
Taste, low level means 0V. Further
In this embodiment, the second and third resistors 145, 147 and
Voltage at connection point 149 of first zener diode 146
147 and the action of the first Zener diode 146
The voltage e_TwoIs high level (+ 5V)
2.5V and voltage e_TwoIs low level (0V)
Is set to 0V. Voltage e₀, Voltage e ₁And electricity
Pressure e_TwoThe following equation (1) is established between.

E ₀ ∝−∫ (e ₂ −e ₁ ) dt (1)

Therefore, the first integrator 1 shown in FIG.
17, the relationship between the voltage e ₀ , the voltage e _1, and the voltage e ₂ in each of the “no phase difference”, “phase advance”, and “phase lag” states shown in FIGS. 2, 4, and 5, respectively. The result is as shown in Table 1 below.

[0040]

[Table 1]

However, since the input to the second integrator 121 (see FIG. 1) located at the next stage in the voltage e ₀ as the integrated output 118 in Table 1, the relationship between the potentials is reversed. .

FIG. 7 specifically shows the configuration of the second integrator. The second integrator 121 outputs the first integrated output 1 output from the first integrator 117 shown in FIG.
A second operational amplifier 152 that connects the fourth resistor 151 and the inverting input terminal, and a connection between the inverting input terminal and the output terminal of the second operational amplifier 152. The fifth resistor 153, the comparison output 119 of the phase comparator 114 (see FIG. 1) at one end, a sixth resistor 155, and the other end of the sixth resistor 155 connected to the cathode side and the anode side. A second zener diode 156 having a grounded ground, and a second zener diode 15
6 has one end connected to the non-inverting input terminal of the second operational amplifier 153 and the other end connected to the third capacitor 157.
A seventh resistor 158 connected to one end of the operational amplifier 15
Low-pass filter 159 having one end connected to the output side of the second filter 159
It is composed of Here, the third capacitor 15
The other end of 7 is grounded. In addition, low-pass filter 1
The second integrated output 122 is output from the other end of the signal 59.

With the second integrator 121 having such a configuration,
The sixth resistor 155, the seventh resistor 158, and the second
The voltage at the connection point 161 of the_ThreeWhen
And a seventh resistor 158, a second operational amplifier 152 and
The voltage at the node 162 of the third capacitor 157 is set to e_FourWhen
I do. Voltage e_ThreeIs + when the comparison output 119 is + 5V.
2.5V, and 0V when the comparison output 119 is 0V
Becomes Therefore, the voltage e _FourAs the third condition
The primary filter of the sensor 157 and the seventh resistor 158.
The voltage e_ThreeIs obtained in accordance with the duty ratio.
Assuming that the first integration output 118 is constant, a low-pass
Of the second integrated output 122 output from the filter 159
The voltage is proportional to the duty of the comparison output 119.
Become.

When the first integrated output 118 fluctuates, the voltage of the first integrated output 118 is-
The voltage is added by the ratio of (the resistance value of the fifth resistor 153) / (the resistance value of the fourth resistor 151). Therefore, if the voltage as the first integrated output 118 increases, the voltage as the second integrated output 122 decreases, and conversely, the first integrated output 122 decreases.
If the voltage as the integral output 118 of the second output decreases, the voltage as the second integral output 122 will increase.

FIG. 8 specifically shows the structure of the phase comparator. The phase comparator 114 outputs the first divided output 1
A second flip-flop circuit 171 having a clock input of 11 and a third flip-flop circuit having a second frequency-divided output 112 as data and a clock signal 138 as a clock input.
Flip-flop circuit 172 and the second frequency-divided output 11
An inverter 173 that inverts the logic of 2 and a NAND circuit 177 that takes the NAND of the second divided output 174 inverted by the inverter 173 and the output 176 of the third flip-flop circuit 172 are provided. .
Reset signal 178 output from NAND circuit 177
(FIGS. 2, 4, and 5C) serve as a reset input of the second flip-flop circuit 171. The output terminal of the second flip-flop circuit 171 outputs a comparison output 119 (FIGS. 2, 4, and 5D).

Therefore, the comparison output 119 becomes high level at the rise of the first divided output 111 (FIGS. 2, 4 and 5A), and the second divided output 112 (FIGS. 2, 4 and 5). It goes low at the falling edge of FIG. 5 (b). As a result, the comparison output 119 becomes the first divided output 111
A signal having a pulse waveform that fluctuates in a range of duty “0” to duty “100” according to the phase difference between the second divided output 112 and the second divided output 112.

That is, in the section B shown in FIG.
The phase of the second frequency-divided output 112 output from the second frequency divider 107 is ahead of the phase of the frequency-divided output 111 of the second frequency-divided output 111. In such a state, as shown in FIG. 4 (g), the upper-order signal 115 of the first phase difference detector 113 is at a high level,
Also, the signal 116 ((h) in the figure) of the lower digit is in a low level state. At this time, the voltage as the second integration output 122 output from the second integrator 121 decreases. As a result, the frequency of the output signal 106 output from the voltage controlled oscillator 104 to which the signal is input decreases.
As a result, the phase as the second frequency-divided output 112 shown in FIG. And
When there is no phase difference, both the upper digit signal 115 and the lower digit signal 116 become high level (see FIG. 2).

On the contrary, in the section C shown in FIG. 5, the phase of the second divided output 112 outputted from the second divider 107 is delayed more than that of the first divided output 111. It is in a state where it is. In such a state, the first phase difference detector 11
Both the signal 115 and the signal 116 are at a low level. As a result, the voltage of the second integration output 122 output from the second integrator 121 increases. As a result, the frequency of the output signal 106 output from the voltage controlled oscillator 104 increases, and the phase of the second divided output 112 advances, and approaches the first divided output 111. When there is no phase difference, both the upper digit signal 115 and the lower digit signal 116 become high level (see FIG. 2).

In this embodiment, the first divided output 11
Although it has been described that there is no phase difference when the first and second frequency-divided outputs 112 have the same phase as shown in the section A of FIG. 2, the present invention is not limited to this. For example, a state where these phase differences are 90 degrees is set as a reference that there is no phase difference,
From this point, the advance or delay of the phase may be determined. In the embodiment, the output of the phase difference detector 113 is 3
Although represented by a value, it may be represented by a value greater than this.

Modification

FIG. 9 shows an outline of the configuration of a PLL circuit according to a modification of the present invention. In this modification, the same parts as those in FIG. 1 of the previous embodiment are denoted by the same reference numerals,
These descriptions will be omitted as appropriate. The PLL circuit of this modification has a configuration in which a pulse generator 201 is added to the circuit of the embodiment. Here, the pulse generator 201 receives the first divided output 111, the second divided output 112, and the output signal 106A, and supplies the correction pulse signal 202 to the phase difference detector 113. Has become.

FIG. 10 shows waveforms at various parts of the PLL circuit of this modification. Sections A, B, C in this figure
Are the sections A, B, and
Corresponds to C. In FIG. 10, the first divided output 1
11 (a), the second frequency-divided output 112 in FIG. 7 (b), the upper digit signal 115 in FIG. 9 (c), and the lower digit signal 116 in FIG. 9 (d). Is shown. As can be understood from these figures, in this modification, the pulse 115P or 11P
6P is generated. That is, when a large phase difference occurs, the pulse 115P or 116P is added in accordance with the large phase difference, so that the state can be promptly corrected to a state without the phase difference.

Therefore, in the sense that the output of the integrator is changed quickly, the correction pulse signal 202 output from the pulse generator 201 does not necessarily have to be a single pulse, but a pulse group consisting of a plurality of pulses. It may be. In short, by increasing the overall pulse width, it is possible to quickly correct the state without a phase difference.

[0054]

As described above, according to the first and second aspects of the present invention, the phase difference is determined by adding the phase difference discriminating means and the correction signal output means to the ordinary PLL circuit. It is possible to realize a PLL circuit having good responsiveness to a change in frequency by determining whether the case is ahead or behind, and generating a correction signal based on this.

According to the third and fifth aspects of the present invention, not only the same effects as those of the first and second aspects of the invention can be obtained, but also a pulse generating means is added and the phase difference is reduced. Since a pulse corresponding to the advance or delay of the phase is generated and input to the phase difference discriminating means, the state can be corrected more quickly to a state without a phase difference.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a PLL circuit according to one embodiment of the present invention.

FIG. 2 is various waveform diagrams showing waveform changes of respective parts in a state where the PLL circuit itself shown in FIG. 1 is synchronized (section A).

FIG. 3 is a block diagram specifically showing a circuit configuration of a phase difference detector in the present embodiment.

FIG. 4 is a waveform diagram showing a waveform change of each part in a state where a phase is advanced as a section B;

FIG. 5 is various waveform diagrams showing waveform changes of respective sections in a state where a phase is delayed as a section C;

FIG. 6 is a circuit diagram showing a specific configuration of a first integrator according to the embodiment of the present invention.

FIG. 7 is a circuit diagram specifically showing a configuration of a second integrator in the present embodiment.

FIG. 8 is a block diagram specifically illustrating a circuit configuration of a phase comparator in the present embodiment.

FIG. 9 is a block diagram illustrating an outline of a configuration of a PLL circuit according to a modification of the present invention.

FIG. 10 is various waveform diagrams showing waveforms of respective parts of a PLL circuit according to a modification.

FIG. 11 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 12 is a circuit diagram of a PLL circuit as a first proposal that uniquely determines a pull-in operation at the time of loss of synchronization.

FIG. 13 is a circuit diagram showing a main part of a PLL circuit having two systems of integration circuits as a second proposal.

FIG. 14 shows a third proposed PLL in which the phase lock performed when the phases of the inputs of the phase comparator match each other is improved.
FIG. 3 is a circuit diagram illustrating a circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 102 Reference frequency signal 103 First frequency divider 104 Voltage controlled oscillator (VCO) 106 Output signal 107 Second frequency divider 113 Phase difference detector (phase difference discriminating means) 114 Phase comparator 115 Upper digit signal 116 Lower Digit signal 117 First integrator (correction signal output means) 118 Integration output 119 Comparison output 121 Second integrator 122 Second integration output 201 Pulse generator

Continuation of the front page (72) Inventor Minoru Fukuda Miyagi Japan KK08

Claims (5)

[Claims] A first frequency dividing means for inputting a reference frequency; a voltage controlled transmitting means for outputting an output signal having a frequency corresponding to an input voltage; and a second frequency dividing means for dividing an output signal of the voltage controlled transmitting means. A frequency dividing means, a phase comparing means for receiving an output of the first frequency dividing means and an output of the second frequency dividing means and comparing phases, and an output of the first frequency dividing means and a second Phase difference discriminating means for inputting the output of the frequency dividing means and determining whether the phases of the two outputs coincide with each other and whether the phase of the output of the latter is advanced or delayed with respect to the output of the former. Correction signal output means for outputting a correction signal of a level corresponding to the state of the phase according to the result; and correcting and integrating the comparison result of the phase comparison means with the correction signal output from the correction signal output means, and integrating the value. And integrating means for inputting to the voltage control transmitting means. And a PLL circuit. 2. The method according to claim 1, wherein the correction signal output means includes:
2. The PLL circuit according to claim 1, wherein a correction signal whose signal level changes stepwise in the order of coincidence and advance is output. 3. A first frequency dividing means for inputting a reference frequency, a voltage controlled transmitting means for outputting an output signal having a frequency corresponding to an input voltage, and a second frequency dividing means for dividing the output signal of the voltage controlled transmitting means. A frequency dividing means, a phase comparing means for receiving an output of the first frequency dividing means and an output of the second frequency dividing means and comparing phases, and an output of the first frequency dividing means and a second Phase difference discriminating means for inputting the output of the frequency dividing means and determining whether the phases of the two outputs coincide with each other and whether the phase of the output of the latter is advanced or delayed with respect to the output of the former. Correction signal output means for outputting a correction signal of a level corresponding to the state of the phase according to the result; and correcting and integrating the comparison result of the phase comparison means with the correction signal output from the correction signal output means, and integrating the value. Integrating means for inputting to voltage control transmitting means; Pulse generating means for receiving the output of the second frequency divider and the output signal of the voltage control transmitting means, generating a pulse corresponding to the phase difference, and inputting the generated pulse to the phase difference determining means. Features PLL circuit. 4. The PLL circuit according to claim 3, wherein said pulse generation means generates a pulse having a pulse width proportional to the magnitude of the phase difference. 5. The PLL circuit according to claim 3, wherein said pulse generation means increases the number of pulses of a fixed width generated in proportion to the magnitude of the phase difference.