JP2000312207A - Communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an inexpensive communication system by realizing a configuration to connect a plurality of communication units corresponding to a reference model of a multi ATM so as to simplify the configuration. SOLUTION: A communication unit 1 is provided with a physical layer processing means 101 that processes a protocol on a physical layer, a plurality of host layer processing means 21, 22 that process a protocol on higher order layer than the physical layer, and an internal connection means 81 that interconnects the physical layer processing means 101 and a plurality of the host layer processing means 21, 22 that are mutually connected. Then the communciation system is provided with an external connection means 8 that interconnects at least one host layer processing section 22 of the communication unit 1 with an internal connection means 82 of other communication unit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a communication medium (physical layer processing means) for processing a protocol of a physical layer and a communication medium (higher layer processing means) for processing a protocol of a layer higher than the physical layer. The present invention relates to a communication system for externally connecting communication devices internally connected by a bus (internal connection means).

[0002]

[Prior art]

[0003] As a conventional communication apparatus of this type, for example, "The ATM ForumTechnical"
Committee UTOPIA Specifi
Cation Level 1, Version
2.01 af-phy-0017.000 Marc
h 21, 1994 "and" The ATM Fo "
rum Technical Committee U
TOPIA Level2, Version 1.0
af-phy-0039.000 June199
5 "is a communication device described in the specification.

[0004] FIG. 12 shows an "AT" described in the specification.
FIG. 3 is a diagram showing a reference model of a UTOPIA bus in the specification of “M Forum UTOPIA Level 1”.

FIGS. 13, 14 and 15 respectively show an "ATM Forum U" described in the specification.
UTOP in the specification of "TOPIA Level 2"
FIG. 3 is a diagram showing a reference model of an IA bus.

In FIGS. 12, 13, 14, and 15, 10, 11, 12,..., 1m (m is a natural number)
Each is a PHY layer processing unit that processes a physical layer protocol. The above-mentioned “PHY” is replaced with “Phys
ical ".

Also, 20, 21, 22,..., 2n (n
Is a natural number) is an ATM layer processing unit that processes an ATM layer and a protocol of a layer higher than the ATM layer.

[0008] Reference numeral 30 denotes a PHY layer processing unit 10,
, 1m (m is a natural number) and an ATM interface processing unit 20, 21, 22,..., 2n (n is a natural number) is a UTOPIA bus.

FIG. 12 is a diagram showing a reference model in a case where the ATM layer processing section and the PHY layer processing section have a one-to-one correspondence. Hereinafter, "1 ATM-1P
HY ”.

FIG. 13 is a diagram showing a reference model in a case where the ATM layer processing section and the PHY layer processing section have one-to-many correspondence. In the reference model shown in FIG. 13, since there are a plurality of PHY layer processing units, it is called “multi-PHY”. Hereinafter, "1 ATM-
MPHY ”.

FIG. 14 is a diagram showing a reference model in a case where the ATM layer processing section and the PHY layer processing section have many-to-one correspondence. In the reference model shown in FIG. 14, since there are a plurality of ATM layer processing units, it is called "multi-ATM". Hereinafter, "MATM-
1PHY ”.

FIG. 15 is a diagram showing a reference model in a case where the ATM layer processing section and the PHY layer processing section have many-to-many correspondence. In the reference model shown in FIG. 15, a plurality of ATM layer
Since there are a plurality of Y layer processing units, "Multi ATM
-Multi-PHY ". Hereinafter, "MA
TM-MPHY ".

"ATM For" described in the above specification
In the specifications of “um UTOPIA” (Levels 1 and 2), among the reference models shown in FIGS. 12 to 15, the reference model “1ATM-1PHY” shown in FIG. 12 and the “1ATM-MPHY” shown in FIG. The configuration (specification) of the interface on the transmission side and the reception side is disclosed only for the reference model. The outline is as follows.

FIG. 16 shows an example of the "AT" described in the specification.
It is a figure which shows the structure of the interface of the transmission side in the specification of "M Forum UTOPIA Level 1."

The configuration of the interface on the transmitting side shown in FIG. 16 is a configuration corresponding to the reference model of "1 ATM-1PHY" shown in FIG.

In FIG. 16, reference numeral 10 denotes a PHY layer processing unit, and reference numeral 20 denotes an ATM layer processing unit.

The reference numeral 31 indicates that the PHY layer processing unit 10
A “TxClav” signal 32 indicating that data can be received to the TM layer processing unit 20, and “TxEnb *” 32 indicating that data transferred from the ATM layer processing unit 20 to the PHY layer processing unit 10 is valid. Signal.

Reference numeral 33 denotes a "TxSOC" signal which is a pulse signal indicating the head of data to be transferred from the ATM layer processing unit 20 to the PHY layer processing unit 10, and 34 denotes a data bus for transmitting 8-bit or 16-bit data. Is a “TxDATA” signal.

3t is a “TxClav” signal 31
, A “TxEnb *” signal 32, a “TxSOC” signal 33, and a “TxDATA” signal 34.

Next, the operation in the configuration of the interface on the transmitting side shown in FIG. 16 will be described.

First, the PHY layer processing unit 10 executes the ATM
If the cell can be received, the “TxClav” signal 31 is asserted.

Next, the ATM layer processing section 20 executes "Tx
Clav "signal 31 is asserted,
If there is an ATM cell to be transferred, "TxEnb
* "Signal 32 and" TxSOC "signal 33 signal are asserted.

The "TxSOC" signal 33 has a width of one clock and is always asserted at the beginning of an ATM cell to be transferred. Then, the ATM cell is transferred by the “TxDATA” signal 34 in accordance with the “TxSOC” signal 33.

FIG. 17 is a diagram showing the "AT" described in the specification.
It is a figure which shows the structure of the interface of the receiving side in the specification of "M Forum UTOPIA Level 1".

The configuration of the interface on the receiving side shown in FIG. 17 is a configuration corresponding to the reference model of "1 ATM-1PHY" shown in FIG.

In FIG. 17, reference numeral 10 denotes a PHY layer processing unit, and reference numeral 20 denotes an ATM layer processing unit.

Reference numeral 36 denotes an “RxClav” signal indicating that data exists in the PHY layer processing unit 10;
Is an "RxEnb *" signal indicating that data can be received by the ATM layer processing unit 20, and 38 is an "RxSOC" signal which is a pulse signal indicating the head of data transferred from the PHY layer processing unit 10 to the ATM layer processing unit 20 , 39
Is an "RxDATA" signal which becomes a data bus for transmitting 8-bit or 16-bit data.

3r is an "RxClav" signal 36
, An “RxEnb *” signal 37, a “RxSOC” signal 38, and a signal line for passing an “RxDATA” signal 39.

Next, the operation of the configuration of the interface on the receiving side shown in FIG. 17 will be described.

First, if there is an ATM cell to be transferred, the PHY layer processing unit 10 outputs an “RxClav” signal 36.
Assert

Next, the ATM layer processing unit 20 executes “Rx
If the "Clav" signal 36 is being asserted and an ATM cell can be accepted, "RxEnb *"
Assert signal 37.

Next, the PHY layer processing section 10 executes “Rx
When the assertion of the “Enb *” signal 37 is detected, the “RxS
The "OC" signal 38 is asserted.

The "RxSOC" signal 38 has a width of one clock and is always asserted at the beginning of the ATM cell to be transferred. Then, the ATM cell is transferred by the “RxDATA” signal 39 in accordance with the “RxSOC” signal 38.

FIG. 18 is a diagram showing the "AT
It is a figure which shows the structure of the interface of the transmission side in the specification of "M Forum UTOPIA Level 2."

The configuration of the interface on the transmitting side shown in FIG. 18 is a configuration corresponding to the reference model of "1 ATM-MPHY" shown in FIG. FIG. 18 shows an example in which three PHY layer processing units (mediums) exist.

In FIG. 18, reference numerals 11, 12, and 13 denote PHY layer processing units, and reference numeral 20 denotes an ATM layer processing unit.

Also, 3t is “TxCla” in FIG.
v "signal 31, a" TxEnb * "signal 32, and a" Tx
This is a set of transmission-side UTOPIA buses that bundle signal lines that pass the “SOC” signal 33 and the “TxDATA” signal 34, respectively.

Further, 311, 312, and 313 are PHYs.
Each of the layer processing units 11, 12, and 13 is a “TxClav” signal indicating that data can be received by the ATM layer processing unit 20, and the PHY layer processing unit 1
1, 12, and 13 correspond one-to-one.

3b is a PHY layer processing unit 11,
5-bit width “TxAddr” indicating an address selected from addresses assigned to each of 12 and 13
Signal.

Reference numerals 11a, 12a, and 13a are addresses assigned to the PHY layer processing units 11, 12, and 13, respectively.

For example, in the configuration of the interface on the transmitting side shown in FIG. 18, two addresses 11a (# 0 and # 1) are assigned to the PHY layer processing unit 11. This indicates that the device or device to be processed in the PHY layer processing unit 11 has two ports.

Next, the operation in the configuration of the interface on the transmitting side shown in FIG. 18 will be described.

First, the ATM layer processing unit 20
One of the addresses respectively assigned to the layer processing units 11, 12, and 13 is selected using a method such as round robin or fixed priority, and a “TxAddr” signal 3
Output the address to b.

The PHY layer processing unit (for example, 11) selected by the “TxAddr” signal 3b among the PHY layer processing units 11, 12, and 13 asserts the “TxClav” signal (for example, 311).

If the value (address) of the "TxAddr" signal 3b is # 1, the PHY layer processing unit 11 has been selected. The selected PHY layer processing unit 11 asserts a “TxClav” signal 311 when the ATM cell can be received.

The subsequent cell transfer procedure is the same as the description of the operation in the configuration of the interface on the transmitting side shown in FIG.

FIG. 19 shows the "AT
It is a figure which shows the structure of the interface of the receiving side in the specification of "M Forum UTOPIA Level 2."

In FIG. 19, reference numerals 11, 12, and 13 denote PHY layer processing units, and reference numeral 20 denotes an ATM layer processing unit.

Further, 3r is the symbol “RxCl” in FIG.
av ”signal 36, an“ RxEnb * ”signal 37, and an“ R
This is a set of UTOPIA buses on the receiving side, which bundle signal lines for passing the “xSOC” signal 38 and the “RxDATA” signal 39, respectively.

361, 362 and 363 are PHYs.
An "RxClav" signal indicating that each of the layer processing units 11, 12, and 13 has data to be transferred to the ATM layer processing unit 20, and the PHY layer processing unit 1
1, 12, and 13 correspond one-to-one.

3c is a PHY layer processing unit 11,
5-bit width “RxAddr” indicating an address selected from addresses assigned to each of 12 and 13
Signal.

Reference numerals 11a, 12a, and 13a are addresses assigned to the PHY layer processing units 11, 12, and 13, respectively.

For example, in the example shown in FIG.
The HY layer processing unit 11 has two addresses 11a (# 0
And # 1) are assigned. This indicates that the device or device to be processed in the PHY layer processing unit 11 has two ports.

Next, the operation in the configuration example of the interface on the receiving side shown in FIG. 19 will be described.

First, the ATM layer processing unit 20 sends the PHY
One of the addresses assigned to the layer processing units 11, 12, and 13 is selected using a method such as round robin or fixed priority, and the address is output to the “RxAddr” signal 3c.

In the PHY layer processing units 11, 12, and 13, the PH selected by the “RxAddr” signal 3c
The Y layer processing unit (for example, 11) asserts an “RxClav” signal (for example, 361).

Here, if the value (address) of the "RxAddr" signal 3c is # 1, the PHY layer processing unit 11 has been selected. The selected PHY layer processing unit 11 transfers A to the ATM layer processing unit 20.
If the cell has a TM cell, the “RxClav” signal 3
Assert 61.

The subsequent cell transfer procedure is the same as the description of the operation of the configuration of the interface on the receiving side shown in FIG.

Note that the "ATM
Among the clock signals and control signals included in the specifications of "Forum UTOPIA" (Levels 1 and 2), those not directly related to the present invention are not shown in the drawings, and the descriptions in the specification text are omitted. ing.

[0060]

In a conventional communication apparatus of this kind, the "MATM-1PHY" shown in FIG.
Reference model and "MATM-MPHY" shown in FIG.
With regard to the reference model, the specification in the standard (the configuration of the interface on the transmission side and the reception side) has not been determined.

Particularly, when a communication device corresponding to the reference model of "MATM-MPHY" is realized, the ATM
A complicated configuration such as a switch is required. On the other hand, the "M
When realizing a communication device corresponding to the reference model of "ATM-1PHY", it can be realized without using a complicated configuration such as an ATM switch, so that an inexpensive communication device with a simplified configuration is realized. Can be.

When a communication device corresponding to the reference model of “MATM-1PHY” is realized, A
It is also possible to use a configuration such as a TM switch,
For example, in an ATM switch, a mechanism for viewing destination information such as an ATM cell header and a routing header is indispensable, and a circuit therefor is required, and the configuration is redundant.

When an external device such as an ATM switch is connected to a PHY layer processing unit and used,
In a configuration using a switch, the multiplicity of the external interface of the communication device with the ATM exchange does not increase, and the transmission line bandwidth of the external interface cannot be used effectively.

The present invention has been made in order to solve the above-mentioned problems, and is roughly described as "MATM-1PH".
It is an object of the present invention to realize a configuration of a communication system in which a plurality of communication devices corresponding to the reference model “Y” are connected.

A first object of the present invention is to enable a plurality of communication devices to be externally connected by using a stack cable or the like, so that a transmission line band of an external interface can be effectively used by a plurality of communication devices. An object of the present invention is to provide a communication system capable of easily setting a bypass route when a communication device or an internal module of the communication device fails.

A second object of the present invention is to enable a plurality of communication devices to be externally connected in a rosary using a stack cable or the like, and to effectively use the transmission line band of the external interface by the plurality of communication devices. An object of the present invention is to provide a communication system capable of easily setting a bypass route when the communication device or an internal module of the communication device fails.

A third object of the present invention is to enable a plurality of communication devices to be externally connected in a star shape by using a stack cable or the like, and to effectively utilize a transmission path band of an external interface by a plurality of communication devices. It is possible to obtain a communication system that can facilitate setting of a detour path in the event of a failure of the communication device or an internal module of the communication device, and that can further increase the flexibility of connection between communication devices. is there.

A fourth object according to the present invention is to provide a communication apparatus which is capable of preventing data loss even when there is a difference between clock signals to be referred to between extended UTOPIA buses or when a delay is a problem in a stack cable. There is no communication system that can communicate correctly.

A fifth object of the present invention is to provide a communication system in which, for example, when an ATM switch is connected to a PHY layer processing unit and used as an external device, the multiplicity of an external interface of the communication device with the ATM switch is improved. Is to obtain a communication system capable of effectively using the transmission path bandwidth of the communication system.

[0070]

A first communication system according to the present invention is interconnected with one physical layer processing means for processing a protocol of a physical layer and a physical layer processing means for processing a protocol of a layer higher than the physical layer. A plurality of upper layer processing means, and a plurality of communication devices each comprising: one physical layer processing means; and internal connection means for connecting the interconnected plurality of upper layer processing means. External connection means for connecting the upper layer processing means to the internal connection means of another communication device.

In a second communication system according to the present invention, the external connection means connects one of the upper layer processing means in the communication device to the internal connection means of another communication device, and It is characterized in that the devices are connected in a rosary.

In a third communication system according to the present invention, the external connection means connects the plurality of upper layer processing means in the communication device to the internal connection means of another communication device, respectively. Are connected in a star shape.

A fourth communication system according to the present invention is characterized in that, in said communication device, said upper layer processing means or said internal connection means connected to said external connection means includes a first-in first-out memory. And

A fifth communication system according to the present invention is characterized in that, in said communication device, said physical layer processing means includes second external connection means for connecting to an external device.

[0075]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a communication system according to the present invention will be described with reference to the drawings.

The communication device according to the present invention is a communication device corresponding to the reference model “MATM-1PHY” shown in FIG. The UTOPIA bus 30 shown in FIG. 14 is an extended UTOP
It becomes IA bus. The extended UTOPIA bus is
One of the "internal connection means" described in the claims
It is an embodiment.

First, an example of the configuration of the interface on the transmitting side and the receiving side in the communication apparatus according to the first embodiment of the present invention will be described.

FIG. 1 is a diagram showing the configuration of the interface on the transmitting side in the communication device according to the first embodiment of the present invention.

In FIG. 1, reference numeral 10 denotes a PHY layer processing unit, and 21, 22, and 23 denote ATM layer processing units. The PHY layer processing unit 10 is an embodiment of the “physical layer processing unit” described in the claims. ATM layer processing units 21, 22,
23 is an embodiment of the "upper layer processing means" described in the claims.

Reference numeral 42 denotes the ATM layer processing units 21 and 2
"T" indicating that the data of Nos. 2 and 23 are respectively valid
xEnb * "signal, 43 is an ATM layer processing unit 21, 2
A “TxSOC” signal, which is a pulse signal indicating the beginning of data to be transferred from 2, 23 to the PHY layer processing unit 10,
Reference numeral 4 denotes a “TxDATA” signal that serves as a data bus for transmitting 8-bit or 16-bit data.

4t is a “TxEnb *” signal 42
And a transmission-side extended UT that bundles signal lines for passing a “TxSOC” signal 43 and a “TxDATA” signal 44, respectively.
A collection of OPIA buses. These signal lines are shown in FIG.
Corresponds to the UTOPIA bus 3t shown in FIG.

Reference numerals 401, 402 and 403 denote ATM.
This is a “TxReq” signal that is asserted as a transmission request when data to be transferred to the PHY layer processing unit 10 by each of the layer processing units 21, 22, and 23 exists.

Further, 411, 412 and 413 are ATM
This is a “TxClav” signal indicating that the PHY layer processing unit 10 can receive data transmitted from the layer processing units 21, 22, and 23, respectively.

Next, the operation of the configuration of the interface on the transmitting side shown in FIG. 1 will be described.

First, the PHY layer processing unit 10 executes the ATM
From the “TxReq” signals 401, 402, 403 requested to be transmitted from the layer processing units 21, 22, 23 to the PHY layer processing unit 10, one of the ATMs is determined by a method such as round robin or fixed priority.
Select a processing unit and assert the corresponding "TxClav" signal.

For example, when the PHY layer processing section selects the ATM layer processing section 21, the PHY processing section 10 asserts the "TxClav" signal 411. The ATM layer processing unit 21 can transfer data to the PHY layer processing unit 10 while the “TxClav” signal 411 is asserted.

The procedure after data transfer is the same as that described for the interface on the transmitting side shown in FIG. That is, the “TxEnb *” signal 41 is asserted, and the ATM cell is transferred to the PHY layer processing unit 10 by the “TxDATA” signal 44. In this case, ATM
At the beginning of the cell, the "TxSOC" signal 43 is asserted.

Here, when there are a plurality of ATM cells in the ATM layer processing section 21, every time one cell is transferred, "Tx
The “Clav” signal 411 may be negated or transferred continuously.

The set 4t of the extended UTOPIA bus on the transmitting side shown in FIG. 1 is a bundle of the “TxEnb *” signal 42, the “TxSOC” signal 43, and the “TxDATA” signal 44, as described above. How to bundle them (multiplexing method)
There are three types of methods: a method of multiplexing all of the signals, a method of multiplexing some of the signals, and a method of not multiplexing all of the signals.

FIG. 2 is a diagram showing a multiplexed configuration (two examples) of the extended UTOPIA bus in the communication device according to the first embodiment of the present invention, and shows the extended U on the transmitting side shown in FIG.
FIG. 11 is a diagram showing a configuration in a case where a set 4t of TOPIA buses is actually realized.

In FIG. 2, reference numeral 10 denotes a PHY layer processing unit, and 21, 22, and 23 denote ATM layer processing units.

4t is the extended UTOPIA on the transmitting side.
Among the bus signal lines, a transmission enable signal (“TxEnb
* ”Signal 42), transmission head pulse signal (“ TxSOC ”
Signal 43), transmission data signal (“TxDATA” signal 4
4) shows a signal line of a signal multiplexed with (4).

The content of each of these signals has already been described in the description of the configuration of the communication device shown in FIG.

Further, 4a, 4b, and 4c are AT
4a shows signal lines of signals transmitted from the M layer processing units 21, 22, and 23. Reference numeral 4a denotes a transmission enable signal (“TxEnb *” signal 42a), a transmission head pulse signal (“TxSOC” signal 43a), and , And a transmission data signal (TxDATA 44a).

4b is a transmission enable signal (“T
xEnb * ”signal 42b), a transmission head pulse signal (“ TxSOC ”signal 43b), and a transmission data signal (T
xDATA 44b).

4c is a transmission enable signal (“T
It is a signal line for passing the “xEnb *” signal 42c), the transmission head pulse signal (“TxSOC” signal 43c), and the transmission data signal (“TxDATA” signal 44c).

Reference numeral 15 denotes a multiplexing unit that multiplexes signals passing through each of the signal lines 4a, 4b, and 4c. The multiplexing unit 15 multiplexes signals by, for example, a multiplexing method using a selector or a bus drive selecting method using a buffer IC.

[0098] In FIG.
The configuration example 2 is a configuration without the multiplexing unit 15. In the case of “Configuration Example 2”, for example, when the PHY layer processing unit 10 is an LSI, it is assumed that the PHY layer processing unit 10 is connected in parallel to each of the ATM layer processing units 21, 22, and 23. Can be.

The transmission data signal (“TxDATA”
The signals 44a, 44b, and 44c) may be multiplexed as shown in "Configuration Example 1", and the other signals (control signals) may be configured as shown in "Configuration Example 2".

FIG. 3 is a sequence diagram showing a data transfer procedure in the interface on the transmitting side of the communication device according to the first embodiment of the present invention.

In FIG. 3, reference numeral 10 denotes a PHY layer processing unit, and reference numeral 20 denotes an ATM layer processing unit. Next, the operation will be described with reference to FIG. 1 using the sequence diagram shown in FIG.

First, the ATM layer processing unit 20 sends the PHY
The transfer request signal to the port 2 (“TxReq” signal 402) is asserted to the layer processing unit 10 (step S1).

Next, the PHY layer processing unit 10 sends the ATM
The port 2 available signal (“T
xClav ”signal 412) (step S
2).

Next, the ATM layer processing unit 20 sends the PHY
The “TxSOC” signal 42b and the “T
The “xEnb *” signal 43b and the “TxData” signal 44
b is transferred (step S3).

Next, the ATM layer processing unit 20 sends the PHY
At the same time when the transfer request signal to the ATM port 1 (“TxReq” signal 401) is asserted to the layer processing unit 10, the transfer request signal to the port 3 (“TxReq”) is asserted.
q "signal 403).

When the PHY layer processing unit 10 detects the assertion of a plurality of transfer request signals in an overlapping manner,
The HY layer processing unit 10 determines the order of the ATM cell transfer ports by a method such as fixed priority or round robin (step S4). In the example shown in FIG. 3, port 1 is selected first.

Next, the PHY layer processing section 10 sends the ATM
An available signal of port 1 (“T
xClav ”signal 411) (step S
5).

Next, the ATM layer processing unit 20 sends the PHY
The “TxSOC” signal 42a and “T
An “xEnb *” signal 43a and a “TxData” signal 44
The ATM cell consisting of a is transferred (step S6).

Next, the PHY layer processing unit 10 sends the ATM
An available signal of port 3 (“T
xClav ”signal 413) (step S
7).

Next, the ATM layer processing unit 20 sends the PHY
The “TxSOC” signal 42c and the “T
The “xEnb *” signal 43c and the “TxData” signal 44
Then, the ATM cell composed of c and c is transferred (step S8).

The positions of ports 1, 2, and 3 correspond to the ATM layer processing units 21, 22, and 23 shown in FIG.
It corresponds to.

FIG. 4 is a diagram showing the configuration of the interface on the receiving side in the communication apparatus according to the first embodiment of the present invention.

In FIG. 4, reference numeral 10 denotes a PHY layer processing unit, and 21, 22, and 23 denote ATM layer processing units.

Numeral 48 denotes a pulse signal "RxSOC" indicating the head of data to be transferred from the PHY layer processing unit 10 to the ATM layer processing units 21, 22, and 23, respectively.
The signal 49 is an "RxDATA" signal which serves as a data bus for transmitting 8-bit or 16-bit data.

A signal line passing the “RxSOC” signal 48 and a signal line passing the “RxDATA” signal 49 are respectively “RxSOC” in the conventional communication device shown in FIG.
This corresponds to a signal line for passing the signal 38 and a signal line for passing the “RxDATA” signal 39.

4r is an “RxSOC” signal 48
, And a set of reception-side extended UTOPIA buses in which signal lines for passing the “RxDATA” signal 49 are bundled.

Reference numerals 461, 462, and 463 denote signal lines for passing an “RxClav” signal asserted when the PHY layer processing unit 10 is capable of receiving data, respectively, and are connected to the respective ATM layer processing units 21, 22, and 23. One-to-one correspondence.

Further, 471, 472, 473 are ATM
This is an “RxEnb *” signal indicating that each of the layer processing units 21, 22, and 23 can receive data.

The operation of the configuration of the interface on the receiving side of the communication apparatus according to the first embodiment of the present invention shown in FIG. 4 differs from the operation of the configuration of the interface on the receiving side of the conventional communication apparatus shown in FIG. The description is omitted because it is basically the same except for the following one point.

That is, the difference from the conventional communication device is that PH
Which of the ATM layer processing units 21, 22, the Y layer processing unit
23 is selected and whether the corresponding "RxClav" signals 461, 462, 463 are asserted depends on the destination of the received ATM cell.

For example, when the ATM layer processing unit 21 is selected, the unselected ATM layer processing unit 22,
23 are “RxEnb *” signals 472 and 47, respectively.
Do not assert 3. Also, the extended UTOPIA on the receiving side
Data transferred by broadcasting via the bus 4r is discarded.

FIG. 5 is a diagram showing another configuration of the interface on the receiving side in the communication apparatus according to the first embodiment of the present invention.

In FIG. 5, reference numeral 20 denotes the whole of the ATM layer processing units 21, 22, and 23. Also, 4r
4 is a set of extended UTOPIA buses on the receiving side.
Are the same as those described above.

[0124] In addition, reference numeral 46 denotes "RxCl" asserted when the PHY layer processing unit 10 can receive data.
av ”signal.

47 is an ATM layer processing unit 21;
Reference numerals 22 and 23 denote “RxEnb *” signals indicating that data can be received.

The conditions that enable the configuration as shown in FIG. 5 are such that the ATM layer processing units 21, 22, and 23 each have means for identifying the header of the ATM cell, and the processing speed Is not a bottleneck for the extended UTOPIA bus 4r on the receiving side.

Each of the ATM layer processing units 21, 22, 2
3 respectively, the ATM cell addressed to itself is ATM
Handles cell disassembly processing and protocols higher than ATM,
ATM cells not addressed to itself are discarded.

In a conventional communication device corresponding to the reference model of “1 ATM-MPHY”, a plurality of PHY layer processing units 11, 1
2, ..., 1m corresponded.

[0129] Therefore, the "ATM
In the specification of “Forum UTOPIA Level 2”, the “TxAddr” signal shown in FIG.
Like the “RxAddr” signal 3c shown in FIG. 9, a 5-bit width address signal indicating an address selected from the addresses assigned to the PHY layer processing units 11, 12,..., 1m is used.

However, in the communication apparatus according to the present invention corresponding to the “MATM-1PHY” reference model, one PHY layer processing unit corresponds to one ATM layer processing unit. Therefore, since it is not necessary to identify the address (port) of the PHY layer processing unit, an address signal having a 5-bit width indicating the above address is deleted.

As the corresponding signals, the above-mentioned "TxReq" signals 401, 402 and 403 are added. This is because a plurality of A
The PHY layer 10 is provided to select one from the plurality of ATM layer processing units 21, 22, and 23 when a request is made from the TM layer processing units 21, 22, and 23.

The above two points correspond to the “UTOPIA bus” 3
r and 3t are “extended” to “extended UTOPIA buses” 4r and 4t.

As described above, with the interface configuration shown in FIGS. 1 to 5, in the communication apparatus according to the first embodiment of the present invention, a plurality of ATM layer processing units and one P
"MATM-1PH" composed of a HY layer processing unit
The configuration of the interface corresponding to the reference model “Y” can be realized.

Embodiment 2 Next, by applying the configuration of the interface of the communication device according to the first embodiment of the present invention described above, a communication system in which a plurality of the communication devices are connected by a stack cable can be configured.

[0135] The configuration and operation of the communication system according to the second embodiment of the present invention will be described below.

FIG. 6 is a diagram showing a reference model on the transmitting side in the communication system according to the second embodiment of the present invention.

In FIG. 6, reference numerals 1 and 2 denote communication devices, respectively. Also, 101 and 102 are communication devices 1 and
2 is a PHY layer processing unit that processes the protocol of the physical layer. Note that the PHY layer processing unit 101,
Reference numeral 102 denotes an embodiment of the "physical layer processing means" described in the claims.

Reference numerals 21 and 22 denote A which processes a protocol higher than the physical layer in the communication device 1.
It is a TM layer processing unit. Reference numerals 23 and 24 denote ATM layer processing units for processing protocols higher than the physical layer in the communication device 2, respectively. Each of the ATM layer processing units 21, 22, 23, and 24 is an embodiment of the "upper layer processing means" described in the claims.

Reference numerals 81 and 82 denote communication devices 1 and 82, respectively.
2 is an extended UTOPIA bus that interfaces the transmitting side between the physical layer and a layer higher than the physical layer. The extended UTOPIA bus is one embodiment of the "internal connection means" described in the claims.

Reference numeral 85 denotes a stack cable provided for connecting the communication device 1 and the communication device 2, and reference numeral 60 denotes a first-in first-out (FIFO) system provided in the ATM layer processing unit 22 of the communication device 1. Memory.

Reference numeral 5 denotes an ATM switch as an embodiment for an external device of the communication device 1, and 8 denotes an ATM switch.
This is a connection interface that is an interface on the transmission side provided for connecting an external device such as the exchange 5 and the PHY layer processing unit 101 in the communication device 1. The connection interface 8 is an embodiment of the "second external connection means" described in the claims.

[0142] In Fig. 6, a circle indicates that the connection is open (no connection). With such a configuration, the communication device 1 and the communication device 2 can be realized by the same module.

The external interface 8 is, for example, an optical fiber cable (155.52 Mbp) as a transmission medium.
s), coaxial cable (44.736 Mbps), twisted pair cable, and the like.

Further, as the transmission protocol, for example,
SDH (SONET), DS3, ISDN UNI, and the like.

These transmission media and transmission protocols are ITU-T, TTC, ANSI, ATM-Foru.
It is a general one defined by a standardization organization such as m.

For the stack cable 85, for example, a ribbon cable, a twisted pair cable, or the like is used as a transmission medium.

The transmission signal is TTL, ECL, PE
A general digital signal line level such as CL and LVDS (IEEE 1596.3) is used on the substrate.

When the signal ground level differs between the communication device 1 and the communication device 2, the connection cannot be simply made by TTL or the like, so an adjusting circuit is required.

The signal line in the stack cable 85 is the extended UTOPIA bus 82, and the transmission request “TxR
eq "signal, transmission available" TxClav "signal,
It consists of a transmission enable “TxEnb *” signal, a transmission head pulse “TxSOC” signal, and transmission data “TxDATA” signal (not shown).

Note that the communication device 1 and the communication device 2
If the TOPIA bus reference clock is asynchronous, an additional clock "TxCLK" signal (not shown) is required.

With the above configuration, the ATM cell transferred on the extended UTOPIA bus 82 is logically a PHY.
It is broadcast to the layer processing unit 102 and the ATM layer processing unit 22. Further, the PHY layer processing unit 102 conceptually exists, and the function of the PHY layer processing unit 102 is stopped.

The first-in first-out (FIFO) memory 60 temporarily stores the ATM cells transferred from the communication device 2 via the stack cable 85. When viewed from the communication device 2, the ATM layer processing unit 22 of the communication device 1
It is regarded as the Y layer processing unit 102.

If there is no difference between the clock signals referred to by the extended UTOPIA bus 81 of the communication device 1 and the extended UTOPIA bus 82 of the communication device 2 and the delay in the stack cable 85 does not matter, Out (F
The memory 60 of the (IFO) system is unnecessary.

Referring to FIG. 6, first-in first-out (FI
When the FO) type memory 60 is not inserted, logically, the extended UTOPIA bus 81 and the extended UTOPIA bus 82
And become one.

Also, conceptually, an integrated extended UTO
For the PIA buses 81 and 82, one PHY layer processing unit 101 and three ATM layer processing units 21, 23, 2
4 is a reference model of "MATM-1PHY" connected thereto.

FIG. 7 is a diagram showing a circuit configuration on the transmitting side of communication apparatus 1 shown in FIG. 6 in the communication system according to the second embodiment of the present invention.

In FIG. 7, 1 is a communication device, 10 is a PHY layer processing unit in the communication device 1, and 21 is a communication device 1
Is an ATM layer processing unit, and 22 is an ATM serving as an interface of a stack cable connection in the communication device 1.
It is a layer processing unit.

An external interface 8 is an interface for connecting the PHY layer processing unit 10 in the communication device 1 to an external device (not shown) such as an ATM switch.

A stack cable interface 6r, 6t is an interface for connecting the communication device 1 and a communication device (not shown) different from the communication device 1 using a stack cable (not shown). It is.

Reference numeral 63a denotes an SAR layer processing unit for assembling an ATM cell to be transmitted, 63b and 63t denote ECLs,
A driver IC using PECL, LVDS, etc., 44a is a transmission data "TxDATA" signal composed of ATM cells assembled by the SAR layer processing section 63a, and 44b is a transmission data "TxDATA" signal received from the stack cable interface 6r via the driver 63b. is there.

The transmission data "TxDAT" is provided in the ATM layers 21 and 22 respectively.
A "on a first-in first-out basis (FIF
O) type memory.

Further, wa is the transmission data “TxDATA”.
First-in-first-out (FIFO) memory 60a for signal 44a
SAR layer processing unit 63a for controlling writing to the
Is a memory write control signal output from the CPU.

Wb is the transmission data "TxDATA"
First-in-first-out (FIFO) memory 60b for signal 44b
This is a memory write control signal output from the driver 63b in order to control writing to the memory.

Reference numerals 62a and 62b denote control units for controlling the reading of the transmission data "TxDATA" signals 44a and 44b stored in the first-in first-out (FIFO) memories 60a and 60b, respectively.

Reference numerals 65a and 65b denote driver ICs for controlling the reading of transmission data "TxDATA" signals 44a and 44b stored in first-in first-out (FIFO) memories 60a and 60b, respectively.

Also, ca and cb are first-in first-out (F
AT stored in the memories 60a and 60b of the
This is a cell counter for counting the number of M cells.

Further, ra and rb are first-in first-out (F
This is a memory read control signal output from the control units 62a and 62b in order to control reading from the memories 60a and 60b of the IFO) system.

Oa and ob are counter output signals output from the cell counters ca and cb by counting the number of ATM cells, respectively.

Further, ea and eb are first-in first-out (F
In order to control the reading of the memories 60a and 60b of the IFO) system, the controllers 65a and 62b
5b is a driver output control signal output to 5b.

The memory write control signals wa and wb and the memory read control signals ra and rb can be realized by a level signal (enable signal) or a pulse signal, respectively. Functionally equivalent.

Reference numerals 40a and 40b denote transmission request "TxReq" signals, respectively, and reference numerals 41a and 41b denote transmission available "TxClav" signals, 42a and 42, respectively.
b is a transmission enable “TxEnb” signal.

Reference numerals 43a and 43b denote a cell head "TxSOC" signal, and reference numeral 44 denotes transmission data "TxDAT".
A "signal, and a bundle of signal lines for passing these signals is a set of extended UTOPIA buses.

Next, the operation of the transmitting side circuit of the communication apparatus according to the second embodiment of the present invention will be described.

First, A in the communication device 1 shown in FIG.
The operation of the TM layer processing unit 22 will be described.

The transmission data “TxDATA” signal 44b and the memory write control signal wb are transmitted from the stack cable interface 6r to the communication device 1 via the driver 63b.
Is input to First-in-first-out (FIFO) memory 60
The write operation to b is controlled by the memory write control signal wb.

The cell counter cb counts the number of ATM cells stored in the first-in first-out (FIFO) memory 60 by monitoring the memory write control signal wb and the memory read control signal rb. ATM
The number of cells is output as a counter output signal ob.

When the counter output signal ob output from the cell counter cb is 1 or more, that is, the control unit 62b stores one or more ATs in the first-in first-out (FIFO) memory 60b.
If M cells are stored, the transmission request “Tx
Req ”signal 40b is asserted.

While the transmission request “TxReq” signal 40b is asserted, the transmission available “TxClav” signal 4 from the PHY layer processing unit 10 is output.
When the assertion of 1b is received, the transmission enable “T
xEnb "signal 42b is asserted, and a memory read control signal rb is sent to a first-in first-out (FIFO) type memory 60 to read out transmission data (ATM cells) from the first-in first-out (FIFO) type memory 60 and output the driver output. Assert the control signal eb.

Also, the cell head "TxSOC" signal 43b is asserted at the head of the ATM cell.

The operation of the ATM layer processing section 21 is to replace the driver 63b with the SAR layer processing section 63a.
That is, the data to be transmitted by the SAR layer processing unit 63a is assembled into an ATM cell, and the transmission data “TxDATA” signal 4
The operation is the same as that of the ATM layer processing unit 22 except that the memory write control signal is output and the memory write control signal is output, and the description is omitted.

Next, the operation of the interface (around the stack cable interface 6t on the transmission side) serving as an interface to the connection destination of the stack cable connection in the communication device 1 will be described.

The transmission data "TxDATA" signal 44t and the memory write control signal 42t are transmitted from the stack cable interface 6t to an external device (not shown) such as an ATM switch via the driver 63t.

The transmission data “TxDATA” signal 4
4t and the transmission data “TxDATA” signal 44 are the same for the transmitted signal.

The memory write control signal 42t is a signal for performing write control of the memory, assuming that there is a first-in first-out (FIFO) type memory in an external device (not shown) such as an ATM switch to which the memory is connected. It is.

The memory write control signal 42t may be created by taking the logical sum (OR) of the transmission enable "TxEnb" signals 42a and 42b, or a new memory write pulse may be generated.

FIG. 8 is a diagram showing a reference model on the receiving side in the communication system according to the second embodiment of the present invention.

In FIG. 8, reference numerals 91 and 92 denote extended UTOs which interface the receiving side between the physical layer and a layer higher than the physical layer in the communication devices 1 and 2, respectively.
It is a PIA bus.

Reference numeral 95 denotes a stack cable provided for connecting the communication device 1 and the communication device 2, 70 denotes a first-in first-out (FIFO) memory provided in the communication device 2, and 9 denotes an ATM. External devices such as exchanges and communication devices 1
Is a connection interface which is an interface on the receiving side provided for connecting the PHY layer processing unit 101 in the first embodiment.

[0189] In Fig. 8, the mark "○" indicates that the connection is open (no connection). With such a configuration, the communication device 1 and the communication device 2 can be realized by the same module.

In FIG. 8, the configuration other than the above is the same as the reference model on the transmitting side of the communication apparatus shown in FIG.
Description is omitted.

The physical configuration (transmission medium, transmission protocol, transmission signal) of the external interface 9 and the stack cable 95 is the same as that described in the reference model on the transmission side of the communication system shown in FIG. I do.

Memory 70 of a first-in first-out (FIFO) system
Temporarily stores the ATM cells transferred from the communication device 1 via the stack cable 95. PHY of communication device 1
When viewed from the layer processing unit 101, the communication device 2 (the input side of the memory 70 of the first-in first-out (FIFO) method)
It is regarded as the layer processing unit 22.

If there is no difference between the clock signals referred to between the extended UTOPIA bus 91 of the communication device 1 and the extended UTOPIA bus 92 of the communication device 2 and the delay does not matter in the stack cable, first-in The above-mentioned (FIFO) type memory 70 may not be provided.

In FIG. 8, first-in first-out (FI
When the FO) type memory 70 is not inserted, the extended UTOPIA bus 91 and the extended UTOPIA bus 92 are logically provided.
And become one.

Further, conceptually, an integrated extended UTO
"MATM-1PH" in which three ATM layer processing units 21, 23 and 24 are connected to PIA buses 91 and 92.
Y ”.

FIG. 9 is a diagram showing a circuit configuration on the receiving side of communication apparatus 2 shown in FIG. 8 in the communication system according to the second embodiment of the present invention.

In FIG. 9, 2 is a communication device, 10 is a PHY layer processing unit in the communication device 2, and 23 is a communication device 1
Is an ATM layer processing unit, and 24 is an ATM serving as an interface of a stack cable connection in the communication device 2.
The layer processing unit 9 is an external interface that is an interface for connecting the PHY layer processing unit 10 in the communication device 2 to an external device (not shown) such as an ATM switch.

A stack cable interface 7r and 7t are interfaces for connecting the communication device 2 and a communication device (not shown) different from the communication device 2 using a stack cable (not shown). It is.

Also, 73t and 73r are ECL, PEC
L, LVDS or the like driver IC, 99a is a stack cable interface 7r via a driver 73r
The received data “RxDATA” signal and the cell head “RxSOC” signal received from the STA.

Reference numeral 99b denotes a received data “RxDATA” signal and a cell head “RxSOC” signal received from the external interface 9 via the PHY layer processing unit 10.

Reference numeral 70 denotes a first-in, first-out (FIFO) memory which is provided in the communication device 2 and stores the received data "RxDATA" signal 99a. W is the received data “RxDATA” signal and the cell head “RxSO
This is a memory write control signal output from the driver 73r to control the writing of the "C" signal 99a to the memory of the first-in first-out (FIFO) system.

Reference numeral 99 denotes a reception data “RxDATA” signal of the extended UTOPIA bus and a cell head “RxSO
C "signal, s is a select signal for selecting whether the communication device 2 is connected to the stack cable interface 7r or the external interface 9, and 75a and 75b receive the select signal s and receive data" RxDATA "signal and cell head" RxSOC "signal. This is a driver IC that controls output to a signal line passing through the signal line 99.

Further, m is a control unit that receives a control signal from the driver ICs 75a and 75b and controls output to the ATM layer processing units 23 and 24, that is, a control unit that controls an extended UTOPIA bus, and c is a first-in first-out (FIFO) system. Memory 70
Is a cell counter for counting the number of ATM cells stored in.

The reference numeral 96a stores the received data received from the stack cable interface 7r on a first-in first-out (FI) basis.
This is a reception available “RxClav” signal output by the cell counter c to notify the control unit m that it can be obtained from the memory 70 of the FO) system.

The PHY layer processing unit 10 outputs the reception available “RxCla” 96b to inform the control unit m that the reception data received from the external interface 9 can be obtained from the PHY layer processing unit 10.
v "signal.

Reference numeral 97 denotes a reception data “RxDATA” signal and a cell head “R” via the extended UTOPIA bus.
This is a reception enable “RxEnb” signal output by the control unit m to notify that the “xSOC” signal 99 can be received.

Reference numerals 21w and 22w denote write control signals output from the control unit m to the ATM layer processing units 23 and 24 for writing received data to the ATM layer processing units 23 and 24, respectively.

Reference numeral 96 denotes a reception available “RxCl
An “av” signal, 97 is a reception enable “RxEnb” signal, 99 is a reception data “RxDATA” signal and a cell head “RxSOC” signal, and a bundle of these signals is a set of extended UTOPIA buses.

Next, the operation of the receiving side circuit of the communication apparatus according to Embodiment 2 of the present invention will be described.

First, the operation when the communication device 2 shown in FIG. 9 connects the stack cable (when the select signal S selects the stack cable connection) will be described.

When the stack cable is connected, the driver 75a is activated by the select signal s.

The received data “RxDATA” signal, cell head “RxSOC” signal 99a, and memory write control signal w are input from the stack cable interface 7r to the communication device 2 via the driver 73r.

The writing operation to the memory 70 of the first-in first-out (FIFO) system is controlled by a memory write control signal w.

The cell counter c monitors the memory write control signal w and the reception enable “RxEnb” signal 97, and thereby, the first-in first-out (FIFO) type memory 60 is used.
Is counted, and if the counted number of ATM cells is one or more, the reception available signal 96a is asserted.

When the control unit m detects the reception available signal 96 asserted via the driver 75a,
The reception enable signal 97 is asserted, and as a result, the reception data “R” is read from the first-in first-out (FIFO) memory 70.
xDATA ”signal and cell head“ RxSOC ”signal 9
9 is read from the control unit m to the ATM layer processing unit 23,
The write control signals 21w and 22w output to the control unit 24 are transferred to the ATM layer processing units 21 and 22, respectively.

The ATM layer processing unit 2 is connected to another communication device (not shown) connected to the communication device 2 via the stack cable interface 7t by a stack cable.
4, the received data "RxDATA" signal from the stack cable interface 7t and the cell head "RxS"
When transferring the “OC” signal 99, the driver 73t becomes active, and the received data “RxDATA” signal, the cell head “RxSOC” signal 99 and the write control signal 2
2w is transmitted by the stack cable.

When the communication device 2 is connected to an external device (not shown) such as an ATM switch via the external interface 9 and the PHY layer processing section 10 is functioning, the driver 75b is operated by the select signal s. Become active.

In this case, driver 75a is inactive. When the driver 75b is active, it is functionally the same as the state of the communication device 1 shown in FIG.

When the communication device 2 is connected to an external device (not shown) such as an ATM switch via the external interface 9, the operation when the PHY layer processing section 10 functions is the same as that of the conventional communication device. Since the operation is the same as that of the first embodiment, the description is omitted.

In the communication devices 1 and 2 shown in FIGS. 7 and 9, a case has been described in which the bus selection method using the driver ICs 65a, 65b, 75a, and 75b is employed. Is also possible.

In the configuration of the communication system shown in FIGS. 6 and 8, the interface data transfer procedure in communication apparatuses 1 and 2 is the same as the interface data transfer procedure in the communication apparatus described in the first embodiment. Since there is, description is omitted.

In order to simplify the description, FIGS.
In the configuration of the communication system shown in (1), a two-stage stack configuration has been described as an example, but a stack configuration with three or more stages may be used. This case can be realized by sequentially connecting the communication devices having the same configuration as the communication device 2 shown in FIG.

With the above configuration, in the communication system according to the second embodiment of the present invention, a plurality of communication devices can be connected by a stack cable, and the transmission line band of the external interface can be controlled by the plurality of communication devices. Can be used effectively.

Further, by realizing the above configuration, it is possible to easily set a bypass route when the communication device or an internal module of the communication device fails.

Embodiment 3 Embodiment 2 according to the present invention
Has shown a configuration in which a plurality of communication devices are connected in a daisy chain when a plurality of communication devices are connected with a stack cable, but a configuration in which a star-type connection may be used.

The communication system according to the third embodiment of the present invention has a plurality of communication devices connected in a star-shaped stack cable.

FIG. 10 is a diagram showing a reference model on the transmitting side in the communication system according to the third embodiment of the present invention.

In FIG. 10, reference numerals 1, 2, and 3 denote communication devices. Reference numerals 101, 102, and 103 denote PHY layer processing units that process physical layer protocols in the communication devices 1, 2, and 3, respectively. The PHY layer processing unit is one embodiment of the “physical layer processing unit” described in the claims.

Reference numerals 21, 22, and 23 denote ATM layer processors which process protocols higher than the physical layer in the communication device 1, respectively. Reference numerals 24 and 25 each process protocols higher than the physical layer in the communication device 2. The ATM layer processing units 26 and 27 are ATM layer processing units that process protocols higher than the physical layer in the communication device 3. The ATM processing unit 2
Each of 1, 22, 23, 24, 25, 26, and 27 is an embodiment of the "upper layer processing means" described in the claims.

Reference numerals 81, 82, and 83 denote interfaces on the transmitting side of the extended UTOPIA bus, which are interfaces of the physical layer and layers higher than the physical layer in the communication devices 1, 2, and 3, respectively. A stack cable 86 provided for connecting the device 2 and a stack cable 86 provided for connecting the communication device 1 and the communication device 3 are provided. In addition, extended UTO
Each of the PIA buses 81, 82, and 83 is an embodiment of the "internal connection means" described in the claims.

Reference numerals 61 and 62 designate first-in first-out (FIFO) memories provided in the ATM layer processing units 22 and 23 of the communication device 1, respectively.
Is a first-in, first-out (FIFO) type memory provided in the ATM layer processing unit 25 in FIG.

Reference numeral 8 denotes a connection interface which is a transmission-side interface provided for connecting an external device (not shown) such as an ATM switch and the PHY layer processing unit 101 in the communication device 1. The connection interface 8 is an embodiment of the "second external connection means" described in the claims.

[0233] In Fig. 10, a mark "O" indicates that the connection is open (no connection).

The physical configuration (transmission medium, transmission protocol, transmission signal) of the external interface 8 and the stack cables 85 and 86 are described in the reference model on the transmission side of the communication system shown in FIG. 6 (Embodiment 2). Since they are the same, the description is omitted.

Memory 61 of a first-in first-out (FIFO) system
Temporarily stores the ATM cells transferred from the communication device 3 via the stack cable 86. When viewed from the communication device 3, the ATM layer processing unit 23 of the communication device 1 is regarded as the PHY layer processing unit 103.

Similarly, the first-in-first-out (FIFO) type memory 62 temporarily stores ATM cells transferred from the communication device 2 via the stack cable 85. When viewed from the communication device 2, the ATM layer processing unit 22 of the communication device 1
It is regarded as the HY example or the processing unit 102.

The extended UTOPIA bus 81 in the communication device 1 has one PHY layer processing unit 101 and an ATM
A layer processing unit 21, an ATM layer processing unit 22 including first-in first-out (FIFO) memories 61 and 62,
23 ATM layer processing units are connected,
The communication system shown in FIG. 10 is “MATM-1PHY”
Of the reference model.

The operation of the communication devices 1, 2, and 3 in the configuration of the communication system shown in FIG. 10 is the same as the operation of the communication device shown in FIGS. 1 to 3 (Embodiment 1). Omitted.

Extended UTOP in Communication Devices 1, 2, and 3
If there is no deviation between the clock signals to be referred to on the IA buses 81, 82, and 83 and no delay is a problem in the stack cables 85 and 86, the first-in first-out (FIFO) memories 61 and 62 are unnecessary. It is.

In FIG. 10, first-in first-out (F
If the memories 61 and 62 of the IFO (system) are not inserted, the extended UTOPIA buses 81, 82 and 83 are logically integrated.

Also, conceptually, an integrated extended UTO
One PHY layer processing unit 101 and four ATM layer processing units 21 and 2 for PIA buses 81, 82 and 83
"MATM-1PHY" to which 4, 26 and 27 are connected
Is a reference model.

Note that the configuration and operation of the transmission side circuit in the communication devices 1, 2, and 3 in the communication system shown in FIG. 10 are the same as the configuration and operation of the transmission side circuit in the communication device shown in FIG. The description is omitted.

FIG. 11 is a diagram showing a reference model on the receiving side in the communication system according to Embodiment 3 of the present invention.

In FIG. 11, reference numerals 1, 2, and 3 denote communication devices. Reference numerals 101, 102, and 103 denote PHY layer processing units that process physical layer protocols in the communication devices 1, 2, and 3, respectively.

Reference numerals 21 and 22 denote A which processes a protocol higher than the physical layer in the communication device 1.
Each of the TM layer processing units 23 and 24 processes a protocol higher than the physical layer in the communication device 2.
Each of the TM layer processing units 25 and 26 processes a protocol higher than the physical layer in the communication device 3.
It is a TM layer processing unit.

Reference numerals 91, 92 and 93 denote extended UTOPIA bus receiving interfaces serving as interfaces of the physical layer and layers higher than the physical layer in the communication devices 1, 2, and 3, respectively.

Reference numeral 95 denotes a stack cable provided for connecting the communication device 1 and the communication device 2, 96 denotes a stack cable provided for connecting the communication device 1 and the communication device, 71, 72, Reference numeral 73 denotes a first-in first-out (FIFO) memory provided in each of the communication devices 1, 2, and 3.

Reference numeral 9 denotes a connection interface, which is an interface on the receiving side provided for connecting an external device (not shown) such as an ATM switch and the PHY layer processing unit 101 in the communication device 1.

[0249] In Fig. 11, the mark "O" indicates that the connection is open (no connection).

The physical configuration (transmission medium, transmission protocol, transmission signal) of the external interface 9 and the stack cables 95 and 96 are described in the reference model on the transmission side of the communication system shown in FIG. 6 (Embodiment 2). Since they are the same, the description is omitted.

A first-in first-out (FIFO) type memory 72
Temporarily stores the ATM cells transferred from the communication device 1 via the stack cable 95. PHY of communication device 1
When viewed from the layer processing unit 101, the communication device 2 (the input side of the memory 72 of the first-in first-out (FIFO) system)
It is regarded as the layer processing unit 22.

Similarly, the first-in first-out (FIFO) memory 73 temporarily stores the ATM cells transferred from the communication device 1 via the stack cable 96. When viewed from the PHY layer processing unit 101 of the communication device 1, the communication device 3
(Input side of the first-in first-out (FIFO) type memory 73)
Is regarded as the ATM layer processing unit 22.

Extended UTOP in Communication Devices 1, 2, and 3
If there is no deviation between the clock signals to be referred to in the IA buses 91, 92, and 93 and no delay is a problem in the stack cables 95 and 96, the first-in first-out (FIFO) memories 72 and 73 are unnecessary. It is.

In FIG. 11, if the first-in first-out (FIFO) memories 72 and 73 are not inserted into the communication devices 2 and 3, respectively, the extended UTOPIA buses 91 and 9 are logically provided.
2, 93 are integrated.

In addition, conceptually, an integrated extended UTO
One PHY layer processing unit 101 and four ATM layer processing units 21 and 2 for PIA buses 91, 92 and 93
The reference model of “MATM-1PHY” to which 3, 25, and 26 are connected.

Note that the configuration and operation of the receiving circuit in the communication devices 1, 2, and 3 in the communication system shown in FIG. 11 are the same as the configuration and operation of the receiving circuit in the communication device shown in FIG. The description is omitted.

In the configuration of the communication system shown in FIGS. 10 and 11, the interface data transfer procedure in communication apparatuses 1, 2, and 3 is the same as the interface data transfer procedure in the communication apparatus described in the first embodiment. The description is omitted because it is the same.

Further, for simplicity of description, the configuration of the communication system shown in FIGS. 10 and 11 has been described using a two-stage stack configuration as an example, but a stack configuration of three or more stages may be used. In this case, it can be realized by sequentially connecting communication devices having the same configuration as the communication device 2 shown in FIG.

With the above configuration, in the communication system according to the third embodiment of the present invention, a plurality of communication devices can be connected in a star-shaped stack cable, and the transmission line band of the external interface can be adjusted to a plurality of channels. It can be used effectively by communication devices.

Further, by realizing the above configuration, it is possible to easily set a bypass route when the communication device or an internal module of the communication device fails. Further, the degree of freedom of connection between the communication devices can be made more flexible.

In addition, the configuration described in Embodiment 2 (connection of daisy-chain type stack cables) and Embodiment 3
May be combined with the configuration described in (1) (star-type stack cable connection).

[0262]

As described above, according to the first communication system of the present invention, a plurality of communication devices can be connected by a stack cable, and the transmission line band of the external interface can be made effective by the plurality of communication devices. Available to Further, it is possible to easily set a bypass route when the communication device or an internal module of the communication device fails.

Further, according to the second communication system of the present invention, it is possible to connect a plurality of communication devices in a tiered stack cable, and to effectively use the transmission line band of the external interface by the plurality of communication devices. it can. Also,
By realizing the above configuration, it is possible to easily set a detour path when the communication device or an internal module of the communication device fails.

Further, according to the third communication system of the present invention, it is possible to connect a plurality of communication devices in a stack cable in a star shape, and to effectively use the transmission path band of the external interface by the plurality of communication devices. it can. Further, it is possible to easily set a bypass route when the communication device or an internal module of the communication device fails. Further, the degree of freedom of connection between the communication devices can be made more flexible.

Further, according to the fourth communication system of the present invention, even when there is a difference between clock signals to be referred to between the extended UTOPIA buses in the communication device and when a delay becomes a problem in the stack cable. Therefore, correct communication without missing data can be performed.

Further, according to the fifth communication system of the present invention, in a specific usage such as when an external device such as an ATM switch is externally connected to the PHY layer processing unit, it is compared with a configuration using an ATM switch. This is advantageous in terms of multiplicity in multiplexing at an external interface with an external device such as an ATM switch.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an interface on a transmission side in a communication device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a multiplexed configuration of an extended UTOPIA bus in the communication device according to the first embodiment of the present invention.

FIG. 3 is a sequence diagram showing a data transfer procedure in a transmission-side interface of the communication device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an interface on a receiving side in the communication device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing another configuration of the interface on the receiving side in the communication device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a reference model on a transmitting side in a communication system according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration on a transmitting side of a communication device in a communication system according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a reference model on a receiving side in a communication system according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a circuit configuration on a receiving side of a communication device in a communication system according to a second embodiment of the present invention.

FIG. 10 is a diagram showing a reference model on a transmitting side in a communication system according to a third embodiment of the present invention.

FIG. 11 is a diagram showing a reference model on a receiving side in a communication system according to a third embodiment of the present invention.

FIG. 12: “ATM Forum UTOPIA Le”
2 is a diagram showing a reference model of a UTOPIA bus in the specification of “vel 1”. FIG.

FIG. 13: “ATM Forum UTOPIA Le”
2 is a diagram showing a reference model of a UTOPIA bus in the specification of “vel 2”.

FIG. 14: “ATM Forum UTOPIA Le”
2 is a diagram showing a reference model of a UTOPIA bus in the specification of “vel 2”.

FIG. 15: “ATM Forum UTOPIA Le”
2 is a diagram showing a reference model of a UTOPIA bus in the specification of “vel 2”.

FIG. 16: “ATM Forum UTOPIA Le”
2 is a diagram illustrating a configuration of an interface on the transmission side in the specification of “level 1”. FIG.

FIG. 17: “ATM Forum UTOPIA Le”
2 is a diagram illustrating a configuration of an interface on the receiving side in the specification of “level 1”. FIG.

FIG. 18: “ATM Forum UTOPIA Le”
2 is a diagram showing a configuration of an interface on the transmission side in the specification of “vel 2”.

FIG. 19: “ATM Forum UTOPIA Le”
2 is a diagram showing a configuration of an interface on the receiving side in the specification of “vel 2”.

[Explanation of symbols]

1, 2, 3 Communication device 4t, 4r Set of extended UTOPIA bus 8, 9 External interface 10, 101, 102 PHY layer processing unit 21, 22, 23, 24, 25, 26, 27 ATM layer processing unit 60, 61, 62, 63 First-in first-out (FIFO) type memory 70, 71, 72, 73 First-in, first-out (FIFO) type memory 81, 82, 83, 91, 92, 93 Extended UTOPI
A bus 85, 86, 95, 96 Stack cable 5 ATM switch In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] 1. One physical layer processing means for processing a protocol of a physical layer, a plurality of interconnected upper layer processing means for processing a protocol of a layer higher than the physical layer, and the one physical layer processing A plurality of communication devices each comprising: an internal connection means for connecting a plurality of means and the plurality of interconnected upper layer processing means; and connecting the upper layer processing means in the communication device to the internal connection of another communication device. A communication system comprising: external connection means for connecting to the means. 2. The external connection means connects one upper layer processing means of the communication device to the internal connection means of another communication device, and connects the communication devices in a rosary. The communication system according to claim 1, wherein: 3. The external connection means connects the plurality of upper layer processing means of the communication device to the internal connection means of another communication device, respectively, and connects the communication devices in a star shape. The communication system according to claim 1, wherein: 4. The communication apparatus according to claim 1, wherein said upper layer processing means or said internal connection means connected to said external connection means has a first-in first-out memory. A communication system according to claim 1. 5. The communication system according to claim 1, wherein said physical layer processing means includes second external connection means connected to an external device.