JP2000307430A - Sigma delta type d/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the sigma delta type D/A converter of high quality which is suppressed in the adverse effect of a phase shift between a sample clock and a noise shaper clock. SOLUTION: A prefetch register 1 is provided right before a previousvalue hold register 3 which perform oversampling for a noise shaper part and a phase shift part 2 switches the phase of the operating clock of the prefetch register 1 according to the phase difference between a sample clock and a prefetch clock to vary the substantial oversampling rate of the previous-value hold register 3. Consequently, the generation of distortion when the sample clock and noise shaper clock do not synchronize with each other can be suppressed to a practical level. Consequently, the sigma delta type D/A converter is usable even for uses which were impossible because of the problem of clock jitters.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a D / A conversion circuit.

[0002]

2. Description of the Related Art At present, some digital audio devices use a sigma-delta D / A converter. This is because after oversampling the input sample data, the noise shaper performs a noise shaper operation in accordance with a noise shaper clock having a frequency several times to several tens times higher than the frequency of the sample clock, thereby re-quantizing the noise in the audio band. That is to suppress. For this reason, the oversampling unit interpolates the input data using the previous value hold or linear interpolation, and oversamples the input sample data at the clock frequency of the noise shaper unit. Here, the oversampling magnification (hereinafter referred to as “Nos”) means a magnification indicating how many times the clock frequency of the noise shaper unit after oversampling is higher than the sample clock. Such a sigma-delta D / A converter is, for example, as shown in FIG. The input sample data is once input to the input register 71, and the input sample data is output according to the sample clock. This output is oversampled by the previous value hold register 72. The previous value hold register 72 captures and holds the input sample data using a clock obtained by dividing the noise shaper clock by Nos. That is, each time the noise shaper unit operates the same number of times as Nos, the input sample data is set to 1 in the previous value hold register.
And the same data is output to the noise shaper unit as many times as Nos. The noise shaper section includes a noise shaper operation section 73, a quantizer 74, and an adder 7
5, the noise shaper operation is performed at an operation rate several times to several tens times higher than the input sample rate. Quantizer 7
The output of No. 4 is converted into an analog quantity by an analog conversion unit 76 including a PWM circuit, a low-pass filter and the like.
Although the noise shaper unit is divided into blocks such as the noise shaper operation unit 73, the quantizer 74, and the adder 75 for convenience of explanation in FIG. 3, the noise shaper operation is actually performed as a whole. .

In general, a D / A converter converts input digital data into an analog amount in accordance with the timing of a conversion clock, and outputs the analog amount. Each digital data is reflected in a converted analog waveform. The time span occupied must be exactly the same. If there is a time variation (jitter) in the conversion clock cycle, a variation occurs in the time width occupied by each input sample data, and the analog waveform is distorted.

In particular, in the case of a sigma-delta type D / A converter, since the noise shaper unit converts the analog amount at a high clock frequency, the fluctuation rate is large even if the jitter has the same time width. turn into. Also, due to the principle of operation of the noise shaper, a huge amount of quantization noise components exist in the frequency band higher than the audio frequency band, and the interaction between clock jitter and this quantization noise component causes large distortion in the analog waveform. There is a property that it occurs. For this reason, a high-precision clock without jitter is required for the conversion clock of the sigma-delta D / A converter. Therefore, in the sigma-delta D / A converter, a clock is generated in a block on the D / A converter side, and this clock is supplied to an input sample data generation block to synchronize with the clock on the D / A converter side. The method of obtaining input sample data has been commonly used. With this method, it is possible to supply a clock with high jitter accuracy to the D / A converter.

[0005]

However, in the above method, it is necessary to send a clock from the D / A converter to the input sample data generation block to control this block. Only applicable to relatively small system configurations. For example, it cannot be applied to a system in which the data generation side cannot be controlled from the reception side, such as an FM broadcast or TV broadcast receiver, or a D / A converter that receives digital data generated by another device.

That is, when digital data input from the outside is D / A converted by a sigma-delta D / A converter, the following methods are conceivable, but all have problems.

In the first method, a multiplied clock synchronized with a sample clock input from the outside is created by a PLL or the like, and is used for D / A conversion.
In this method, the clock obtained by the PLL has a problem in jitter quality, and there is a limit in improving the quality by devising the PLL configuration. This method requires a clock Nos times the sample clock. It is difficult to use it for a sigma-delta D / A converter.

A second method is to generate a high-precision clock by a crystal oscillator or the like on the D / A converter side asynchronously with a sample clock input from the outside, and to perform D / A conversion using the clock. It is. Regarding such a problem, for example, FIGS. 8A and 8B show a case where the sample clock in the sigma-delta D / A converter of FIG.
A, the state of the input sample data output from the input register 71 is 8B, the noise shaper clock is C, the hold clock of the previous value hold register 72 is 8D, and the state of the sample data output from the previous value hold register 72 is 8E. explain. If the hold time of the previous value hold register obtained by multiplying the cycle of the noise shaper clock by Nos is longer than the sample clock cycle, the conversion operation cannot be completed in time and the input sample data is ignored. Also, as shown in FIG. 8B, if the hold time is shorter than the sample clock cycle, the input sample data cannot be made in time, and the same input sample data is D / A converted twice. .
Even if the period of the sample clock and the hold time are almost the same, the phases are gradually shifted due to the lack of synchronization with each other, and one of the above two problems occurs. As described above, in the asynchronous system, the input sample data is ignored or the same data is D / A twice.
The analog waveform is greatly distorted due to the difference in the number of input / output samples, such as when the time width of the input sample data occupying the converted analog waveform becomes zero or double due to the conversion.

The third method is as follows. The D / A converter-side block generates a conversion clock having a frequency equal to Nos times the frequency of the sample clock asynchronously with a sample clock input from the outside. Also, the input sample data is temporarily stored in the FIFO buffer according to the sample clock. Next, the read clock obtained by dividing the conversion clock by (1 / Nos) is
The input sample data is read from the I / O buffer, applied to the noise shaper operation unit, and D /
A conversion is performed. The difference in the number of input / output samples due to the lack of synchronization between the sample clock and the data read clock is absorbed by the increase or decrease in the number of data stored in the FIFO buffer. As long as the number of input / output samples does not exceed the number of data that can be held in the FIFO buffer or becomes 0 or less,
An analog waveform without distortion can be obtained. However, there is a need for a FIFO buffer having a capacity corresponding to the maximum phase error (= continuous reproduction time × frequency error) between the sample clock and the data read clock, and the system configuration becomes complicated and large in scale. Have. In addition, the input is delayed by an amount corresponding to the number of data stored in the FIFO buffer, and cannot be used for applications requiring a real-time response.

Further, in any of the first to third methods, when the phase of the sample clock coincides with the phase of the operation clock of the noise shaper, a phenomenon similar to chattering occurs. In other words, a fluctuation corresponding to the hold time ± 1 occurs according to a minute fluctuation of the jitter of the sample clock.

[0011]

Therefore, according to the present invention, the oversampling ratio (No.
s) is made variable, and a device is adopted to absorb the phase error between the hold clock and the sample clock due to the synchronization between the sample clock and the noise shaper clock. For example, when the frequency of the noise shaper clock is originally set to operate at Nos = 48, if the phase error due to non-synchronization accumulates and reaches a certain value, the oversampling magnification (No.
s) is set to +1 to 49 or -1 to 47 to absorb the phase error. At this time, the variation rate of the sample time width is suppressed to a relatively small value of ± 1 / Nos.

A prefetch register is provided immediately before the previous value hold register. Input sample data is once taken into this register according to a prefetch clock obtained by shifting the phase of the noise shaper clock, and then output to the previous value hold register. The prefetch clock and the sample clock are monitored, and when the sample and hold timing of the sample data and the sample and hold timing of the prefetch clock are close to each other, the phase shift is optimized from among a plurality of values. Select and set things. As a result, it is possible to prevent a problem that a large fluctuation occurs in the oversampling magnification in accordance with a minute jitter fluctuation of the sample clock due to the coincidence of the two timings.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A pre-value hold register for oversampling input sample data input in accordance with a sample clock at a substantially specific oversampling factor;

A noise shaper section for performing a noise shaper operation on the output of the preceding value hold register in accordance with a noise shaper clock having a frequency obtained by multiplying the frequency of the sample clock by the oversampling magnification; A control circuit for changing the oversampling magnification of the previous value hold register to a value obtained by adding +1 or -1 to the initial value at a timing when the phase error is accumulated and becomes close to one cycle of the sample clock. Method D /
It is preferred to configure an A-converter.

A prefetch register for sampling and holding input sample data input in accordance with a sample clock with a prefetch clock obtained based on a noise shaper clock having a frequency obtained by multiplying a specific oversampling factor of the frequency of the sample clock; A pre-value hold register that samples and holds the output of the register according to the noise shaper clock and oversamples the input sample data substantially at the oversampling ratio; and a noise shaper that outputs the output of the pre-value hold register according to the noise shaper clock. A noise shaper unit for performing an operation, and selecting one of a plurality of clocks having different phases from the noise shaver clock to select the prefetch clock And, the timing of the sample hold timing for both monitors and the prefetch clock and the sample clock becomes close to each other, by switching the clock, the oversampling ratio of the previous value holding register to the initial value +1
Alternatively, it is also preferable to configure a sigma-delta D / A converter including a control circuit that changes the value to a value obtained by adding -1.

The control circuit preferably switches between a clock having a phase shift in the leading direction with respect to the noise shaper clock and a clock having the same shift width as the leading clock and having a phase shift in the delay direction. . Further, the control circuit generates a clock generated at the sample and hold timing of the sample clock and obtained by ANDing a clock having a pulse width overlapping with the plurality of clocks and the selected clock at the specific timing. It is also preferable to use a prefetch clock.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Details of a sigma-delta type D / A converter according to the present invention will be described with reference to an embodiment shown in FIG.

In FIG. 1, the components denoted by the same reference numerals as those in FIG. 7 indicate the same components as those shown in FIG. 7, and their operations are the same as those described above. This example is a sigma-delta type D / A converter having a noise shaper section that operates with a noise shaper clock that is asynchronous with the sample clock.
Implement the conversion. In the figure, 1 is a prefetch register, 2 is a phase shift unit as a control circuit,
3 is a previous value hold register.

The prefetch register 1 includes a phase shift unit 2
The output of the input register 71 is fetched and held, that is, sampled and held, and output in accordance with the prefetch clock output from the FF. The input register 71 samples and holds input sample data input from the outside according to a sample clock.

As shown in FIG. 2, the phase shift unit 2 includes a first phase shifter 21, a second phase shifter 22, and a selection circuit 23.
And a determination circuit 24. First phase shifter 2
Both the first and second phase shifters 22 receive the noise shaper clock, and each of them receives +
A clock P1 having a phase shift of 90 degrees and -90 degrees,
Generates P2. The selection circuit 23 receives the selection signal from the determination circuit 24 and selectively outputs the clocks P1 and P2, and the output becomes the prefetch clock. The determination circuit 24 receives the sample clock and the prefetch clock, compares the phases of the two, and switches the state of the selection signal at a timing when the phases are close to each other.
By switching this state, the clock output from the selection circuit 23 is switched. As will be described later, this switching is performed immediately before the phase error due to the non-synchronization of the sample clock and the noise shaper clock reaches one sample clock. Thus, the oversampling magnification of the previous value hold register 3 in FIG. 1 is changed to a value obtained by adding +1 or −1 to its initial value to absorb the phase error, and the input sample data is ignored or the same data is output twice. This prevents D / A conversion. The previous value hold register 3 samples and holds the output of the prefetch register according to the noise shaper clock. In FIG. 1, a noise shaper unit including a noise shaper operation unit 73, a quantizer 74, and an adder 75 performs a noise shaper operation according to a noise shaper clock. The analog converter 76 converts the output of the noise shaper into an analog amount and outputs the analog amount.

Next, the operation of the present embodiment will be described with reference to the timing charts of FIGS. 3 and 4 in addition to FIGS. 1 and 2 described above. 3, A is a sample clock, B is input sample data output from the input register 71, C is a prefetch clock output from the phase shift unit 2, and D is sample data output from the prefetch register. , E are prefetch clocks, and F is sample data output from the previous value hold register. In FIG. 4, P1 and P2 are +90 degrees with respect to the noise shaper clock as described above,
Clocks P1 and P2 having a phase shift of −90 degrees are shown, and G is a selection signal output from the determination circuit 24. In this figure, the same reference numerals as those shown in FIG. 3 indicate the same signals as those in FIG.

The input register 71 samples and holds the input sample data at the falling timing of the sample clock A, and the sample data output at each such sample and hold timing changes in the order of a, b, c, and d. The prefetch register 1 samples and holds the output of the input register 71 every time the prefetch clock C falls. The previous value hold register 3 samples and holds the output of the prefetch register 1 every time the noise shaper clock E falls.

Here, for convenience of explanation, the substantial oversampling magnification of the previous value hold register 3 is set to Nos = 4.
There is. That is, the hold time in the previous value hold register 3 is usually equal to the No. of the cycle of the noise shaper clock.
s (= 4) times. Also, sample clock A
And the noise shaper clock E are asynchronous, and the data hold time is shorter than the sample clock cycle.
Even if the phases of the sample clock A and the noise shaper E match at a specific timing, the phases gradually shift. The phase error is accumulated, and when the phases of the sample clock A and the noise shaper E match again,
This is equivalent to one cycle of the sample clock A. At such a timing, in the related art, the input sample data is ignored, or the same data is subjected to D / A conversion twice, so that the time width of the input sample data in the converted analog waveform becomes zero. Or twice as a result,
The distortion of the analog output waveform is caused by the difference in the number of input / output samples.

Immediately before such timing, the phase shifter 2 performs the following operation. As shown in FIG. 4, if the clock P1 in which the phase of the noise shaper clock E is shifted by +90 degrees is initially selected as the prefetch clock C, the phase of the clock P1 approaches the phase of the sample clock A. Judgment circuit 24
When the difference between the phase of the clock P1 and the phase of the sample clock A becomes H within a predetermined range, it is determined that the sample hold timings of the clock P1 and the sample clock A are close to each other, and the selection signal G is changed from "H" to It is set to “L”. Upon receiving this, the selection circuit 23 changes its output to the clock P2 obtained by shifting the phase of the noise shaper clock E by -90 degrees.
Switch to.

This switching is shown in FIG. 3 as occurring at the timing of the sample data b, whereby the oversampling magnification of the previous value hold register 3 is set to Nos = 5 to absorb the phase error. This allows
As is clear from comparison with the timing chart of FIG. 8B of the conventional device, the time variation per sample data sampled and held in the previous value hold register 3 is reduced. That is, the time width of the sample data does not become zero or double, and the distortion of the analog output waveform can be suppressed. The change of Nos is due to the switching of the phase of the prefetch clock, and returns to Nos = 4 in the next sample data c.

As shown in FIG. 4, the phase of the prefetch clock C and the phase of the sample clock A again fall below the predetermined value H, and the determination circuit 24 sets the selection signal G to "L".
To “H”. Upon receiving this, the selection circuit 23 switches its output to the clock P1.

When the phase of the sample clock A coincides with the phase of the prefetch clock C, the hold time of the previous value hold register fluctuates finely by the prefetch clock + 1 or -1 pulse in response to fine jitter fluctuation. However, by monitoring the sample clock A and the prefetch clock C and switching between the clocks P1 and P2 when the phase difference between the two falls within a predetermined range, it is possible to prevent the operation from continuing with the two phases in agreement. In addition, the variation of the oversampling magnification can be minimized.

Although not shown, when the hold time is longer than the sample clock cycle, the oversampling magnification is reduced by -1 by switching the prefetch clock, and the data is ignored as shown in FIG. That can be avoided.

As described above, in the above embodiment, by making the oversampling magnification variable, it is possible to suppress the occurrence of distortion when the sample clock and the noise shaper clock are not synchronized to a practical level.
This makes it possible to use the sigma-delta D / A converter even in applications where clock jitter has conventionally been a problem and cannot be used.

Further, since the oversampling magnification is automatically determined by the relative relationship between the sample clock and the noise shaper clock during operation, it is possible to use any combination of the two clocks. That is, any noise shaper clock can be used as long as the frequency is an integer multiple of the frequency of the sample clock.

Further, when the configuration of the present embodiment is applied to a configuration in which the sample clock and the noise shaper clock are synchronized, not only the degree of freedom of the combination of the two clocks is increased, but also the above-mentioned adverse effect due to the jitter is eliminated. It can be suppressed.

In the above embodiment, the clock output from the phase shift unit has the same frequency as the noise shaper clock. However, the present invention is not limited to this. For example, a phase shift unit may be configured as shown in FIG. The output of each unit in FIG. 5 is shown in the timing chart of FIG. In FIG. 5, reference numeral 51 denotes a frequency dividing circuit, and a noise shaper clock E
Is divided by 1/8 to generate clocks P51 and P52 which are 180 degrees out of phase with each other. 52 and 53 are phase comparison circuits. The phase comparison circuit 52 compares the sample clock A with the clock P51, and generates an output at a timing when the falling edge of the sample clock A and the clock P51 overlap. The comparison circuit 53 compares the sample clock A with the clock P52, and generates an output when the falling edge of the sample clock A and the clock P52 overlap. Reference numeral 54 denotes a selection circuit, which responds to outputs from the phase comparison circuits 52 and 53 by using clocks P51 and P51.
P52 is selectively output, and the phase comparison circuit 5
When the output from the phase comparison circuit 53 is received, the clock P52 is output. Reference numeral 55 denotes a phase shifter, which outputs a clock P53 with the phase of the sample clock shifted. Here, the phase of the sample clock is delayed by the period of the “H” state. Reference numeral 56 denotes an AND gate, which performs an AND operation on the clock P54 output from the selection circuit 54 and the clock P53 output from the phase shifter, and outputs the result. The clock P5 output from the AND gate 56
5 is substantially synchronized with the sample clock, and is used as a prefetch clock. Other configurations may be the same as those of the above-described embodiment, and the same operation and effect as those of the above-described embodiment can be obtained even when the phase shift unit shown in FIG.

[0033]

According to the present invention, the occurrence of distortion when the sample clock and the noise shaper clock are not synchronized can be suppressed to a practical level. This allows
The sigma-delta D / A converter can be used even in applications where clock jitter has conventionally been a problem and cannot be used.

Since the oversampling magnification is automatically determined by the relative relationship between the sample clock and the noise shaper clock during operation, it is possible to use any combination of the two clocks. That is, any noise shaper clock can be used as long as the frequency is an integer multiple of the frequency of the sample clock.

Further, when the present invention is applied to a device in which the sample clock and the noise shaper clock are synchronized, it is possible to suppress an adverse effect due to jitter fluctuation of the sample clock.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration of a sigma-delta D / A converter according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a configuration of a main part of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIG. 1;

FIG. 4 is a timing chart for explaining the operation of FIG. 2;

FIG. 5 is an explanatory diagram for explaining a configuration of another embodiment.

FIG. 6 is a timing chart for explaining the operation of FIG. 5;

FIG. 7 is an explanatory diagram showing a configuration of a conventional sigma-delta D / A converter.

FIG. 8 is a timing chart for explaining the operation of FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 prefetch register 2 phase shift unit (control circuit) 3 previous value hold register 73 noise shaper operation unit (noise shaper unit) 74 quantizer (noise shaper unit) 75 adder (noise shaper unit) 21 first phase shifter (control Circuit) 22 second phase shifter (control circuit) 23 selection circuit (control circuit) 24 determination circuit (control circuit) 51 frequency dividing circuit (control circuit) 52 phase comparison circuit (control circuit) 53 phase comparison circuit (control circuit) 54 Selection circuit (control circuit) 55 Phase shifter (control circuit) 56 AND gate (control circuit)

Claims (4)

[Claims] 1. A pre-value hold register for oversampling input sample data input in accordance with a sample clock at a substantially specific oversampling factor, and a noise having a frequency obtained by multiplying the frequency of the sample clock by the oversampling factor. A noise shaper unit that performs a noise shaper operation on the output of the previous value hold register in accordance with the shaper clock; and a timing at which a phase error between the noise shaper clock and the sample clock is accumulated and becomes close to one cycle of the sample clock. Set the oversampling magnification of the previous value hold register to +1 or -1 as the initial value.
And a control circuit for changing the value to a value obtained by adding. 2. A prefetch register for sampling and holding input sample data input in accordance with a sample clock with a prefetch clock obtained based on a noise shaper clock having a frequency obtained by multiplying a specific oversampling factor of the frequency of the sample clock, A pre-value register that samples and holds the output of the prefetch register in accordance with the noise shaper clock, and oversamples input sample data substantially at the oversampling ratio; and outputs the output of the pre-value hold register in accordance with the noise shaper clock. A noise shaper unit for performing a noise shaper operation; and selecting one of a plurality of clocks having a different phase shift from the noise shaver clock to select the prefetch clock. The prefetch clock and the sample clock are monitored, and the clock is switched at a timing when the sample and hold timings of both are close to each other, so that the oversampling magnification of the previous value hold register is increased by +1 to the initial value. Or a control circuit for changing the value to a value obtained by adding -1. 3. The control circuit switches between a clock having a phase shift in a leading direction with respect to the noise shaper clock and a clock having a phase shift in a delay direction with the same shift width as the leading clock. The sigma-delta D / A converter according to claim 2, wherein: 4. The control circuit is generated at a sample and hold timing of the sample clock, and is obtained by ANDing a clock having a pulse width overlapping with the plurality of clocks and the selected clock at the specific timing. 3. The sigma-delta D / A converter according to claim 2, wherein a clock is the prefetch clock.