JP2000305778A - Instruction processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve program execution performance by means of eliminating the useless access of DRAM by stopping the reading of an instruction when a branch instruction is detected and re-starting the reading when the branch instruction is executed. SOLUTION: A branch instruction code detecting means 118 detects the branch instruction at the moment when the fetched instruction still exists on an instruction bus. Then the code detecting means is inputted to the access stop terminal 121 of a selective memory access means 116, and the means 116 stops access until a next access re-start control input is obtained. The branch instruction is stored in a fetch control part just as the normal instruction, decoded and executed so that it is decided whether branching occurs. Then the instruction is accessed by a proper address based on the judgement of the condition. As a result, the fetched instruction is outputted to the instruction bus. Then the next correct instruction is stored in the fetch control part, decoded as a normal instruction after that and executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed processor LS.
In particular, the present invention relates to a pipeline processor having an instruction prefetch mechanism in which a main memory is also mounted on the same chip.

[0002]

2. Description of the Related Art Advances in LSI miniaturization manufacturing technology have enabled large-scale logic gates and DRAMs (Dynamic Random Access Memory) to be mounted together on a single chip. is there.

A high-speed SRAM (static random access memory) conventionally used as an on-chip memory does not have an overhead at the time of access but has a small capacity. Since the capacity of the DRAM is sufficiently large, the main memory can be constituted only by the on-chip memory.

FIG. 8 shows a configuration 880 of a conventional processor chip of a simple DRAM mixed type. DRAM requires much longer access cycle time than SRAM due to sense amplifier operation and precharge operation.However, by increasing the number of input / output bits, data and instructions can be sent to a high-speed processor as long as continuous address access is executed. It is possible to supply.

However, when a general program is executed by a processor, instructions and data are rarely accessed in the order of memory addresses, and the address of memory access changes according to various conditions. FIG. 7 shows an example of a program in which the execution order of instructions is changed by a branch instruction. The example of 770 is a case where the branch instruction 773 exists in the normal instruction 771, and some instructions 772 following the branch instruction are skipped without being executed. Reference numeral 775 in the figure denotes a case of a repetitive processing (Loop). After the normal instruction 776, the instruction from the loop start part 777 to the loop end part 778 is returned, and the instruction following the loop processing part as long as the condition 779 is satisfied. Are sequentially executed. The return condition is usually “until the number of repetitions reaches a specified value”.

Generally, in a program mainly composed of numerical calculations such as signal processing, there is a very high probability that a condition is satisfied by a conditional branch instruction and the program is branched. Furthermore, regarding data access, if the application is close to numerical calculation, it is possible to make the access to some degree in order by creating a program, but every time a branch occurs, the instruction prefetch mechanism takes in advance. The instruction group and the next access already started at that time are canceled, and the access operation of the necessary instruction is started after the DRAM access cycle is completed. FIGS. 9 and 10 show timing charts at this time. FIG. 9 shows the case of executing a simple branch instruction, and FIG. 10 shows the case of executing a loop instruction.

In both figures, reference numerals 950 and 150 denote instruction bus access address unit states, 951 and 151 denote instruction bus instruction fetch output states, 952 and 152 denote instruction fetch control unit storage states, 953 and 1
53 indicates an instruction decode state, and 954 and 154 indicate instruction execution unit states.

In FIG. 9, at the time when the branch instruction 990 is decoded and executed, the fetch 991 of the next instruction has already been performed, and the further preceding instruction access 992 has also been executed. 993 is also taking place. For this reason, instruction cycles etc. corresponding to 991 and 993
The nine cycles shown at 994 are wasted. The correct branch destination is performed in the DRAM accessible cycle 995 after the branch instruction is executed and output on the instruction bus at 996,
At 997, it is stored in the instruction fetch control unit.

Similarly, in the case of the loop processing shown in FIG.
When the loop end instruction indicated by 00 is executed and an attempt is made to start a memory access at the return destination of the loop, an instruction fetch has already been performed.
191 and instruction access 192 have been completed, and instruction access 1101 for the DRAM access at the return address indicated by 1101 can be started. Instruction fetch 193 corresponding to 192 access has been completed. Nine instruction cycles indicated by 194 until the instruction is fetched onto the bus and stored in the instruction fetch control unit in 1103 are wasted.

In order to reduce the dead time associated with such DRAM access and to realize high-speed operation of the processor, conventionally, a larger SRAM or cache memory is used as a processor.
The configuration was sandwiched between DRAMs. An outline of the configuration is shown at 883 in FIG. In this case, the performance degradation due to the branch instruction can be suppressed, but the chip area of the cache portion increases, which leads to a significant increase in chip cost.

[0011]

Accordingly, the present invention provides
An object of the present invention is to provide a processor which can reduce performance degradation even when a branch instruction or loop processing is repeatedly executed without using a high-speed buffer memory element such as a cache in a DRAM embedded processor LSI.

[0012]

According to a first aspect of the present invention, there is provided a processor in which a data input / output signal line bundle and a command input line bundle are separated from each other. Branch instruction code detecting means is provided for each field of the processor, and in the instruction prefetch control portion of the processor, an address counter means for memory access for instruction prefetching, a register means for storing a branch destination address, and outputs of these counter means and register means Memory access means for selecting and receiving one of them as an input and outputting either one of them, further comprising an input terminal for selection, a control input terminal for temporarily stopping the memory access operation, and a control terminal for resuming the memory access And temporarily interrupts the memory access with the logical sum signal of the detection output signal of the detection means. A signal line that is connected to a control input terminal to be executed and that indicates whether a branch instruction is to be executed or not is output when the corresponding branch instruction is executed, is connected to the input terminal for selection, and indicates the end of execution of the branch instruction. An instruction processing apparatus characterized in that a signal is connected to a terminal for resuming the memory access.

A second means for solving the problem is a processor in which a data input / output signal line bundle and a command input line bundle are separated, and the processor has a loop processing start instruction and a loop processing end instruction, and Code detection means for the loop processing start instruction and the loop processing end instruction is provided in each of one or a plurality of fields corresponding to the instruction code, and an instruction prefetch control part of the processor indicates a memory access address for instruction prefetch. A counter means, a register means for storing a loop return destination address, a selective memory access means for receiving and selecting one of the outputs of the counter means and the register means and outputting one of the outputs, and further comprising a selective memory access means for selecting Input terminal,
A control signal terminal for providing loop counter means for counting the number of times of loop processing, and for storing a detection signal when the detection means detects the start of loop processing in the register for storing the return address of the loop and the address of the instruction at that time. At the same time, also connected to a control signal terminal for setting the number of loops in the loop counter means,
When the value of the loop counter means is not zero, a detection signal when the detection means detects the end of the loop processing is propagated to a selection control input of the selective memory access means, and when the value is zero, the detection signal is transmitted to the selection control input. There is provided an instruction processing apparatus characterized by providing a logic means for performing processing not to be propagated.

[0014]

Embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 show the configuration of the first and second embodiments of the present invention, respectively.

In the figures, 101 and 201 are LSI chips, 102 and 202, respectively.
Is the core of the processor, 103 and 203 are mixed DRAM (dynamic random access memory), and 104 and 204 are DRAM
Instruction signal line bundle for supplying instructions to the processor from
A data signal line bundle for inputting and outputting data between the DRAM and the processor (hereinafter, referred to as a data bus); each bus is divided into an address portion and a content portion; Are the instruction access address units 106 and 2
06 and the instruction access output section 10 which is the instruction content section
7 and 207, and the data bus includes data access address sections 108 and 208 and data access input / output sections 109 and 209 of the data content section.

Inside the processor core, there are data processing units (data paths) 111 and 211, and control units (control paths) 110 and 210 for performing various controls. Among the control units, an instruction fetch control unit 112 is provided. , 212, instruction decoding units 113, 21
3. There are control signal generators 114 and 214. The fetch control unit includes an instruction look-ahead counter 11 that generates a continuous address for fetching an instruction to be executed in the future in advance.
5, 215, selective memory access means 116, 216 for selecting the address of this counter and another non-contiguous address and outputting either of them to the memory for accessing the instruction, and a selection signal input terminal for this selection It consists of 117 and 217.

In FIG. 1 showing the configuration of the first embodiment of the present invention, in order to detect a branch instruction immediately after being fetched from a memory, a branch instruction code detecting means 118 is connected to a predetermined field of an instruction access output section of an instruction bus. To be provided.

FIG. 3 shows an installation state of the branch instruction detecting means. In this figure, 330 is the entire instruction code format (16
331, an opcode field (6 bits) therein, 332 a first operand field (5 bits), 33
3 is a second operand field (5 bits). In this example, it is assumed that the branch instruction is an operation code of 1100.
The first operand of the branch instruction is, for example, a condition for branching, and the second operand is an internal register number storing a branch destination address. The first element of the detecting means 118 is constituted by a logic gate 334 which outputs a logic 1 as soon as the pattern of 1100 is inputted from the instruction bus. In the example of FIG. 3, since the instruction access output unit 107 has a bit width of three instructions and outputs the instructions in parallel, three detection means first elements are provided. In the example of FIG. 1, the number is two. The logical sum of the first element output of the branch instruction detecting means is calculated by a logic circuit 335, and the output 336 is used as the output of the detecting means 118.

Generally, the access cycle time of the DRAM is several times the operation cycle time of the processor. Therefore, the instruction bus from the embedded DRAM has a wide bit width, reads a plurality of instructions in parallel, and reduces the cycle time gap. However, it is possible to increase the average throughput and fill the gap.

Further, in the first embodiment of the present invention, the output 336 is transmitted to the selective memory access means 1 as shown in FIG.
Connect to 16 access stop input terminals 121. The selective memory access unit 116 stores an instruction prefetch counter 115 indicating the next consecutive memory address of the instruction address currently being fetched, and stores the address of the branch destination (or stores the address when a future branch instruction is executed). Both outputs of the branch destination address register 119 are set as input addresses, and the address from the address 115 or 119 is selected according to the polarity of the input signal at the selection signal input terminal 117. And an instruction fetch operation is performed. But access stop input terminal
As soon as logic 1 is input to 121, the address output and fetch operation are stopped. In addition, the instruction fetch operation that has been temporarily stopped returns to the normal operation again when the assert signal is input to the access restart control input terminal 120, and the fetch operation is restarted. After the branch instruction is fetched, it is stored in the instruction fetch control unit 112.
After the control signal is generated at 114, the control signal is generated by the branch instruction processing means 122 in the data processing unit 111. If the branch condition is met, a branch occurs, a branch occurrence notification signal 124 is sent from the 122 to the selection signal input terminal 117, and the branch destination address register 119 is selected. Conversely, if the branch condition is not met, it is necessary to fetch instructions at the next consecutive address, and the prefetch address counter is selected.

At the end of the execution of the branch instruction, a branch instruction execution end signal 123 is sent from the branch instruction processing means 122 to the access restart control input terminal 120. FIG. 5 shows an operation state of this embodiment. In the figure, 550 indicates an instruction bus access address section state, 551 indicates an instruction bus instruction fetch output state, 552 indicates an instruction fetch control section storage state, 553 indicates an instruction decode state, and 554 indicates an instruction execution section state.

At 560, when the fetched instruction is still on the instruction bus, the branch instruction code detecting means 118
Since 556 is detected, the code detection means output 336 is input to the access stop terminal 121 of the selective memory access means 116, so that the selective memory access means 116 suspends access until the next access resumption control input comes. ,
It is possible to cancel the address access 555 that was to occur immediately next. Like the normal instruction, the branch instruction 556 is stored in the fetch control unit, decoded, and when executed, it is determined whether or not a branch will occur, and at the time indicated by 557 at an appropriate address based on the condition judgment, To access. As a result, the instruction fetched at 558 is output to the instruction bus. Then, the next correct instruction is stored in the fetch control unit at 559, and then decoded and executed as a normal instruction. The invalid cycle 561 from this branch instruction to the next execution instruction is six in this example.

On the other hand, the second embodiment shown in FIG. 2 has a configuration corresponding to loop processing, and in order to perform a high-efficiency loop processing operation using this configuration, the processor is required to provide a processor other than a normal conditional branch instruction. Add a loop start instruction and a loop end instruction. Reference numeral 225 denotes a loop processing start instruction code and end instruction code detection means provided at the output unit of the instruction bus, and 226 denotes a loop return address register, which stores an address where the loop processing start instruction is present. This is realized by transferring the value of the instruction prefetch counter 215 at that time to the register 226 when the detection means 225 detects the loop instruction start instruction code. FIG. 4 shows a configuration example of the detection means 225. In this case, it is necessary to detect two types of codes, a loop processing start instruction 440 and a loop processing end instruction 441. Therefore, the required number of first detection elements 442 and 443 for each of them are juxtaposed, and the logic circuits 444 and 445 use OR and output each
446 and 447 are two outputs of the detection means 225. 227 is a logic means for controlling the loop processing autonomously, 228 is a loop number counter, and the value of the counter is initially set to 0.
When the loop processing start instruction is executed in the instruction execution stage, the following condition-dependent processing is performed. 1) When the number-of-loops counter 228 is 0: A value obtained by subtracting 1 from the number of repetitions specified by the operand part of the loop processing start instruction 440 is set in the number-of-loops counter 228. 2) When the loop count counter 228 is positive: The loop count counter 228 is decremented, and the value is reduced by one.

Also, when the detecting means 225 detects the loop processing end instruction code 441, the processing according to the following conditions is performed. 1) When the number-of-loops counter 228 is 0: Since the execution of the specified number of times of the loop has been completed, the process proceeds to the execution of the next instruction without branching. That is, the selective memory access means 216 selects the instruction prefetch counter 215 (holding the next incremented value of the currently accessed memory address) and performs the next memory access. 2) When the loop count counter 228 is positive: Further loop repetition processing is necessary, so that the selective memory access means 216 selects the loop return destination address register 226 to access the loop processing start instruction section, and The branch is performed by the memory access, and the value of the loop return destination address 226 is substituted into the instruction prefetch counter 215.

FIG. 6 shows an operation state of this configuration. If there is a loop processing end instruction among the instructions on the bus fetched by the previous access shown at 660, a loop processing end instruction is detected by the loop processing start / end instruction code detecting means 225 at 660, and the loop counter is executed. Depending on the value of, the return address or the next consecutive address is prepared,
Accessed at 662.

In FIG. 6, L.end is a loop processing end instruction, and L.end is
sta indicates a loop processing start instruction. The return address contains a loop processing start instruction, which is fetched at 663, stored in the fetch control unit as shown at 665, coded, and executed. Loop processing end instruction 66
The invalid instruction cycle 661 between 4 and the start instruction 665 is only one cycle.

[0028]

As is clear from the above description, the effect of the present invention is obtained in a processor system using a DRAM as a storage element (particularly when the parallel input / output bit width can be increased).
It is to realize a significant improvement in program execution performance by eliminating useless access to the DRAM when branching of instruction execution order due to a branch instruction or a loop processing instruction occurs frequently. Further, by eliminating useless memory access, power consumption required for that purpose can be reduced, and low power consumption can be realized. In addition, a small amount of hardware such as a simple logic circuit and a counter is required for this purpose, and a very high effect of high performance and low power consumption is exhibited.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a second embodiment of the present invention.

FIG. 3 is a configuration diagram of an instruction code and an instruction bus field in a branch instruction and an instruction code detection unit;

FIG. 4 is a configuration diagram of an instruction code in an instruction to start and end a loop process, a field of an instruction bus, and an instruction code detection unit;

FIG. 5 is a diagram showing an operation state according to the first embodiment;

FIG. 6 is a diagram showing an operation state according to the second embodiment;

FIG. 7 is a diagram showing an execution order of instructions;

FIG. 8 is a diagram of a conventional processor and a memory configuration example.

FIG. 9 is a diagram showing an operation state of branch instruction execution in a conventional method.

FIG. 10 is a diagram showing an operation state of loop instruction execution in a conventional method.

[Explanation of symbols]

101 LSI chip 102 Processor core unit 103 DRAM 104 Instruction bus 105 Data bus 106 Instruction access address unit 107 Instruction access output unit 108 Data access address unit 109 Data access input / output unit 110 Control processing unit 111 Data processing unit 112 Instruction fetch control unit 113 Instruction decode unit 114 Control signal generation unit 115 Instruction prefetch counter 116 Selective memory access means 117 Select signal input terminal 118 Branch instruction code detection means 119 Branch destination address register 120 Access resume control input terminal 121 Access stop input terminal 122 Branch instruction processing means 123 Branch instruction execution end signal 124 Branch occurrence notification signal 150 Instruction bus access address section state 151 Instruction bus instruction fetch output state 152 Instruction fetch control section storage state 153 Instruction decode state 154 Instruction execution section state 191 Fetched on previous access and on bus Invalid instruction at 192 invalid Access to address 193 Invalid instruction on fetched bus 194 Invalid instruction cycle or no execution cycle 201 LSI chip 202 Processor core 203 DRAM 204 Instruction bus 205 Data bus 206 Instruction access address 207 Instruction access output 208 Data Access address section 209 Data access input / output section 210 Control processing section 211 Data processing section 212 Instruction fetch control section 213 Instruction decoding section 214 Control signal generation section 215 Instruction prefetch counter 216 Selective memory access means 217 Selection signal input terminal 225 Loop processing start / End instruction code detecting means 226 loop return destination address register 227 loop processing discriminating logic means 228 loop number counter 307 instruction access output section 330 instruction code example 101 331 opcode field 332 first operand field 333 second operand field 334 first code Output element 335 Second code detection element (OR circuit) 336 Code detection means output 407 Instruction access output unit 430 Instruction code example 101 431 Opcode field 432 101st operand field 433 Second operand field 440 Instruction code example 2 (loop processing) Start instruction) 441 Instruction code example 3 (loop processing end instruction) 442 Loop processing start code detection unit 101st element 443 Loop processing end code detection unit 101st element 444 Loop processing start code detection unit second element (OR circuit) 445 Loop processing end code detection unit second element (OR circuit) 446 Loop processing start code detection unit output 447 Loop processing end code detection unit output 550 Instruction bus access address part state 551 Instruction bus instruction fetch output state 552 Instruction fetch control unit storage Status 553 Instruction decode status 554 Instruction execution status 555 Canceled access 556 Branch instruction 557 Access to branch destination address 558 Fetched branch destination instruction 559 Branch target instruction or re-execution start instruction cycle 560 Instruction fetched on previous access and on bus 561 Invalid instruction cycle or cycle where nothing is executed 650 Instruction bus Access address section state 651 Instruction bus instruction fetch output state 652 Instruction fetch control section storage state 653 Instruction decode state 654 Instruction execution section state 660 Instruction fetched on previous access and on the bus 661 Invalid instruction cycle or cycle where nothing is executed 662 Loop return address 663 Instruction on bus including loop start instruction 664 Loop end instruction 665 Loop start instruction 770 For pure branch 771 Instruction executed (other than branch) 772 Instruction not executed 773 Branch instruction 775 For loop processing 776 Instructions to be executed (loop start / end instructions 777 Loop start instruction 778 Loop end instruction 779 Return condition: (number of repetitions) <(determined number of times) 880 Simple DRAM embedded processor chip 881 CPU part 882 Embedded DRAM 883 Embedded DRAM with cache Processor chip 884 Installed cache part 950 Instruction bus access address part state 951 Instruction bus instruction fetch output state 952 Instruction fetch control part storage state 953 Instruction decode state 954 Instruction execution part state 990 Branch instruction 991 Accessed before the branch instruction 991 and fetched on the bus Invalid instruction at 992 Invalid address access 993 Invalid instruction on fetched bus 994 Invalid instruction cycle or no-execution cycle 995 Access to branch target address 996 Instruction fetched branch target instruction on instruction bus 997 Branch target instruction Is stored in the instruction fetch control unit. Launch instruction 1101 Access to branch destination address 1102 Fetched loop return destination instruction 1103 Return destination instruction cycle

Claims (2)

[Claims] 1. An instruction prefetch counter, a branch destination address storage means, a selection means for selecting a value of the instruction prefetch counter and a value of the branch destination address storage means and outputting the selected value as an address signal, Connected branch instruction detecting means, wherein when the branch instruction detecting means detects a branch instruction, reading of the instruction is stopped, and when the branch instruction is executed, reading of the instruction is restarted. Processing equipment. 2. A loop processing start instruction detecting means having a loop processing start instruction and a loop processing end instruction and connected to an instruction input signal and detecting the loop processing start instruction;
A loop processing end instruction detecting means connected to the instruction input signal for detecting the loop processing end instruction, an instruction prefetch counter, a branch destination address storage means, a value of the instruction prefetch counter and the branch destination address storage means Selecting means for selecting the value of
A counter for counting the number of loops, and when the loop processing end command is detected by the loop processing end command detection means, when the counter indicates that the loop is not ended, the selection means Output the value of the branch destination address storage means.