JP2000299437A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a resistance element in a narrower area without increase in the number of processes, in a DRAM process. SOLUTION: A word line 13a is formed on a memory region 10a of a substrate 10, and a connection conductive layer (conductive layer) 13b is formed in a peripheral region 10b. After a diffusion layer 14 is formed on the surface side of the substrate 10 in the memory region 10, an interlayer insulating film layer (insulating film) 15 is formed to cover this. A contact hole 19, which reaches the diffusion layer 14 and the connection conductive layer (conductive layer) 13b, is formed at the interlayer insulating film layer 15, in which a conductive material 20 is embedded. Thus, a bit contact of the conductive material 20 is formed in the memory region 10a, and a resistance element of the conductive material 20 is formed in the peripheral region 10b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a resistor element provided on the same substrate as a memory cell or a logic circuit.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view of an essential part showing an example of a semiconductor device. The semiconductor device shown in FIG.
, A memory cell 2, a logic circuit 3 and the like are provided on the front side. In this semiconductor device, a word line 4 and a bit line 5 of the memory cell 2 and a gate line 6 and a line 7 connected to a diffusion layer in the peripheral circuit 3 are provided with a polycide layer composed of a polysilicon layer and a silicide layer thereover. Wiring is used. The memory cell 2 has a cylindrical capacitor 8 above the bit line 5, and the upper electrode 9 of the capacitor 8 is made of polysilicon.

In the semiconductor device having such a structure, when a resistance element is provided on the substrate 1, the resistance element made of polycide is formed in the same step as the word line 4 and the bit line 5, or the upper part of the capacitor 8 is formed. A resistive element made of polysilicon is formed in the same step as the electrode 9.

[0004]

However, the semiconductor device provided with the above-described resistance element has the following problems. That is, when a resistance element made of polycide is formed in the same step as a word line or a bit line, it is necessary to increase the wiring length in order to increase the resistance of the resistance element. For this reason, the area occupied by the resistive element increases, which is a factor for increasing the chip area.

Therefore, by using only the polysilicon layer constituting the lower layer of polycide as a resistance element,
Although it is conceivable to increase the resistance of the resistance element, in this case, it is necessary to selectively form a silicide layer only on the polysilicon layer portion to be polycide. For this reason,
A mask process must be added to form a resistance element.

Further, even if a resistive element made of polysilicon is formed in the same step as the upper electrode of the capacitor, since the polysilicon has a low resistance, a wiring length is required to obtain a high-resistance resistive element. Need to be longer. Therefore, similarly to the case where polycide is used as a resistance element, there is a problem that the area occupied by the resistance element increases and the chip area increases.

Therefore, the present invention provides a semiconductor device and a semiconductor device in which a resistive element can be arranged on the same substrate as other elements without adding a special step, and a chip area can be reduced. It is an object of the present invention to provide a manufacturing method thereof.

[0008]

According to the present invention, there is provided a semiconductor device having a resistive element in which a conductive material is embedded in a contact hole formed in an insulating film on a substrate. It is characterized by that. A DRAM (Dynami) comprising a capacitor above the insulating film
c Random Access read / write memory) When a cell is provided on the substrate, the resistance element
It is assumed that it is provided in the same layer as the bit contact of the M cell. Further, the resistance element may be connected in series by a conductive layer below the insulating film.

In the semiconductor device having such a configuration, since the resistive element is arranged upright on the substrate, the area of the resistive element occupying the substrate is reduced. Moreover, this resistance element is formed in the same step as the contact of another element formed on the substrate. When the resistance element is provided in the same layer as the bit contact of the DRAM cell, the resistance element is formed in the same step as the bit contact without adding a special step for forming the resistance element. . Further, the resistance value of the resistance element is increased by connecting the resistance element in series with the conductive layer below the insulating film.

The method of manufacturing a semiconductor device according to the present invention includes the steps of: covering a substrate on which a conductive layer is formed on a front surface side with an insulating film, forming a contact hole in the insulating film reaching the conductive layer; Embedding a conductive material in the contact hole to form a resistor element made of the conductive material.

In this manufacturing method, since the resistance element is formed by embedding a conductive material in the contact hole, the other element formed on the substrate can be formed without adding a special process for forming the resistance element. A resistive element is obtained in the same step as the contact of the element.

When forming a contact hole forming a resistance element, a mask layer is formed on the insulating film, a hole is formed in the mask layer, and a sidewall is formed on a side wall of the hole. Next, the insulating film on the bottom surface of the hole may be etched using the sidewall and the mask layer as a mask until the insulating film reaches the conductive layer.

By doing so, the diameter of the contact hole is reduced in a self-aligned manner, so that the cross-sectional area of the resistance element embedded therein is reduced, and the resistance of the resistance element is increased.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments to which the semiconductor device of the present invention and its manufacturing method are applied will be described below with reference to the drawings. Here, first, a method of manufacturing a semiconductor device in which the present invention is applied to a DRAM in LOGIC process will be described, and then a configuration of a semiconductor device of the present invention obtained thereby will be described.

(First Embodiment) As shown in FIG. 1A, a substrate 10 made of silicon has a memory region 10a and a peripheral region 10b on the surface side. And
By the following steps, DRAM cells are formed in the memory region 10a, and a logic circuit having a resistance element is formed in the peripheral region 10b. Here, the formation part of the DRAM cell and the resistance element is illustrated.

First, an element isolation region 11 and a gate oxide film 12 are formed on the front side of a substrate 10. Next, the substrate 10
A word line 13a having a polycide structure (for example, a film thickness of 200 nm) is formed on the memory region 10a in FIG. This polycide structure is assumed to be composed of, for example, a polysilicon layer and a tungsten layer thereover. In the same step as the formation of the word line 13a, a connection conductive layer 13b having a polycide structure (that is, a conductive layer described in claims) is formed on the element isolation region 11 in the peripheral region 10b of the substrate 10.

Next, an impurity for forming the diffusion layer 14 is introduced into the surface layer of the substrate 10 by ion implantation using the word line 13a as a mask. Next, the word line 13a
After forming an interlayer insulating film layer 15 (that is, an insulating film described in claims) on the substrate 10 in a state of covering the connection conductive layer 13b, a mask layer 16 is formed on the interlayer insulating film layer 15. This mask layer 16 is made of, for example, 0.58% by weight of phosphorus.
It is made of contained amorphous silicon (phosphorus-doped amorphous silicon: hereinafter, referred to as PDAS).

[0018] Next, here using a resist pattern (not shown) to the mask to etch the mask layer 16 and the interlayer insulating film layer 15, the opening diameter W ₁ to form a hole 17 of about 0.28 .mu.m. At this time, the bottom of the hole 17 is
The interlayer insulating film layer 15 is left with a thickness of about 0 nm. This hole 1
Numeral 7 is provided at the formation position of the node contact and bit contact of the DRAM cell in the memory region 10a, and at the contact formation position of the other element not shown here on the connection conductive layer 13b in the peripheral region 10b. Provided. Note that two holes 17 are formed on each connection conductive layer 13b.

After that, the resist pattern used for forming the holes 17 is removed, PDAS is formed again, and this is etched back, so that the sidewalls 18 made of PSAS are formed on the inner walls of the holes 17. This gives W ₁ =
The opening diameter of the hole 17 which was about 0.28 μm was changed to W ₂ =
Reduce to about 0.12 μm.

Thereafter, the interlayer insulating film layer 15 exposed at the bottom of the hole 17 is removed by etching using the mask layer 16 and the side wall 18 as a mask, and a contact hole 19 reaching the diffusion layer 12 is formed in the memory region 10a. Then, a contact hole 19 reaching the connection conductive layer 13b is formed in the peripheral region 10b.

Next, as shown in FIG. 1 (2), a film thickness (for example, 3
(00 nm), a conductive material 23 is formed above the substrate 10. As a result, the inside of the contact hole 19 is filled with the conductive material 20.

As the conductive material 13b, for example,
Semiconductor materials such as amorphous silicon to which impurities are added such as PDAS, polysilicon to which impurities are added, and metals such as aluminum, copper, tungsten, titanium, and cobalt, and alloys of these metals are used. it can.

Thereafter, as shown in FIG. 2A, while the conductive material 20 is left only in the contact hole 19,
The conductive material 20 and the mask layer (16) are etched back, and the interlayer insulating film layer 15 is planarized by CMP (chemical mechanical polishing). Thereby, the bit contact 21 and the node contact 22 made of the conductive material 20 are formed in the memory region 10a,
Resistive element 23 made of conductive material 20 in peripheral region 10b
To form These resistance elements 23 are connected to the connection conductive layer 13.
By b, two are connected in series. Here, in the case where PDAS (containing 0.58% by weight of phosphorus) is used as the conductive material 20, the resistance element 2
No. 3 has a resistance value of about 1 to 3 kΩ.

Next, as shown in FIG. 2B, the bit contact 21, the node contact 22 and the resistor 23
The insulating film 24 is formed on the interlayer insulating film layer 15 in a state of covering the insulating film 24. This insulating film 24 is formed of, for example, L having a thickness of about 80 nm.
P-TEOS film, that is, TEOS (tetraethoxy sila)
ne) LP-CVD (low pressure-chemica) using gas
(l) A silicon oxide film formed by a vapor deposition method. Thereafter, a contact hole 25 is opened in the insulating film 24 above the bit contact 21 and each resistance element 23.

Next, a tungsten polycide (for example, a film thickness of 120 nm) is formed on the insulating film 24 in the memory region 10a.
Is formed. This bit line 26
“a” is connected to the bit contact 21. The electrode 26 made of tungsten polycide is formed on the insulating film 24 in the peripheral region 10b in the same process as the formation of the bit line 26a.
b is formed. At this time, if necessary, the connection conductive layer 13
The electrode 26b is formed in a state where the resistance elements 23 not connected by b are connected. Thereby, this electrode 2
A total of four resistive elements 23 are connected in series, including two resistive elements 23 connected by 6b, and two further resistive elements 23 connected by these resistive elements 23 and the connection conductive layer 13b.

After the above, the bit line 26a and the electrode 26b
Is formed on the insulating film 24 so as to cover the insulating film 24.

Then, as shown in FIG. 3, after the surface of the interlayer insulating film layer 27 is planarized by the CMP method, a silicon nitride film 28 is formed on the interlayer insulating film layer 27 as an etching stopper layer. Next, the silicon nitride film 28,
A contact 29 connected to the node contact 22 is formed in the interlayer insulating film layer 27 and the insulating film 24, and the node contact 22 extends upward.

Thereafter, a barrel-type lower electrode 31 is formed in a state of being connected to the contact 29, and is covered with a dielectric film 32.
Form 3 Thus, a barrel-type capacitor 34 including the lower electrode 31, the dielectric film 32 and the upper electrode 33 is formed in the memory region 10a, and the DRAM cell 35 having the capacitor 34 is obtained. The lower electrode 31 and the upper electrode 33 are made of polysilicon.

Next, an interlayer insulating film layer 36 is formed above the substrate 10 so as to cover the capacitor 34, and the surface thereof is flattened. Then, the contact hole 3 connected to the upper electrode 33 of the capacitor 34 is formed in the interlayer insulating film layer 36.
7a, and an electrode 26b of the resistance element 23 is formed on the interlayer insulating film layer 36 and the interlayer insulating film layer 27 thereunder.
Contact hole 37b is formed. Next, after the inner walls of the contact holes 37a and 37b are covered with a barrier metal 38, these contact holes 37a and 37b are covered.
Plugs 39 are formed by burying, for example, tungsten in the insides a and 37b.

Thereafter, the plug 3 is formed on the interlayer insulating film layer 36.
An aluminum electrode 40 connected to the substrate 9 is formed, and a semiconductor device is obtained as described above.

In the semiconductor device thus obtained,
Since the resistance element 23 is formed in the same step as the bit contact 21 of the DRAM cell 35, no special step for forming the resistance element 23 is added. In addition, since the resistance element 23 has a contact shape formed in the interlayer insulating film layer and is arranged upright on the substrate 10, the occupied area is small. For this reason, the chip area can be reduced, the chip yield on one substrate (wafer) can be increased, and the cost per chip can be reduced.

Further, as described with reference to FIG. 1A, when forming the contact hole 19 which becomes the outer shape of the bit contact 21 and the resistance element 23, the side wall 18 is formed on the side wall of the hole 17. Thereafter, the bottom surface of the hole 17 is etched using the sidewall 18 as a mask, whereby the contact hole 19 in which the diameter of the hole 17 is reduced in a self-aligned manner is obtained. For this reason, it is possible to obtain a contact hole 19 having a diameter smaller than the limit of lithography, and it is possible to reduce the cross-sectional area of the resistance element 23 formed therein to increase the resistance.

Further, since the resistance elements 23 are connected in series by the connection conductive layer 13b under the interlayer insulating film layer 15, these resistance elements 23 are further connected in series by the wiring of the electrode 26b. It is possible to obtain a desired resistance value. Moreover, the connection conductive layer 13b
Since it has a polycide configuration, it has low bias dependence and thermal dependence and can obtain a stable resistance value.

Since the electrode 26b of the resistance element 23 has a polycide structure, an ohmic contact between the electrode 26b and the plug 39 made of metal can be achieved. For this reason, although not shown here, a metal contact (Buried Met) connected to a diffusion layer formed on the surface layer of the substrate 10 is formed in the peripheral region 10b of the semiconductor device.
When an alon diffusion (hereinafter referred to as BMD) is provided, the plug 39 to be connected to the electrode 26b can be formed in the same step as the plug for making an ohmic contact to and connecting to the BMD. In this case, since the upper electrode 33 of the capacitor 34 is made of polysilicon, an ohmic contact with the plug 39 cannot be made, but there is no problem in the capacitor 34.

(Second Embodiment) FIG. 4 is a sectional view of a main part for explaining another embodiment of the present invention. The difference between the semiconductor device shown in this figure and the semiconductor device described with reference to FIG. 3 lies in the configuration of a connection conductive layer 45 for connecting the resistance element 23. That is, in the semiconductor device shown in this figure, the connection conductive layer 45 is constituted by the diffusion layer provided on the surface layer of the substrate 10. The connection conductive layer 45 composed of the diffusion layer is formed in the diffusion layer 14 of the memory region 10a.
And is formed in the same step. Each connection conductive layer 45 is isolated by the element isolation region 11.

Even with such a semiconductor device, the same effects as those of the semiconductor device of the first embodiment can be obtained.

[0037]

As described above, according to the semiconductor device of the first aspect of the present invention, by providing the resistance element in which the conductive material is buried in the contact hole formed in the insulating film, other elements can be provided. The resistance element can be formed in the same step as the element contact formation, and the resistance element is erected on the substrate, so that the area of the resistance element occupying on the substrate can be reduced. Therefore, the area of a semiconductor device having a resistive element can be reduced without adding a special step.

Further, according to the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, since the resistance element is formed by burying a conductive material in the contact hole, it is formed on the substrate. A resistive element can be obtained in the same step as the contact of another element. For this reason, it is possible to obtain a resistive element standing on the substrate without adding a special process for forming the resistive element.

[Brief description of the drawings]

FIG. 1 is a sectional process view (part 1) of a main part for describing an embodiment of the present invention.

FIG. 2 is a sectional view (part 2) of a main part for describing the embodiment of the present invention.

FIG. 3 is a sectional process view (part 3) of a main part for describing an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a main part for describing another embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor device in which a DRAM cell and a logic circuit are provided on the same substrate.

[Explanation of symbols]

10 ... substrate, 13b, 45 ... connection conductive layer (conductive layer), 1
5 ... interlayer insulating film layer (insulating film), 16 ... mask layer, 17 ...
Hole, 18 ... sidewall, 19 ... contact hole,
Reference numeral 20: conductive material, 21: bit contact, 23: resistance element, 35: DRAM cell

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (6)

[Claims] 1. A semiconductor device, comprising: a resistance element in which a conductive material is embedded in a contact hole formed in an insulating film on a substrate. 2. The semiconductor device according to claim 1, wherein a DRAM cell including a capacitor is provided above the insulating film on the substrate, and the resistance element is the same as a bit contact of the memory cell. A semiconductor device, which is provided in one layer. 3. The semiconductor device according to claim 1, wherein the resistance elements are connected in series by a conductive layer below the insulating film. 4. The semiconductor device according to claim 2, wherein said resistance elements are connected in series by a conductive layer below said insulating film. 5. A step of covering a substrate on which a conductive layer is formed on a front surface side with an insulating film, forming a contact hole reaching the conductive layer in the insulating film, filling a conductive material in the contact hole, Forming a resistive element made of the conductive material. 6. The method of manufacturing a semiconductor device according to claim 5, wherein when forming the contact hole, a mask layer is formed on the insulating film, and a hole is formed in the mask layer.
Forming a sidewall on a side wall of the hole, and then etching the insulating film on the bottom surface of the hole using the sidewall and the mask layer as a mask until the insulating film reaches the conductive layer. Production method.