JP2000299436A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device where a logic circuit and a storage circuit coexist, wherein in a power-on sequence, a gate control or internal node initialization is performed at a prestage of the storage circuit to prevent entrance of uncertain signal into the storage circuit. SOLUTION: A logic coexisting DRAM/LSI comprises a logic region 1, containing a logic circuit and a DRAM macro region 2 containing DRAM. The DRAM macro region 2 comprises an input latch circuit 21, which latches the output signal from an output latch circuit 12 of the logic region 1, a gate control circuit 22 comprising 2-input NOR gate, where that output signal is logically calculated with a reset signal for gate control, and then the output signal of fixed level is outputted, and a DRAM logic 23 which is controlled by a memory signal comprising the output signal, etc., and the input signal which is inputted in the DRAM logic 23 is set to a fixed level by the gate control circuit 22 during a power-source voltage step-up period at power on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a circuit technology of a semiconductor device, and more particularly to a technology effective when applied to a semiconductor device in which a logic circuit and a storage circuit are mounted together.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventors, in a so-called logic-mixed memory LSI in which a logic circuit and a storage circuit are mixed, an output latch circuit and an input latch circuit are provided between the logic circuit and the storage circuit. Is connected, an output signal from the logic circuit is latched by an output latch circuit, and the latched output signal is latched by an input latch circuit to be used as an input of a storage circuit.

Incidentally, such a logic embedded memory LS
The technology relating to I is, for example, February 9, 1998.
Nikkei Electronics "Nikkei Electronics" P10
3 to P150.

[0004]

The inventors of the present invention have studied the technology of the above-described logic embedded memory LSI, and as a result, the following has been found.
That is, in the power-on sequence of the logic embedded memory LSI, in a rising transient state of the power supply voltage from OV to VDD, an indefinite signal is injected from the output latch circuit of the logic circuit to the input latch circuit of the storage circuit, and latch-up occurs. And other problems.

[0005] In a general memory LSI,
Although there is a similar power-on sequence, there is no input of an indeterminate input signal such as in a logic-embedded memory LSI, so that the above-described problem does not occur. However, in a configuration in which a logic circuit and a storage circuit are mixed, the output signal becomes uncertain through the logic circuit, and a countermeasure against the above problem is required.

Accordingly, an object of the present invention is to focus on injecting an undefined signal in a power-on sequence in an LSI in which a logic circuit and a storage circuit are mixed, and perform gate control or internal node initialization in a preceding stage of the storage circuit. Another object of the present invention is to provide a semiconductor device capable of preventing input of an indefinite signal to a memory circuit.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor device according to the present invention comprises: an output latch circuit for latching an output signal from a logic circuit;
An output signal from the output latch circuit is input, and an input latch circuit for latching the input signal is logically operated on an output signal from the input latch circuit and a reset signal input to the logic circuit to perform gate control. And a gate control circuit for outputting a fixed level output signal to the storage circuit.

In this way, during the power supply voltage boosting period in which the reset signal at the time of power-on is input, the gate control is performed in the preceding stage of the storage circuit by the reset signal, and the input signal input to the storage circuit by the gate control is fixed. Thus, the input of the indefinite signal to the storage circuit can be prevented.

Another semiconductor device according to the present invention comprises an output latch circuit for latching an output signal from a logic circuit;
An output signal from the output latch circuit is input, the input signal is latched, a logical operation is performed on the latched input signal and a reset signal input to the logic circuit, internal node initialization is performed, and a fixed level And an input latch circuit that outputs an output signal to the storage circuit.

Thus, during the power supply voltage boosting period in which the reset signal at the time of power-on is input, the internal signal is initialized at the previous stage of the storage circuit by the reset signal, and the input input to the storage circuit by the internal node initialization is performed. The signal can be set to a fixed level to prevent input of an indefinite signal to the memory circuit.

In the semiconductor device, the reset signal may be input from outside the semiconductor device, or may be generated inside the semiconductor device.
This is applied to a storage circuit such as an AM.

Therefore, according to the semiconductor device, since gate control or internal node initialization is performed in the previous stage of the storage circuit, the signal level in the next and subsequent stages is fixed. And other problems can be prevented. As a result, reliability is improved, and a semiconductor device technology in which a logic circuit and a storage circuit are mixed can be established.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

(First Embodiment) FIG. 1 is a schematic functional configuration diagram showing a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing an input latch circuit in the semiconductor device according to the first embodiment. FIG. 3 is an explanatory diagram showing signal states at power-on.

First, an example of a schematic configuration of the semiconductor device of the first embodiment will be described with reference to FIG.

The semiconductor device according to the first embodiment is, for example, a logic-loaded DRAM in which a logic circuit and a DRAM are loaded.
A logic area 1 which is an LSI and includes a logic circuit;
A DRAM macro area 2 including a RAM is formed on one semiconductor chip by a known semiconductor manufacturing technique.

The logic area 1 receives an external input signal including a reset signal as input, performs a logic operation on the input signal and outputs the logic signal, and an output signal from the logic logic 11 as an input. An output latch circuit 12 for latching this input signal and outputting it to the DRAM macro area 2, an input latch circuit 13 receiving an output signal from the DRAM macro area 2 and latching this input signal,
An output stage logic logic 14 or the like which receives an output signal from the input latch circuit 13 as an input, performs a logical operation on the input signal, and outputs the result as an external output signal is provided.

The DRAM macro area 2 receives an output signal from the output latch circuit 12 in the logic area 1 and latches the input signal. An output signal from the input latch circuit 21 and a logic logic A gate control circuit 22 comprising a two-input NOR gate which receives a reset signal input to the input terminal 11 as an input, performs a logical operation on the input signal and the reset signal, performs a gate control, and outputs a fixed-level output signal; An output signal from the gate control circuit 22 is input, a DRAM logic 23 controlled by a memory signal including the input signal is input, and an output signal from the DRAM logic 23 is input. And an output latch circuit 24 for outputting to the input latch circuit 13.

As shown in FIG. 2, the input latch circuit 21 in the DRAM macro area 2 has two PMOS transistors TP1 and TP2 and two NMOS transistors connected between a power supply voltage and a ground voltage at an input stage. TN1, TN2 and PMOS connected to this output
Transistor TP3 and NMOS transistor TN3
And two inverters IV1, IV1 connected between both ends.
IV2, an inverter IV3 connected to the output stage, and two inverters IV4 and IV for generating a gate control signal.
5, the input signal IN is input to the gates of the PMOS transistor TP1 and the NMOS transistor TN1, and the PMOS transistor TP3 and the NMO
The signal is latched by the path of the S transistor TN3 and the inverters IV1 and IV2, and output as the output signal OUT from the inverter IV3.

In the input latch circuit 21, the clock signal CLK is input to the inverter IV5 via the inverter IV4, and the gate control signal CL is output as the output.
KT is generated, and an inverted gate control signal CLKB is generated from the connection node. Gate control signal CLKT
Is input to the gates of the PMOS transistor TP2 and the NMOS transistor TN3. Gate control signal CLK
B is input to the gates of the NMOS transistor TN2 and the PMOS transistor TP3. Note that other DRAMs
The output latch circuit 24 in the macro area 2, the output latch circuit 12 and the input latch circuit 13 in the logic area 1 have the same configuration.

Logic mixed DR configured as described above
In the AM / LSI, a reset signal supplied from outside the chip includes a logic logic 11 in the logic area 1, a gate control circuit 22 in the DRAM macro area 2, and a DRAM.
The data is supplied to a desired circuit such as the logic 23, and is used for initializing the flip-flop circuit and for setting data set depending on whether various fuses are cut or not. For example, this reset signal is controlled to a high level during a power supply voltage boosting period at power-on, and becomes a low level when the power supply voltage is stabilized.

Next, regarding the operation of the first embodiment, a signal state at the time of power-on of the DRAM / LSI with embedded logic will be described with reference to FIG. Here, paying attention to the input section of the DRAM macro area 2 where the input signal level is a problem, the output signal of the logic logic 11 is output from the output latch circuit 12.
, The input latch circuit 21 of the DRAM macro area 2,
A signal path passed to the DRAM logic 23 via the gate control circuit 22 will be described.

When the logic embedded DRAM / LSI is powered on, an input signal level that is more undefined than the logic logic 11 is output to the DRAM macro area 2 through the output latch circuit 12.
Is propagated to That is, the signal at the output node A of the output latch circuit 12 is an undefined signal whose signal level is not fixed due to noise or the like. If the undefined signal is directly input to the DRAM logic 23 in the DRAM macro area 2 as in the related art, there is a problem that a problem such as latch-up occurs in the DRAM logic 23.

However, as in the first embodiment, the DR
By providing the gate control circuit 22 at a stage subsequent to the input latch circuit 21 in the AM macro area 2, an indefinite input signal propagated from the logic area 1 is first input to the input latch circuit 21.
And outputs it as one input signal of the two-input NOR gate of the gate control circuit 22.

Thereafter, the NOR gate of the gate control circuit 22 performs a NOR operation on the output signal from the input latch circuit 21 as one input and the reset signal input to the logic logic 11 as the other input. Output a fixed level output signal. That is, the gate control circuit 2
The signal at the output node B of No. 2 is an output signal fixed at a low level while the reset signal is at a high level (power supply voltage boosting period in a transient state where the power supply voltage rises from 0 V to VDD).

The NOR gate of the gate control circuit 22 includes a PMOS transistor and an NMOS transistor whose gates are controlled by a reset signal (not shown).
A PMOS transistor and an NMOS transistor gate-controlled by an input signal.
It has a general configuration in which S transistors are connected in series, and two NMOS transistors are connected in parallel with the S transistors. Therefore, while the reset signal is at the high level, the PMOS transistor controlled by the reset signal is cut off, and the NMOS transistor is turned on and pulled to 0 V. Therefore, even if the input signal is uncertain, the gate control circuit 22 Works stably.

When the power supply voltage rises to VDD and stabilizes after the power supply voltage boosting period, the signal at the output node A of the output latch circuit 12 becomes a fixed level. At this time, the reset signal shifts from the high level to the low level, and accordingly, the signal at the output node B of the gate control circuit 22 becomes an output signal fixed at the high level.

Therefore, the logic mixed D of the first embodiment
According to the RAM / LSI, an undefined input signal level (node A) is input to the input latch circuit 21 during the power supply voltage boosting period at power-on.
In the gate control circuit 22 at the subsequent stage, the output is fixed to the low level (node B) by the reset signal, and therefore, the undefined input signal level is not propagated to the DRAM logic 23 as it is. Therefore, the DRAM logic 23
Since problems such as latch-up in the inside can be prevented, the reliability of the product can be improved.

Second Embodiment FIG. 4 is a schematic functional configuration diagram showing a semiconductor device according to a second embodiment of the present invention, and FIG. 5 is a circuit diagram showing an input latch circuit in the semiconductor device according to the second embodiment. It is.

The semiconductor device according to the second embodiment is a logic-loaded DRAM / LSI in which a logic circuit and a DRAM are mounted in the same manner as in the first embodiment, and includes a logic region 1 including a logic circuit and a DRAM. DRAM macro area 2
The difference from the first embodiment is that the DRAM
The input latch circuit 21a in the macro area 2 includes an internal node initialization function instead of the gate control function, and does not require a gate control circuit.

That is, the DRA according to the second embodiment
As shown in FIG. 4, the M macro area 2 receives an output signal from the output latch circuit 12 of the logic area 1 as an input, latches the input signal, and outputs the latched input signal to the logic logic 11. An input latch circuit 21a that performs a logical operation on an input reset signal and initializes an internal node to output a fixed level output signal, and the first embodiment is connected to a stage subsequent to the input latch circuit 21a. DRAM logic 23 and output latch circuit 24 similar to
And so on.

The input latch circuit 21a in the DRAM macro area 2 includes an inverter IV11 in an input stage and a PMO connected to the output, as shown in FIG.
S transistor TP11 and NMOS transistor T
N11 and inverters IV12-IV14, PMOS transistor TP12 and NMOS transistors TN12, N connected to this output to form a latch path.
It is composed of OR gates NOR11 and NOR12, inverters IV15 and IV16 for generating gate control signals, etc., and an input signal IN is input to the inverter IV11.
A NOR operation is performed on the reset signal and the reset signal in the latch path, and the result is output as an output signal OUT from the inverter IV14.

In the input latch circuit 21a, the clock signal CLK is input and the inverters IV15 and I5
The gate control signal CLKT generated through V16 is
The gate control signal CL is input to the gates of the PMOS transistor TP11 and the NMOS transistor TN12.
KB is input to the gates of the NMOS transistor TN11 and the PMOS transistor TP12, respectively.

Logic embedded DR configured as described above
In the AM / LSI, in the input latch circuit 21a of the DRAM macro area 2, the indeterminate input signal propagated from the logic area 1 and the reset signal input to the logic logic 11 are converted into NOR gates NOR11 and NOR11.
R12 performs a NOR operation, initializes internal nodes after the NOR gate NOR11, and can output a fixed-level output signal. Therefore, the signal of the output node B is the same as in the first embodiment (FIG. 3). Is an output signal fixed at a low level during the power supply voltage boosting period.

Therefore, the logic embedded D according to the second embodiment
According to the RAM / LSI, an undefined input signal level (node A) is input to the input latch circuit 21a during the power supply voltage boosting period at power-on.
In 1a, there is no node that becomes floating due to the reset signal, and the output is fixed at a low level (node B), so that the DRAM logic 23 has an undefined input signal level as in the first embodiment. Is not propagated as it is. Therefore, DRAM logic 2
Since problems such as latch-up in 3 can be prevented,
Further, the reliability of the product can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, the case where the reset signal is inputted from the outside has been described. However, the reset signal can be generated by an internal circuit in the logic area. During the power supply voltage boosting period, the reset signal generated by the internal circuit causes D
The signal level input to the RAM logic can be fixed.

As for the latch circuit, FIG.
The configuration is not limited to the configuration shown in FIG. 5, and various configurations having the same function can be adopted.

Further, the present invention provides a logic embedded DRAM.
-It is effective for LSIs and the like, but can be applied to all multi-function mixed chip products in which logic circuits and storage circuits are mixed.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By providing a gate control circuit that performs a logical operation on an input signal and a reset signal and performs a gate control to output a fixed-level output signal, the power supply voltage boosting period at power-on is reset. The gate control is performed in the preceding stage of the storage circuit by the signal, and the input signal input to the storage circuit can be set to a fixed level by the gate control. Therefore, it is possible to prevent the input of an undefined signal to the storage circuit.

(2) By providing an input latch circuit that performs a logical operation of an input signal and a reset signal, initializes an internal node and outputs a fixed-level output signal, the power supply voltage boosting period at power-on is reduced. , The internal signal is initialized at the preceding stage of the memory circuit by the reset signal, and the input signal input to the memory circuit can be set to a fixed level by the internal node initialization, thereby preventing the input of an undefined signal to the memory circuit. It becomes possible.

(3) According to the above (1) and (2), since gate control or internal node initialization is performed in the preceding stage of the memory circuit, the signal level in the succeeding stages is fixed. Since defects such as latch-up of the memory circuit can be prevented, reliability is improved, and a semiconductor device technology in which a logic circuit and a memory circuit are mixed can be established.

[Brief description of the drawings]

FIG. 1 is a schematic functional configuration diagram showing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating an input latch circuit.

FIG. 3 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 4 is an explanatory diagram showing a signal state at power-on.

FIG. 4 is a schematic functional configuration diagram showing a semiconductor device according to a second embodiment of the present invention;

FIG. 5 shows a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an input latch circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Logic area 2 DRAM macro area 11 Logic logic 12 Output latch circuit 13 Input latch circuit 14 Logic logic 21, 21a Input latch circuit 22 Gate control circuit 23 DRAM logic 24 Output latch circuit TP1-TP3, TP11-TP12 PMOS transistors TN1-TN3 , TN11 to TN12 NMOS transistors IV1 to IV5, IV11 to IV16 Inverter NOR11, NOR12 NOR gate

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 17/22 H01L 27/04 U 19/0175 H03K 19/00 101K (72) Inventor Yuji Yokoyama Ome, Tokyo 6-16-16 Shinmachi, Shichi-shi In the Device Development Center, Hitachi, Ltd. (72) Inventor Michiaki Nakayama 3-16-16 Shinmachi, Shinmachi, Ome-shi, Tokyo In the Device Development Center, Hitachi, Ltd. (72) Masahiro Katayama Tokyo 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems, Ltd. (reference) 5B024 AA03 BA29 CA07 5F038 BG03 BH18 DF01 DF05 DF11 EZ20 5F083 AD00 GA23 ZA12 ZA30 5J055 AX21 BX41 CX27 DX01 EY21 EZ07 EZ12 EZ25 EZ31 GX01 GX02 GX04 5J056 AA01 BB21 CC00 CC14 DD13 DD28 FF01 FF08

Claims (5)

[Claims] 1. A semiconductor device in which a logic circuit and a storage circuit are mixed, an output latch circuit for latching an output signal from the logic circuit, an output signal from the output latch circuit being input, and an input signal And a gate for performing a logical operation on an output signal from the input latch circuit and a reset signal input to the logic circuit, performing gate control, and outputting a fixed-level output signal to the storage circuit. And a control circuit, wherein an input signal input to the storage circuit is set to a fixed level during a power supply voltage boosting period when the reset signal is input at power-on. 2. A semiconductor device in which a logic circuit and a storage circuit are mixed, an output latch circuit for latching an output signal from the logic circuit, an output signal from the output latch circuit being input, and an input signal And an input latch circuit that performs a logical operation on the latched input signal and a reset signal input to the logic circuit, initializes an internal node, and outputs a fixed-level output signal to the storage circuit. A semiconductor device having an input signal input to the storage circuit at a fixed level during a power supply voltage boosting period in which the reset signal is input at power-on. 3. The semiconductor device according to claim 1, wherein the reset signal is input from outside the semiconductor device. 4. The semiconductor device according to claim 1, wherein said reset signal is generated inside said semiconductor device. 5. The semiconductor device according to claim 1, wherein the storage circuit is a DRAM.