JP2000299271A - Exposure method and aligner - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an exposure method and an aligner, where pilot exposure can be dispensed with. SOLUTION: An exposure method, where a circuit pattern on a mask is transferred on a semiconductor substrate through a surface image forming technique comprises a process 103 where the mask and the semiconductor substrate are aligned with each other, a process 104 where only a test pattern formed on the mask is exposed, a process 105 where the latent image of an exposed pattern is measured with an optical microscope and an atomic force microscope provided to an exposure system, a process 106 where a measured value or an induced value is compared with a prescribed value, a process 108 where an exposure process is carried out when the measured value is within the range of a prescribed value, a process 107 where an exposure condition is corrected through a correction process, if the measured value is beyond the range of a prescribed value, and then a process 108 where a main exposure process is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method and an exposure apparatus, and more particularly, to an exposure method and an exposure apparatus capable of substantially preventing the occurrence of rework.

[0002]

2. Description of the Related Art In optical lithography, the wavelength has been shortened in order to suppress a decrease in the depth of focus while obtaining a resolving power. At present, at the mass production level, the i-line (365 nm)
Up to rF excimer laser (248 nm), and at the research and development level, from KrF excimer laser to ArF excimer laser (193 nm). from now on,
VUV (Vacuum Ultra) having a shorter wavelength
Studies using a laser in the (Violet) range are progressing, and specifically, an F2 laser (157 nm) or the like is a promising candidate.

Although the above is a discussion from the side of the exposing machine, a resist material is also an important factor in forming a pattern. In general, since the light absorption of an organic substance increases as the wavelength becomes shorter, g-line (365 nm), i-line, Kr
With the change to F and ArF, how to secure the transmittance of the resist has been a major issue. Transmittance is 40 ~
This is because, if it is reduced to 50% or less, the difference in light intensity between the surface of the resist film and the substrate side becomes large, and it becomes impossible to form a good pattern. Up to ArF, it is possible to maintain the other resist performance while maintaining the transmittance to some extent, and many ArF resists having a good pattern shape have been reported. On the other hand, no appropriate resist material has been reported for F2, and pattern formation using a conventional single-layer resist is not possible at present.

As a method capable of forming a good pattern even if the light absorption of the resist material is large, TSI (Top S
(surface imaging) technology. this is,
A light reaction is performed only in the vicinity of the resist film surface by exposure, and an exposed or unexposed portion is selectively subjected to a silylation reaction, and then a portion where no silylation reaction occurs is removed by dry etching to form a pattern. . T
There are many reports on SI technology (for example, Matsunaga et al., Proceedings of the 57th Annual Conference of the Japan Society of Applied Physics, No. 2, P476, 7).
p-S-1 (1996), Endo et al., Proc. 2, P645,3
a-SC-11, (1997)), TSI technology is also very promising for F2 laser lithography, and is likely to be the only possible resist process.

[0005] By the way, the TSI technology is generally used in FIG.
The process flow shown in FIG. In this process flow, first, a resist is applied (step 1001), and then exposure is performed (step 1002), silylation is performed (step 1002), dry development is performed (step 1004), and a displacement is measured by CD (step 1005). Check if it is within the value (Step 1
006) If not, the resist is stripped (step 1007), inspected (step 1008), and terminated (step 1009).

[0006]

As described above, the conventional steps become very complicated. In particular, the silylation reaction after the exposure and the dry development are steps which are not present in the conventional processes. For this reason, the pattern dimension standard and the superimposition standard impose an extremely heavy burden on rework (a series of steps from the resist peeling to the repetition of the steps in FIG. 10) in the case of deviation, which is economical. It is extremely undesirable from the viewpoint of yield. Therefore, it is necessary to develop a technology that does not cause rework. In addition, when performing a series of lot processing, a method of performing pilot exposure on the first few semiconductor substrates has been adopted, but since the substrate used for pilot exposure is similar to rework,
There is a need for a technique that does not require pilot exposure.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an exposure method and an exposure apparatus which do not require pilot exposure in order to solve the above-mentioned problem.

[0008]

In order to achieve the above object, an exposure method according to the present invention is an exposure method for transferring a circuit pattern on a mask to a semiconductor substrate by a surface image forming technique. After aligning, a step of exposing only the inspection pattern portion formed on the mask, a step of measuring a latent image of the exposed inspection pattern portion by an optical microscope and an atomic force microscope, and a measurement value or its induction A step of comparing the value with a predetermined value, and performing exposure if the value is within the predetermined value and correcting exposure conditions by a predetermined correction process if the value is outside the predetermined value, and a step of performing main exposure. It is characterized by the following.

Preferably, the step of measuring includes obtaining a line width and a misalignment using a latent image of the resist after the test exposure so as not to cause rework (reconstruction).

Further, an atomic force microscope measures a step by utilizing a phenomenon in which a light irradiation part of a resist contracts in volume, and predicts a line width from a correlation between the step and a line width obtained in advance. Is preferred.

Further, it is preferable that the optical microscope measures the overlay displacement by utilizing the change in the transmittance of the resist and the change in the absorption wavelength accompanying the volume shrinkage.

Further, it is preferable that the atomic force microscope and the optical microscope are built in the exposure apparatus.

Further, the optical microscope is preferably used in common with an alignment optical system in the exposure apparatus.

Further, it is preferable that the wafer stage on which the semiconductor substrate is mounted is commonly used as a wafer stage for an atomic force microscope and an optical microscope.

An exposure apparatus according to the present invention is an exposure apparatus for transferring a circuit pattern on a mask to a semiconductor substrate by a surface image forming technique, wherein the optical microscope and the atomic force microscope measure a latent image of an exposed inspection pattern. With
The measured value or its induced value is compared with a predetermined value, and if it is within the predetermined value, the exposure is performed as it is, and if it is outside the predetermined value, the exposure condition is corrected by a predetermined correction process. .

Further, it is preferable that the wafer stage on which the semiconductor substrate is mounted is commonly used as a wafer stage for an atomic force microscope and an optical microscope.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a flowchart showing an embodiment of an exposure method according to the present invention in the order of steps. In this method, after a wafer is loaded on a stage (Step 101), an alignment mark is measured (Step 102), an exposure position is determined (Step 103), and only an inspection pattern portion is exposed (Step 10).
4), CD measurement (estimation) of the displacement (step 105),
It is checked whether the measured value is within a predetermined value (step 106). If the measured value is not within the predetermined value, the exposure condition is corrected (step 107). If the measured value is within the predetermined value, main exposure is performed (step 107), and the wafer is unloaded. (Step 108) and end (Step 10).
9). The exposure method of the present invention comprises the steps 104, 105,
Other than 106, it is the same as the conventional exposure method. That is, the exposure method of the present invention determines the exposure position after the alignment mark measurement (Step 102) (Step 103),
It is characterized in that only the inspection pattern portion is exposed (step 104), and the displacement is measured (predicted) by CD (step 105).

Next, FIG. 2 is a plan view showing the configuration of the reticle in the embodiment of the present invention. In order to obtain a latent image of only the inspection pattern portion, a reticle having the configuration shown in FIG. 2, that is, a reticle 1 which is separated from the present chip portion 3 by a light-shielding band only in the inspection pattern portion 2 is used.

Next, FIG. 3 is a plan view showing the configuration of an embodiment of the exposure apparatus of the present invention. The AFM 4 and the optical microscope 6 built in the exposure device are used for observing the latent image of the resist. For the displacement, an optical microscope (or alignment optical system 5) is used.

Next, FIG. 4 is a schematic diagram showing measurement by a CD monitor. As described above, AFM is used for line width observation.
4 and the optical microscope 6, the line width cannot be directly obtained from the latent image. However, the dimensions after dry development are estimated by measuring the unevenness of the CD monitor 11 shown in FIG. The figure shows a large square outer box 9 and a smaller square inner box 10. Details will be described later.

Next, FIG. 5 is a schematic diagram showing a box mark in the embodiment of the present invention. As shown in this figure, the overlay error measurement pattern, commonly known as a box (B
ox) It is obtained by measuring a pattern. The box pattern has an outer box 9 and an inner box 10.

As described above, the line width and the positional deviation after the pattern formation can be predicted, so that the exposure is performed under the same condition if it is within a predetermined standard, and the condition is corrected by a preset correction formula if it is out of the standard. And exposure.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings.

First, the semiconductor substrate coated with the resist is introduced into an F2 laser exposure machine, and is processed from step 101 to step 103 in FIG. 1 in the same manner as in a normal exposure method. Next, using the reticle 1 shown in FIG. 2, the blind of the exposure machine is opened only in the inspection pattern section 2 and the semiconductor substrate is exposed. The portion to be exposed is selected in a scribe line or a peripheral portion of the substrate where no chip exists. Next, in the box mark formed from the latent image and the base step shown in FIG.
The overlay error can be determined from the relative displacement between the outer box 9 and the inner box 10. The resist is
It is transparent to light having a long wavelength of 500 nm or more, and there is no problem in position measurement with an overlay measurement device. By exposing and measuring three or more real marks in the semiconductor substrate, correction factors such as shift, rotation, orthogonality, and magnification can be calculated. If the calculation result is equal to or smaller than a preset standard value, the exposure is performed as it is. The standard value may be defined by the measured overlay error itself, instead of being set by the correction factor.

Next, with reference to FIGS. 6 to 8, an increase and a decrease in the exposure amount will be described. Subsequent to the overlay error measurement, the line width is predicted. At this time, generally, a photosensitive organic material, particularly a chemically amplified resist, undergoes a volume change with exposure to light.
For example, when the CD monitor 11 shown in FIG. 4 is exposed on the substrate, the resist has a cross-sectional shape as shown in FIG.
The amount of film reduction (indicated by D in the figure) is measured by AFM (atomic force microscope). The completed line width is predicted from the relationship between the measured value, the film thickness reduction D obtained in advance as shown in FIG. 7, and the dimension (line width). The relationship shown in FIG. 7 differs depending on the conditions of silylation and dry development. Similarly, by using the relationship between the exposure amount and the film reduction amount D obtained in advance as shown in FIG. 8, it can be understood how much the exposure amount should be increased or decreased to obtain a desired size. In the same manner as in the case of the displacement, the exposure is performed as it is by comparing it with a standard value or exposing as it is, or performing exposure amount correction.

When measuring the amount of film reduction by the AFM 4 described above, the semiconductor substrate remains on the wafer stage 8. This is because once released from the fixed state when performing position measurement, the correction value already obtained cannot be used (it is necessary to start over). Therefore, the fact that the wafer stage 8 is shared between the exposure and the AFM measurement is one of the features constituting the exposure apparatus of the present invention.

As described above, when the condition that the displacement and the line width are sufficiently within the standard is found, the blind of the exposure apparatus is opened so that the light is applied only to the main chip portion 3 of the reticle 1, and the main exposure is performed. Start (step 107). Subsequent steps are the same as in the case of ordinary TSI technology.

Next, another embodiment of the present invention will be described with reference to FIG.

FIG. 9 is a plan view showing the configuration of a reticle according to another embodiment of the present invention. When the reticle of FIG. 2 is used, the rotation, orthogonality, and magnification of the wafer can be corrected, but the rotation, orthogonality, and magnification of the chip cannot be corrected. Therefore, as shown in FIG. 9, if a reticle 1a having test pattern portions 2a and 2b arranged above and below the chip portion 3 is used, it is possible to correct a correction factor relating to the chip.

In the process flow of FIG. 1, the latent image measurement is performed for each substrate, but it is not always necessary.
In many cases, the first one or several sheets of the lot are sufficient.

[0032]

As described above, according to the present invention, since the actual exposure is performed to obtain the correction values relating to the positional deviation and the line width, the occurrence of rework due to at least these two factors is suppressed to a very small level. (To the extent that there is no problem even if the substrate on which rework has occurred is discarded).

Further, most of the factors causing the rework are only the above-mentioned two factors of the positional deviation and the line width, so that there is an effect that the economy can be improved and the TAT can be reduced.

Further, at the time of rework, the mixture of the organic substance formed by the silylation reaction and the dry development and SiO ₂ must be peeled off cleanly. This mixture is a substance that is very difficult to peel off, but if it remains, it becomes a defect and causes a decrease in yield. However, the effect of improving the yield by eliminating one defect generation factor in a lithography process that has been performed 10 times or more is achieved. Play.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of an exposure method according to the present invention in the order of steps.

FIG. 2 is a plan view showing a configuration of a reticle according to the embodiment of the present invention.

FIG. 3 is a partially enlarged view showing an inspection pattern according to the embodiment of the present invention.

FIG. 4 is a plan view showing a configuration of an example of the present invention.

FIG. 5 is a schematic diagram showing a box mark in the embodiment of the present invention.

FIG. 6 is an AFM of a CD monitor according to the embodiment of the present invention.
It is a schematic diagram showing measurement.

FIG. 7 is a graph showing the relationship between deposition collection and line width in an example of the present invention.

FIG. 8 is a graph showing the relationship between deposition shrinkage and line width.

FIG. 9 is a plan view showing an example of a conventional reticle.

FIG. 10 is a flowchart showing the operation of the conventional example.

[Explanation of symbols]

 Reference Signs List 1 reticle (example) 1a, 1b reticle (other example) 2 inspection pattern part (example) 2a, 2b inspection pattern (other example) 3 main chip part 4 AFM 5 (Off-axis) alignment optical system 6 Projection optical system 7 Wafer 8 Wafer stage 9 Outer box 10 Inner box 11 CD monitor

Claims (9)

[Claims] 1. An exposure method for transferring a circuit pattern on a mask onto a semiconductor substrate by a surface image forming technique, wherein an inspection pattern portion formed on the mask after performing alignment between the semiconductor substrate and the mask. Only exposing, and measuring the exposed latent image of the inspection pattern portion with an optical microscope and an atomic force microscope, and comparing the measured value or its induced value with a predetermined value, An exposure method comprising: exposing as it is if the value is within the predetermined value; and correcting exposure conditions by a predetermined correction process if the value is outside the predetermined value; and performing a main exposure. 2. The method according to claim 1, wherein the measuring step includes rework (reconstruction).
2. The exposure method according to claim 1, further comprising obtaining a line width and a misregistration using a latent image of the resist after the test exposure so as not to generate the image. 3. The atomic force microscope measures a step using a phenomenon in which a light irradiation part of the resist contracts in volume, and predicts a line width based on a correlation between the step and a line width obtained in advance. The exposure method according to claim 2, wherein the exposure is performed. 4. The optical microscope according to claim 2, wherein the optical microscope measures overlay deviation using a change in transmittance of the resist or a change in absorption wavelength accompanying volume shrinkage. Exposure method. 5. The apparatus according to claim 1, wherein said atomic force microscope and said optical microscope are built in an exposure apparatus.
5. The exposure method according to any one of items 1 to 4. 6. The optical microscope according to claim 5, wherein said optical microscope is shared with an alignment optical system in said exposure apparatus.
Exposure method according to 1. 7. A wafer stage on which the semiconductor substrate is mounted is commonly used as a wafer stage for the atomic force microscope and the optical microscope. Exposure method. 8. An exposure apparatus for transferring a circuit pattern on a mask to a semiconductor substrate by a surface image forming technique, comprising: an optical microscope and an atomic force microscope for measuring a latent image of an exposed inspection pattern; Alternatively, the induced value is compared with a predetermined value, and if it is within the predetermined value, the exposure is performed as it is, and if it is outside the predetermined value, the exposure condition is corrected by a predetermined correction process. Exposure equipment. 9. An exposure apparatus according to claim 8, wherein a wafer stage on which said semiconductor substrate is mounted is shared as a wafer stage for said atomic force microscope and said optical microscope.