JP2000298995A - Analog associative memory and analog operation element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable performing accurate operation without being affected by parasitic capacity of a wiring part and the like in an analog associative memory performing picture operation processing obtaininfg difference between reference data and input data with an analog value and using sum of absolute values of difference between this reference data and input data. SOLUTION: Analog storage elements A11-Amn are provided at one side of a differential amplifier circuit having a load circuit of a current mirror type. A value corresponding to reference analog data is stored in this analog storage elements A11-Amn. And a value corresponding to input data is given to the other input of the differential amplifier circuit. And a value corresponding to difference between a value corresponding to reference analog data and a value corresponding to input analog data is outputted by this differential amplifier circuit. Sum of absolute values of difference between reference data and input data can be obtained accurately and at high speed with simple constitution accurately by using such an analog associative memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an analog associative memory suitable for extracting features of an image and detecting a motion vector.

[0002]

2. Description of the Related Art In signal processing such as image feature extraction and motion vector detection, an absolute value sum (Manhattan distance) of a difference between input data and reference data is obtained, and an absolute difference between the input data and the reference data is calculated. A template matching method for searching for an address that minimizes the value sum is used. Image processing by such template matching is conventionally performed by digital signal processing. However, in image processing, it is necessary to hold a large number of feature vectors of several types of image patterns and object shapes in a reference area, and to quickly search for data most similar to newly obtained image information. When such processing is performed by digital signal processing,
There is a problem that as the reference data area becomes larger, the time required for the search becomes longer. For this reason,
When the reference data area is enlarged, a high calculation speed is required.

On the other hand, recently, by performing these signal processings in large scale and in parallel with analog signals, the time required for the signal processing is remarkably shortened.
A technique for reducing the power consumption of a signal processing device and reducing the chip area has attracted attention. Among them,
An analog content addressable memory (Analog Content Addressable) that calculates the absolute sum of the difference between the input analog data and the reference analog data and detects the smallest vector
Memory CAM) has attracted attention as a means for enabling high-speed arithmetic processing in a template matching method used for image feature extraction, motion detection, and the like.

The analog associative memory allows parallel processing. For this reason, the search time does not depend on the size of the data area, and the larger the reference data area, the faster the calculation time as compared with digital signal processing.

As shown in FIG. 18, a conventional analog associative memory has a stacked gate type NMOS transistor ST.
R51 and STR52 are used as analog operation elements, and the difference between input data and reference data is obtained as an analog value using a capacitor formed between the control gate and the transistor channel.

1) ISSCC 1997 TP2.4 P44 2) IEDM1994 P449 3) IEEE Micro October 1996 P20 4) IEDM 1997 P337 That is, as shown in FIG. 19, as shown in FIG. In the well 52,
A drain 53 and a source 54 are formed, and a floating gate 55 and a control gate 56 are provided for this. A capacitor acts between the control gate 55 of the stack gate type MOS transistor and the transistor channel as a capacitor. The charge amount Qch of the capacitor is, as shown in FIG.
Vt).

Here, Vg is the potential of the control gate 56, and Vt is the threshold voltage of the transistor.
In FIG. 20, the horizontal axis represents the control gate 56.
The vertical axis indicates the amount of charge of the capacitor between the control gate and the transistor channel.

Therefore, if the control gate potential Vg is made to correspond to the analog value of the input data, and Vt determined by the charge injected into the floating gate is made to correspond to the analog value of the reference data to be stored, the analog value of the input data and the reference data will The difference is obtained as the charge amount Qch of the charge of the capacitor formed between the control gate 55 and the transistor channel.

Here, assuming that the level of the input data is Vin and the level of the stored reference data is Vstore, when the threshold value Vt is the minimum value Vtmin, the control gate potential Vg and the threshold voltage Vt become Vg = Vtmin + Vin Vt = Vtmin + Vstore, and the difference value Vg-Vt = Vin-Vstore.

However, at this time, the difference value is obtained only when the control gate potential Vg is larger than the threshold voltage Vt (Vg ≧ Vt). If the control gate potential Vg is smaller than the threshold voltage Vt (Vg <Vt), the operation cannot be performed.

Therefore, as shown in FIG. 18, two stack gate type transistors STR51 and STR52 are complementarily provided as shown in FIG. 18 so that the operation can be performed even when the control gate potential Vg is smaller than the threshold voltage Vt (Vg <Vt). Be prepared.

Reference data is stored in one of the stacked gate type transistors STR51 so that Vt = Vtmin + Vstore, and when the control gate potential Vg is larger than the threshold voltage Vt (Vg> Vt), Vg-Vt = Vin-Vstore, the charge amount Qch corresponding to the analog value of the difference is obtained.

The other stack gate type transistor ST
The reference signal is stored in R52 such that Vt '= Vtmax-Vstore (Vtmax is the maximum value of Vt). As a result, the voltage applied to the control gate becomes Vg '= Vtmmax + Vin. When the control gate potential Vg is smaller than the threshold voltage Vt (Vg <Vt), Vt'-Vg = Vstore-Vin, and the analog value of the difference is obtained. Is obtained.

Thus, a charge amount Qch corresponding to the sum of absolute differences | Vin−Vsore | is obtained irrespective of the magnitudes of Vin and Vstore.

As described above, the analog value of the difference between the reference data and the input data obtained as the charge amount Qch is converted into a voltage value by the integrator 61 including the operational amplifier OP51, the capacitor C51, and the reset switch S51. It is taken out.

In this manner, the analog operation elements AF, AF,... Including the two stacked gate transistors STR51 and STR52 are arranged in a matrix as shown in FIG. These analog arithmetic elements AF, A
F,..., The difference between the reference data and the input data is obtained as the charge amount Qch, and the operational amplifier OP
51 and an integrator 61 constituted by a capacitor C51
Supplied to The charge amount Qch corresponding to the difference absolute value calculated by each analog calculation element is added by this integrator, and the sum of the difference absolute values is output as a voltage value for each row.

The output value of the integrator 61 is W
TA (Winner Take All) circuit 62, PQ (Priority Q)
ueue) Finally, an address having the smallest absolute value sum of the differences is output through the circuit 63 and the output ROM 64.

As described above, if the reference vector is formed in the row direction of the memory array and a signal corresponding to the input vector is applied in the column direction, the search for the vector having the shortest distance can be performed at high speed.

[0019]

However, in the conventional analog associative memory, the charge amount Qch of the capacitor formed between the control gate and the transistor channel is used as a signal source for the operation. Such charges are easily affected by the parasitic capacitance of the transistor or the wiring portion, and cause deterioration of the dynamic range of a signal. Further, these parasitic capacitances become remarkable with miniaturization of elements, which is disadvantageous for future large capacity and high integration.

Accordingly, it is an object of the present invention to provide an analog associative memory and an analog arithmetic element capable of performing an accurate arithmetic operation without being affected by a parasitic capacitance or the like of a wiring portion.

[0021]

According to the first aspect of the present invention, there is provided the following:
An analog associative memory in which analog arithmetic elements for obtaining a difference between the analog data and the second analog data are arranged in a matrix, wherein the analog arithmetic element is one of a differential amplifier circuit having a current mirror type load circuit. And a value corresponding to the second analog data is stored in the analog storage element, and a value corresponding to the first analog data is given to the other input of the differential amplifier circuit. An analog content addressable memory configured to output a value corresponding to a difference between a value corresponding to the second analog data and a value corresponding to the first analog data by a differential amplifier circuit.

According to a third aspect of the present invention, an analog storage element is provided in one of the differential amplifier circuits having a current mirror type load circuit, and a value corresponding to the second analog data is stored in the analog storage element. The first input to the other input of the amplifier circuit
Analog operation element for giving a value corresponding to the analog data of the above and outputting a value corresponding to the difference between the value corresponding to the second analog data and the value corresponding to the first analog data by the differential amplifier circuit It is.

According to a fifth aspect of the present invention, there is provided an analog associative memory in which analog arithmetic elements for obtaining a difference between the first analog data and the second analog data are arranged in a matrix. And a current mirror type load circuit connected between a differential amplifier circuit including a first MOS transistor and a stack gate type MOS transistor and a reference potential; A first input terminal derived from the gate of the transistor, a second input terminal derived from the control gate of the stacked gate MOS transistor, and a connection point between the current mirror type load circuit and the stacked gate MOS transistor. Derived output terminal, stack gate type The floating gate potential of the OS transistor is set to be the value of the second analog data when a predetermined potential is applied to the control gate, and a value corresponding to the first analog data is input to the first input terminal. , A predetermined potential is applied to the second input terminal, and a current corresponding to the difference between the value of the second analog data and the value of the first analog data is output from the output terminal. It is.

According to an eleventh aspect of the present invention, there is provided a differential amplifier comprising a MOS transistor and a stack gate type MOS transistor, and a differential amplifier comprising a first MOS transistor and a stack gate type MOS transistor and a reference potential. A connected current mirror type load circuit;
A first input terminal derived from the gate of the OS transistor, a second input terminal derived from the control gate of the stacked gate MOS transistor, and a connection point between the current mirror type load circuit and the stacked gate MOS transistor And a floating gate potential of the stack gate type MOS transistor is set to be a value of the second analog data when a predetermined potential is applied to the control gate. A value corresponding to the first analog data is applied to the input terminal of the first analog data, a predetermined potential is applied to the second input terminal, and the difference between the value of the second analog data and the value of the first analog data is output from the output terminal. Is an analog operation element configured to output a current corresponding to.

According to a fifteenth aspect of the present invention, there is provided an analog associative memory in which analog arithmetic elements for obtaining a difference between the first analog data and the second analog data are arranged in a matrix. MOS
A differential amplifier circuit comprising a transistor and a second MOS transistor; a first MOS transistor and a second MO transistor.
A current mirror type load circuit connected between a differential amplifier circuit comprising an S transistor and a reference potential;
A stack gate type MOS transistor forming a source follower circuit for the gate of the S transistor;
A first input terminal derived from the gate of the MOS transistor, a second input terminal derived from the control gate of the stacked gate MOS transistor, and a third input derived from the drain of the stacked gate MOS transistor Terminal, and an output terminal derived from a connection point between the current mirror type load circuit and the second MOS transistor. When a threshold voltage of the stack gate type MOS transistor is applied to a control gate at a predetermined potential, The value is set so as to be the value of the second analog data, a value corresponding to the first analog data is applied to the first input terminal, a predetermined potential is applied to the second input terminal, and the output terminal A current corresponding to the difference between the value of the second analog data and the value of the first analog data. A log associative memory.

According to a twenty-first aspect of the present invention, a differential amplifier circuit comprising a first MOS transistor and a second MOS transistor, a differential amplifier circuit comprising a first MOS transistor and a second MOS transistor, and a reference A current mirror type load circuit connected between the potentials, a stack gate type MOS transistor forming a source follower circuit for the gate of the second MOS transistor, and a first MO transistor
A first input terminal derived from the gate of the S transistor, a second input terminal derived from the control gate of the stacked gate MOS transistor, and a third input terminal derived from the drain of the stacked gate MOS transistor And an output terminal derived from a connection point between the current mirror type load circuit and the second MOS transistor. When a predetermined potential is applied to the control gate, the threshold voltage of the stacked gate type MOS transistor is increased. 2, a value corresponding to the first analog data is applied to the first input terminal, and a predetermined potential is applied to the second input terminal. An analog that outputs a current corresponding to the difference between the value of the second analog data and the value of the first analog data Calculated element.

According to a twenty-fifth aspect of the present invention, there is provided an analog associative memory in which analog arithmetic elements for obtaining a difference between the first analog data and the second analog data are arranged in a matrix. A differential amplifier circuit comprising a first MOS transistor and a stack gate type MOS transistor; a current mirror type load circuit connected between a first amplifier transistor and a stack gate type MOS transistor; A switching transistor provided between the floating gate of the gate type MOS transistor and the MOS transistor; a first input terminal derived from the gate of the MOS transistor; and a second input terminal derived from the control gate of the stacked gate type MOS transistor. Input terminal An output terminal derived from a connection point between the current mirror type load circuit and the stack gate type MOS transistor. The floating gate potential of the stack gate type MOS transistor is supplied to the control gate via the switching transistor. It is set so as to be the value of the second analog data when applied, a value corresponding to the first analog data is applied to the first input terminal, and a predetermined potential is applied to the second input terminal The value of the second analog data and the first
Is an analog associative memory configured to output a current corresponding to the value of the analog data and the difference.

According to a thirtieth aspect of the present invention, there is provided a differential amplifier comprising a MOS transistor and a stack gate type MOS transistor, and a differential amplifier comprising a first MOS transistor and a stack gate type MOS transistor and a reference potential. A connected current mirror type load circuit, a switching transistor provided between the floating gate and the MOS transistor of the stack gate type MOS transistor, a first input terminal derived from the gate of the MOS transistor, and a stack gate. Type MOS
The second derived from the control gate of the transistor
And an output terminal derived from a connection point between the current mirror type load circuit and the stack gate type MOS transistor. The floating gate potential of the stack gate type MOS transistor is set to a predetermined potential via a switching transistor. Is set to be the value of the second analog data when applied to the control gate, a value corresponding to the first analog data is applied to the first input terminal, and a predetermined value is applied to the second input terminal. Is applied to output an electric current corresponding to the difference between the value of the second analog data and the value of the first analog data from the output terminal.

An analog storage element is provided on one side of a differential amplifier circuit having a current mirror type load circuit, a value corresponding to reference analog data is stored in this analog storage element, and the other input of the differential amplifier circuit is provided on the other input. , An analog operation element that is provided with a value corresponding to the input analog data and outputs a value corresponding to a difference between the value corresponding to the reference analog data and the value corresponding to the input analog data by the differential amplifier circuit. By disposing them in a matrix, an analog associative memory is formed. When such an analog content addressable memory is used, the absolute value sum of the difference between the reference data and the input data can be obtained with a simple configuration, with high accuracy, and at high speed.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION
Description will be made with reference to the drawings in the following order.

1. First embodiment of analog associative memory 1-1. Overall configuration of first embodiment of analog associative memory 1-2. First example of analog operation element 1-3. Operation of first example of analog operation element 1-4. Modified example of first embodiment of analog associative memory 1-5. Example of current-voltage conversion circuit 1-6. 1. An example of a circuit for obtaining the absolute value sum of the difference Second embodiment of analog associative memory 2-1. Overall configuration of second embodiment of analog associative memory 2-2. Second example of analog operation element 2-3. Operation of second example of analog operation element 2-4. 2. Modified example of second embodiment of analog associative memory Third embodiment of analog associative memory 3-1. Overall configuration of third embodiment of analog associative memory 3-2. Third example of analog operation element 3-3. Operation of third example of analog operation element 3-4. 3. Modification of the third embodiment of the analog associative memory Application example.

1. First embodiment of analog associative memory 1-1. FIG. 1 shows an analog associative memory according to a first embodiment of the present invention. In FIG. 1, A1
1 to Amn are analog operation elements. The analog operation elements A11 to Amn are analog operation elements that calculate the difference between the reference data of the analog value and the input data of the analog value by the analog value.

As shown in FIG. 2, each of the analog operation elements A11 to Amn includes NMOS transistors TR1 and TR1.
2, TR3 and TR4, and a stack gate type NMOS transistor STR1.

That is, FIG. 2 shows the details of the analog operation elements A11, A12,..., A21, A22,. In the analog operation elements A11, A12,..., A21, A22,.
The MOS transistor TR1 and the stack gate type transistor STR1 form a differential amplifier circuit. A transistor TR4 for selecting an element is connected between the power supply line and a differential amplifier circuit including the transistor TR1 and the stack gate transistor STR1. Further, a current mirror circuit including a transistor TR2 and a transistor TR3 is connected between the ground and a differential amplifier circuit including the transistor TR1 and the stack gate transistor STR1.

A terminal IN1 for inputting data is derived from the gate of the transistor TR1. From the control gate of the stacked gate transistor STR1, a terminal IN for storing reference data is stored.
2 is derived. Stack gate type transistor STR
A terminal OUT1 for obtaining a current output is derived from a connection point between the transistor 1 and the transistor TR3. The terminal OU
T1 is also used to apply a bias voltage when writing reference data. A terminal IN3 for selecting an element is derived from the gate of the transistor TR4.

As shown in FIG. 1, the analog operation element A1
1 to Amn are arranged in a (m × n) two-dimensional matrix. Analog arithmetic elements A11 to Am arranged in the row direction
1, terminals IN1 derived from A12 to Am2 and A1n to Amn are connected to input data lines SL1 to SLn, respectively. Further, the analog operation elements A11 arranged in the row direction
Am1, A12 to Am2, and terminals IN2 derived from A1n to Amn are connected to reference data lines RL1 to RL1.
RLn.

Analog arithmetic elements A11 to A arranged in the column direction
Terminals OUT1 derived from 1n, A21 to A2n,..., Am1 to Amn are connected to the data lines DL1 to DLm, respectively. Further, the analog operation elements A arranged in the column direction
Terminals IN3 derived from 11 to A1n, A21 to A2n,..., Am1 to Amn are connected to select lines SWL1 to SWL1.
SWLm.

At the ends of the data lines DL1 to DLm,
The current-voltage conversion circuits CV1, CV2,..., CVm are respectively connected. Analog operation elements A11 to A1n, A arranged in the column direction by current-voltage conversion circuits CV1 to CVm.
, Am1 to Amn are respectively added and converted into voltage outputs.

The outputs of the current-voltage conversion circuits CV1 to CVm are supplied to a WTA (Winner Take All) circuit 1. W
The output of the TA circuit 1 is supplied to a PQ (Priority Que) circuit 2. The output of the PQ circuit 2 is supplied to the ROM circuit 3. The output of the ROM 3 is output from the output terminal 4.

In the analog content addressable memory shown in FIG.
When performing signal processing such as image feature extraction and motion vector detection, the analog value reference data forms vectors (DRm1, DRm2,... DRmn), and the analog arithmetic elements A11 to A1n, A21 to A21. A2
,..., Am1 to Amn.

Reference data is stored in each of the analog operation elements A11 to A1n, A21 to A2n,..., Am1 to Amn.
Is stored in the input signal vector (DI1, DI2,
.. DIm) are supplied through the input data lines SL1 to SLn.

When performing signal processing such as image feature extraction and motion vector detection, the analog operation elements A11 to A1n, A21 to A2n,.
Amn, input data (DI1, DI2, ..., DIn)
, And reference data (DRm1, DRm2,..., D
Rmn). The analog operation elements A11 to A1n, A21 to A2n,.
The difference value between the input data of Amn and the reference data is added, and the sum of the difference values is used as the current-voltage conversion circuit C
V1, CV2,..., CVm.

The current-voltage conversion circuits CV1, CV2,.
The output of CVm is supplied to a WTA circuit 1, a PQ (Priority Que) circuit 2, and a ROM circuit 3, and an address at which the sum of absolute differences between the input data and the reference data is minimized is obtained. From the address where the sum of absolute values of the difference between the input data and the reference data is the smallest, detection of a motion vector and extraction of image features are performed.

1-2. First Example of Analog Arithmetic Element As described above, in the analog associative memory shown in FIGS. 1 and 2, the analog arithmetic elements A11 to Amn including the transistors TR1 to TR4 and the stack gate type transistor STR1 are arranged in a matrix. It is arranged in. The difference between the input data and the reference data is obtained by these analog operation elements A11 to Amn. Image feature extraction and motion vector calculation are performed from the sum of the differences between the input data and the reference data thus obtained.

As described above, the analog arithmetic elements A11 to Amn for obtaining the difference between the input data and the reference data
Will be described in more detail.

FIG. 3 shows a first example of the configuration of the analog operation element. As shown in FIG. 3, the analog operation element has a configuration in which the positive side transistor of the differential amplifier circuit is replaced with a stack gate type transistor STR1. Note that the stack gate type transistor S constituting the positive side of the differential amplifier circuit
The channel width of TR1 and the transistor TR1 forming the negative side of the differential amplifier circuit are set to the same size.

Stack gate type transistor STR1
Is a P-well 12 on an N-type substrate 11 as shown in FIG.
In addition, a drain 13 and a source 14 are formed, and a floating gate 15 and a control gate 16 are provided. In such a stack gate type transistor, the electric charge of the floating gate 15 can be taken in and out according to the voltage applied to the control gate 16, and the potential of the floating gate 15 can be set and held.

In FIG. 3, in a differential amplifier circuit composed of a stack gate type transistor STR1 and a transistor TR1, a negative side transistor TR1
Gate potential Vi and the stack gate type transistor S
When the floating gate potential Vf of TR1 matches, the current capability of the transistor TR1 and the current capability of the stack gate type transistor STR1 become equal, and the current output of the differential amplifier circuit becomes "0". Therefore, the floating gate potential Vf of the stack gate type transistor STR1 and the gate potential Vi of the transistor TR1
, A current output Iout according to the difference (Vf-Vi) can be obtained from the node Nout.

Therefore, for example, the power supply voltage V is applied to the control gate of the stack gate type transistor STR1.
If the amount of current injection is controlled so that the floating gate potential Vf when dd is applied corresponds to the reference data Vr, the stacked gate transistor S
TR1 functions as an analog memory for storing reference data.

As described above, the transistors TR1 to TR4
And an analog operation element composed of a stack gate type transistor STR1, the reference data is stored in the stack gate type transistor STR1, and the input data is given to the transistor TR1 to obtain the difference between the input data and the reference data. Can be obtained.

1-3. Operation of First Example of Analog Associative Memory Next, an operation when reference data is written to each of the analog operation elements A11 to Amn of the analog associative memory shown in FIGS. 1 and 2 will be described.

Each of the analog operation elements A11 to Amn of the analog associative memory shown in FIGS. 1 and 2 is set to the erase mode before the reference data is written. In the erase mode, the reference lines RL1, RL
2,... Are supplied with a high erasing voltage Ve of about 20V.

When the high voltage Ve is supplied to the reference lines RL1, RL2,...
The voltage is applied to the control gate of the stack gate type transistor STR1 of the analog operation elements A11 to Amn via N2. High voltage Ve for erasing is applied to the control gate of the stack gate type transistor STR1.
Is applied, electrons are injected into the floating gate of the stacked gate transistor STR1 from the substrate of the transistor, and the potential of the floating gate shifts to a negative potential.

At this time, the input data lines SL1,
SL2,... Are set to 0 V and the select line SW
L1, SW2, SW3,... Are set to 0 V, and the transistors TR1 and TR4 are turned off. Data line D
Lm is also set to 0V.

In a state where data is erased, the potential of the floating gate of the stack gate type transistor STR1 is greatly shifted to a negative potential. Therefore, even if the voltage Vdd is applied to the control gate, the channel of the stack gate type transistor STR1 is not changed. Remains off,
Current does not conduct.

Next, a write mode is set. In the write mode, the reference data lines RL1, R
L2,..., The analog operation elements A11 to A1n, A
-10 to the control gates of the stacked gate transistors STR1 of 21 to A2n,.
A negative voltage of about V is applied. In this state, a potential of about 6 V is applied by the data lines DL1, DL2,... To a node corresponding to the source diffusion layer of the stacked gate transistor STR1.

When such a bias voltage is applied,
Electrons in the floating gate of the stack gate type transistor STR1 are extracted to the source diffusion layer, and the floating gate potential Vf shifts positively.

Here, when the bias is applied, the input data lines SL1, SL2,.
.. Are set to 0 V, and the transistors TR1,
TR4 is turned off, the nodes N1 and N2 (see FIG. 3) are opened, and a through current between the wirings is prevented.

In setting, the distance between the node Nout and the ground is
If a through current can flow through the transistor TR3, a transistor for preventing a through current may be provided between the transistor TR3 and the ground.

At the time of writing, the write mode and the verify mode are alternately repeated to determine the write level. By such a verify operation,
The potential of the floating gate is accurately matched to a desired write level corresponding to reference data.

That is, in the verify mode, the analog potential Vr to be stored in the floating gate of the stacked gate type transistor STR1 is applied to the gate of the negative input transistor TR1 by the input data lines SL1, SL2,. The power supply voltage Vdd is applied to the control gate of the stacked gate transistor STR1 by the reference data lines RL1, RL2,. Select lines SWL1, S
The transistors TR4 in the column selected by WL2,.
Is turned on. As a result, a differential amplifier circuit including the transistor TR1 and the stack gate transistor STR1 operates.

In this case, the gate of the negative side input transistor TR1 is connected to the stack gate type transistor ST.
Since the analog potential Vr to be stored is applied to the floating gate of R1, if a potential corresponding to Vr is written to the floating gate of the stacked-gate transistor STR1, the current capabilities of the transistor TR1 and the stacked-gate transistor STR1 become It becomes equal, and the output current becomes “0”. If the potential of the floating gate of the stacked-gate transistor STR1 is lower than Vr, the output current becomes negative (captures current).
If the potential of the floating gate of the stacked gate transistor STR1 is higher than Vr, the output current becomes positive (outputs current).

In the first writing to the floating gate of the stack gate type transistor STR1, the writing is not sufficient, and the potential of the floating gate is Vr
When the verify operation is performed, the output current becomes negative.

When the output current is negative during verification,
The writing mode is reset, a writing bias is applied, and writing to the floating gate of the stacked gate transistor STR1 is performed.

When the verify operation is performed in the next write operation, the write operation is not sufficient. If the output current is negative, the write mode is set again, a write bias is applied, and the stack gate type transistor STR is turned on.
1 is written to the floating gate.

Thereafter, similarly, a write bias is repeatedly applied, and verification is performed each time.

When writing is repeated as described above,
The floating gate potential of the stacked gate transistor STR1 gradually increases, and the potential of the floating gate eventually reaches Vr. When the floating gate potential becomes higher than the potential Vr of the reference data, the output current at the time of verification changes from negative to positive.

When the output current at the time of verification changes from negative to positive, it is assumed that the potential of the floating gate has reached Vr, and the writing is terminated.

As described above, if the verify operation is performed while repeating the write operation and the point where the output current changes from negative to positive is detected and the write operation is terminated, the stack gate type at the time of applying the voltage Vdd to the control gate can be used. The potential of the floating gate of the transistor STR1 can be set substantially equal to the potential Vr of the reference data.

When the potential corresponding to the potential Vr of the reference data is written to the potential of the floating gate of the stack gate type transistor STR1 in this manner, the operation mode can be set.

In the operation mode, the input data line SL
The analog potential Vi corresponding to the input data is applied to 1, SL2,. This potential Vi is applied to the gate of the negative-side input transistor TR1 via the terminal IN1. Further, the reference data lines RL1, R
The power supply voltage Vdd is supplied to L2,. This power supply voltage Vdd is applied to the control gate of the stack gate type transistor STR1 via the terminal IN2. Then, by the select lines SWL1, SWL2,...
The transistor TR4 in the selected column is turned on.

As described above, the analog potential Vr corresponding to the reference data is stored in the floating gate of the stack gate type transistor STR1. Therefore, a current output corresponding to the difference between the reference analog data Vr and the input analog data Vi is obtained by the differential amplifier circuit including the transistor TR1 and the stack gate type transistor STR1.

1-4. Modified Example of First Embodiment of Analog Associative Memory In the above example, one analog data element stores one reference data, but a plurality of reference data can be stored. You may do it. That is, in the example shown in FIG. 2, one transistor serving as the memory for the reference data is the stack gate type transistor STR1, but in the example shown in FIG. 5, three stack gate type transistors STR1a serving as the memory for the reference data are used. STR1
b, STR1c are connected in parallel. Thus, three stack gate type transistors STR1a, STR1b, STR1 are provided for one differential amplifier circuit.
When c is provided, three reference data can be held for one differential amplifier circuit. By doing so, the reference data lines RL1a, RL1
Reference data to be calculated can be selected at any time by 1b and RL1c.

1-5. Example of Current-to-Voltage Converter Next, the current-to-voltage converters CV1, CV in FIG.
2, CV3,... Will be described.

As shown in FIG. 1, input data is supplied as input signal vectors (DI1, DI2,... DIn) for each column through input data lines SL1, SL2,. Then, for each column, the analog operation elements A11 to A1n, A21 to A2n,.
The calculation is performed by Analog arithmetic elements A11 to A1
, Am1 to Amn, the operation output is output as a current value, and this current value is added to and converted into a voltage value by voltage-current conversion circuits CV1, CV2, CV3,. The voltage-current conversion circuits CV1, CV2,
CV3,... Can be configured as shown in FIG.

FIG. 6 shows the arithmetic elements A11 to A1n arranged in the same column in the analog arithmetic memory of FIG. The analog arithmetic elements A11 arranged in the same column
To A1n are connected to the data line DL1, and the terminals O1 to A1n of the analog operation elements A11 to A1n
The current output from UT1 is supplied to data line DL1.

The current-voltage conversion circuit CV1 includes an operational amplifier OP1 and a feedback resistor R1. The output of the data line DL1 is supplied to the inverting input terminal of the operational amplifier OP1. The voltage Vb is applied to the non-inverting input terminal of the operational amplifier OP1. The output of the operational amplifier OP1 is a resistor R
1 is fed back to the inverting input terminal of the operational amplifier OP1.

In such a configuration, the data line DL1
And terminals O of analog operation elements A11 to A1n in the same column.
A current, which is the sum of the output current from UT1, flows. The output of the operational amplifier OP1 is fed back to the inverting input terminal of the operational amplifier OP1 via the resistor R1, and a voltage Vb for fixing the output of the differential amplifier circuit is applied to the non-inverting input terminal of the operational amplifier OP1. Can be Therefore, a voltage output corresponding to a value obtained by adding the output currents of the analog operation elements A11 to A1n is obtained from the operation amplifier OP1.

1-6. Example of Circuit for Obtaining Sum of Absolute Values of Difference In the example of FIG. 6, current-voltage conversion circuit CV1 stores the data in the control gates of analog operation elements A11, A12,. Potentials vf1, vf2,
vf3,... and the potentials vi1, vi2, v of the input analog data.
The sum (Σ (vfn−vin)) of the differences with i3,... is output. However, in the process of extracting a motion vector and a feature of an image, it is strictly necessary to obtain the sum of absolute values of the differences (Σ | vfn−vin |).

FIG. 7 shows a configuration in which the sum of absolute values of differences between reference data and input data can be obtained. FIG. 7 shows portions of the analog operation elements A11 to A1n arranged in the same column from the analog associative memory in FIG. In the example shown in FIG. 1, one analog operation element for obtaining the difference between the data is provided for each element. In this example, however, two analog operation elements are used for obtaining the absolute value of the difference. Two analog operation elements are provided with opposite polarities.

That is, the analog arithmetic elements A11a and A11b, A1
2a and A12b,..., A1na and A1nb are provided.

The terminal IN1 of one of the analog operation elements A11a to A1na for each data is connected to the input data lines SL1 to SLn, respectively, and the terminal IN2 is connected to the reference data lines RL1 to RLn, respectively.
Terminal OUT1 of analog operation elements A11a to A1na
Are connected to the switch circuits Sa11 to Sa1n.

On the other hand, the terminal IN1 of the other analog operation element A11b to A1nb for each data is
The terminals IN2 are connected to the reference data lines RL1 to RLn, respectively, and the terminal IN2 is connected to the input data lines SL1 to SLn, respectively. Terminals OUT1 of the analog operation elements A11b to A1nb are connected to the switch circuits Sb11 to Sb1n, respectively.

Each terminal b of the switch circuits Sa11 to Sa1n is connected to the write line W1. The respective terminals a of the switch circuits Sa11 to Sa1n are connected to the input sides of the current mirror circuits CM11a to CM1na. The respective terminals b of the switch circuits Sb11 to Sb1n
Are connected to the write line W1. Switch circuit S
The respective terminals a of b11 to Sb1n are connected to the input sides of the current mirror circuits CM11b to CM1nb.

Two current mirror circuits CM11a and CM11b to CM1na and CM1 for each data
The outputs of nb are both connected to data line DL1. At the end of the data line DL1, a current-voltage conversion circuit CV1 is provided.

Current mirror circuits CM11a to CM1n
a is composed of PMOS transistors TR6 and TR7. The sources of the transistors TR6 and TR7 are connected to a power supply line. The gate of the transistor TR6 and T
The gate of R7 is connected, and this connection point is connected to the drain of transistor TR6. The drain of the transistor TR6 and the transistors TR6 and TR
The connection point with the gate 7 is the input side of the current mirror circuit. Further, the drain of the transistor TR7 is the output side of the current mirror circuit.

Current mirror circuits CM11b to CM1n
b is composed of PMOS transistors TR8 and TR9. The sources of the transistors TR8 and TR9 are connected to a power supply line. The gate of the transistor TR8 and T
The gate of R9 is connected, and this connection point is connected to the drain of transistor TR8. The drain of this transistor TR8 and the transistors TR8 and TR8
The connection point with the gate 9 is the input side of the current mirror circuit. Further, the drain of the transistor TR9 is the output side of the current mirror circuit.

In the current mirror circuits CM11a to CM1na and CM11b to CM1nb thus configured, a current equal to the current on the input side is output from the output side only when the input side is positive (current flows out).

In the operation mode, the switch circuits Sa11 to Sa11
Sa1n and the switch circuits Sb11 to Sb1n are all set to the a side. Therefore, the output of one of the analog operation elements A11a to A1na for each data is supplied to the current mirror circuits CM11a to CM1na via the switch circuits Sa11 to Sa1n. The outputs of the other analog operation elements A11b to A1nb are supplied to current mirror circuits CM11b to CM1nb via switch circuits Sb11 to Sb1n.

One of the current mirror circuits CM11a to CM1na for each data is connected to the analog operation element A1.
Only when the output currents of 1a to A1na are positive, currents corresponding to the output currents of the analog operation elements A11a to A1na are output to the data line DL1. The other current mirror circuits CM11b to CM1nb for each data
Indicates that the analog operation elements A11b to A1nb are output only when the output currents of the analog operation elements A11b to A1nb are positive.
Is output to the data line DL1.

As described above, for one data, two analog arithmetic elements A11a to A1na having opposite polarities to each other.
And A11b to A1nb, and these analog operation elements A11a to A1na and A11b to A1n
b, two current mirror circuits CM11a to CM1na and CM11 that operate only when a positive current is output.
By providing b to CM1nb, the absolute value sum of the difference can be obtained.

In the write mode, the analog operation elements A11a to A1na and A11b to A1nb are
It is necessary to apply a bias voltage of about 6 V to the source diffusion layer of the stack gate type transistor STR.
Therefore, the switch circuits Sa11 to Sa1n, Sb11
To Sb1n. In the write mode, a bias voltage of about 6 V required at the time of writing can be applied via the write line W1.

2. Second embodiment of analog associative memory 2-1. Overall Configuration of Second Embodiment of Analog Associative Memory FIG. 8 shows a second embodiment of an analog associative memory to which the present invention is applied. In FIG. 8, the same parts as those in the first embodiment are denoted by the same reference numerals.

In this example, the analog operation elements A11 to A11
mn is an NMOS transistor TR as shown in FIG.
11, TR12, TR13, TR14, and a stacked gate NMOS transistor STR11.

That is, FIG. 9 shows the details of the analog operation elements A11, A12,..., A21, A22,. In the analog operation elements A11, A12,..., A21, A22,.
The MOS transistors TR11 and TR15 form a differential amplifier circuit. These transistors TR11 and TR
15 and a power supply line,
A transistor TR14 for selecting an element is connected. Further, a current mirror circuit including a transistor TR12 and a transistor TR13 is connected between the differential amplifier circuit including the transistors TR11 and TR15 and the ground. The source of the stack gate type NMOS transistor TR11 is connected to the gate of the transistor TR15.

A terminal IN11 for inputting data is derived from the gate of the transistor TR11. A terminal IN12 for storing reference data is derived from the control gate of the stacked gate transistor STR11. A terminal IN14 for applying a write signal is led out from the drain of the stack gate transistor STR11. Transistor TR1
A terminal OUT11 for obtaining a current output is derived from a connection point between the transistor 5 and the transistor TR13. A terminal IN13 for selecting an element is derived from the gate of the transistor TR14.

As shown in FIG. 8, the analog operation element A1
1 to Amn are arranged in a (m × n) two-dimensional matrix. Analog arithmetic elements A11 to Am arranged in the row direction
1, terminals IN11 derived from A12 to Am2 and A1n to Amn are connected to input data lines SL1 to SLn, respectively. Further, the analog operation elements A1 arranged in the row direction
Terminals IN12 derived from 1 to Am1, A12 to Am2, and A1n to Amn are connected to a reference data line RL.
1 to RLn.

Analog operation elements A11 to A arranged in the column direction
Terminals OUT11 derived from 1n, A21 to A2n,..., Am1 to Amn are connected to the data lines DL1 to DLm, respectively. Further, the analog arithmetic elements A11 to A1n, A21 to A2n,.
Is derived from the select line SWL
1 to SWLm.

At the ends of the data lines DL1 to DLm,
The current-voltage conversion circuits CV1, CV2,..., CVm are respectively connected. Analog operation elements A11 to A1n, A arranged in the column direction by current-voltage conversion circuits CV1 to CVm.
, Am1 to Amn are respectively added and converted into voltage outputs.

The outputs of the current-voltage conversion circuits CV1 to CVm are supplied to the WTA circuit 1. WTA circuit 1 output is P
It is supplied to the Q circuit 2. The output of the PQ circuit 2 is supplied to the ROM circuit 3. The output of the ROM 3 is output from the output terminal 4.

In the analog content addressable memory shown in FIG.
When performing signal processing such as image feature extraction and motion vector detection, the analog value reference data forms vectors (DRm1, DRm2,... DRmn), and the analog arithmetic elements A11 to A1n, A21 to A21. A2
,..., Am1 to Amn.

Reference data is stored in each of the analog operation elements A11 to A1n, A21 to A2n,..., Am1 to Amn.
Is stored in the input signal vector (DI1, DI2,
.. DIm) are supplied for each column through the input data lines SL1 to SLn.

When performing signal processing such as image feature extraction and motion vector detection, the analog operation elements A11 to A1n, A21 to A2n,.
Amn, input data (DI1, DI2, ..., DIn)
, And reference data (DRm1, DRm2,..., D
Rmn). The analog operation elements A11 to A1n, A21 to A2n,.
The difference value between the input data of Amn and the reference data is added, and the sum of the difference values is used as the current-voltage conversion circuit C
V1, CV2,..., CVm.

The current-voltage conversion circuits CV1, CV2,.
The output of CVm is supplied to the WTA circuit 1, the PQ circuit 2, and the ROM circuit 3, and the address at which the sum of the absolute values of the differences between the input data and the reference data is minimized is obtained. From the address where the sum of absolute values of the difference between the input data and the reference data is the smallest, detection of a motion vector and extraction of image features are performed.

2-2. Second Example of Analog Arithmetic Element As described above, in the analog associative memory shown in FIGS. 8 and 9, the analog arithmetic elements A11 to Amn including the transistors TR11 to TR15 and the stack gate type transistor STR11 are arranged in a matrix. It is arranged in a shape. The difference between the input data and the reference data is obtained by these analog operation elements A11 to Amn. Image feature extraction and motion vector calculation are performed from the sum of the differences between the input data and the reference data thus obtained.

As described above, the analog operation elements A11 to Amn for obtaining the difference between the input data and the reference data
The configuration of the second example will be described in more detail.

FIG. 10 shows the configuration of a second example of the analog operation element. As shown in FIG. 10, this analog arithmetic element includes a stack gate type transistor ST15 connected to a transistor TR15 on the positive side of the differential amplifier circuit.
The configuration is such that a source follower made of R11 is added. The transistor TR15 forming the positive side of the differential amplifier circuit and the transistor TR11 forming the negative side of the differential amplifier circuit have the same channel width.

In FIG. 10, transistor TR15
And the transistor TR11, when the gate potential Vi of the negative transistor TR11 matches the gate potential of the positive transistor TR15, the current capability of the transistor TR11 and the The current capability becomes equal, and the current output of the differential amplifier circuit becomes “0”. The gate potential of the transistor TR15 is applied to the control gate of the stack gate type transistor STR11 by the power supply voltage V
If dd is applied, it becomes (Vdd-Vt). In addition,
Vt is a threshold voltage of the stack gate type transistor STR11. Therefore, a difference (Vdd-Vt-Vi) between the difference (Vdd-Vt) between the power supply voltage Vdd and the threshold voltage Vt and the gate potential Vi of the transistor TR11.
) Can be obtained from the node Nout.

Here, the output potential (Vdd-Vt) to the source side of the stack gate type NMOS transistor STR11
) Corresponds to the analog signal potential, the stacked gate transistor STR11 functions as an analog memory for storing reference data.

As described above, the transistors TR11-TR
15 and a stack gate type transistor STR11, an analog arithmetic element stores reference data in the stack gate type transistor STR11 and gives input data to the transistor TR11, thereby obtaining a difference between the input data and the reference data. A current output according to the difference can be obtained.

2-3. Operation of Second Example of Analog Associative Memory Next, an operation of writing reference data to each of the analog arithmetic elements A11 to Amn of the analog associative memory shown in FIGS. 8 and 9 will be described.

Each of the analog operation elements A11 to Amn of the analog associative memory shown in FIGS. 8 and 9 is set to the erase mode before the reference data is written. In the erase mode, the reference lines RL1, RL
2,... Are supplied with a high erasing voltage Ve of about 20V.

When the high voltage Ve is supplied to the reference lines RL1, RL2,...
The voltage is applied to the control gate of the stack gate type transistor STR11 of the analog arithmetic elements A11 to Amn via N12. When the high voltage Ve for erasing is applied to the control gate of the stacked-gate transistor STR11, electrons are injected into the floating gate of the stacked-gate transistor STR11 from the substrate of the transistor, and the potential of the floating gate shifts to a negative potential.

At this time, input data lines SL1,
SL2,... Are set to 0 V and the select line SW
Are set to 0 V, and the transistor TR1
1 and TR14 are turned off.

Next, a write mode is set. In the write mode, the reference data lines RL1, R
L2,..., The analog operation elements A11 to A1n, A
-21 to A2n,..., To the control gates of the stacked gate transistors STR11 of Am1 to Amn,
A negative voltage of about 0 V is applied. And in that state,
A potential of about 6 V is applied to the drain diffusion layer of the stack gate type NMOS transistor STR11 by the write lines WL1, WL2,.

When such a bias voltage is applied, electrons in the floating gate of the stack gate type NMOS transistor STR11 are extracted to the drain diffusion layer, and the threshold voltage Vt of the stack gate type NMOS transistor STR11 decreases. .

At the time of writing, the write mode and the verify mode are alternately repeated to determine the write level. By such a verify operation,
The potential of the floating gate is accurately matched to a desired write level corresponding to reference data.

That is, in the verify mode, the analog potential Vr to be stored in the floating gate of the stacked gate type transistor STR11 is applied to the gate of the negative input transistor TR11 by the input data lines SL1, SL2,. The power supply voltage Vdd is applied to the control gate of the stacked gate transistor STR11 by the reference data lines RL1, RL2,. Write line WL
The power supply voltage Vdd is applied to the drain of the stack gate type transistor STR1 by 1, WL2,. The transistors TR14 in the selected column are turned on by the select lines SWL1, SWL2,. This allows
A differential amplifier circuit of the transistor TR11 and the stack gate type transistor STR11 is operated.

In this case, the gate of the negative side input transistor TR11 is connected to the stack gate type transistor S11.
Since the analog potential Vr to be stored is applied to the floating gate of TR11, (Vdd-Vt) becomes Vr.
, The stack gate type transistor ST
When the threshold voltage Vt of R11 is reached, the current capabilities of the transistor TR11 and the transistor TR15 become equal, and the output current becomes "0". If the threshold voltage Vt of the stack gate type transistor STR11 is higher than that, the output current becomes negative (captures current). When the threshold voltage Vt of the stack gate type transistor STR1 becomes lower than that, the output current becomes positive (outputs current).

In the first write to the floating gate of the stack gate type transistor STR1, the write is not sufficient and the threshold voltage Vt is high.
When the verify operation is performed, the output current becomes negative.

When the output current is negative during verification,
The mode is reset to the write mode, a write bias is applied, and writing to the floating gate of the stacked gate transistor STR11 is performed.

When the verify operation is performed in the next write operation, the write operation is not sufficient. If the output current is negative, the write mode is set again, a write bias is applied, and the stack gate type transistor STR is turned on.
Data is written to 11 floating gates.

Thereafter, similarly, a write bias is repeatedly applied, and verification is performed each time.

As the writing is repeated in this manner, the threshold voltage Vt of the stacked gate transistor STR11 decreases, and (Vdd-Vt) becomes Vr.
Reach Then, when the threshold voltage Vt of the stacked gate transistor STR11 decreases until (Vdd-Vt) becomes larger than Vr, the output current at the time of verification changes from negative to positive.

When the output current at the time of verification changes from negative to positive, the write is terminated on the assumption that the threshold voltage Vt of the stacked gate transistor STR11 has dropped to a point where (Vdd-Vt) becomes equal to Vr. .

As described above, if the verify is performed while repeating the writing, and the point at which the output current changes from negative to positive is detected and the writing is terminated, the gate voltage (Vdd-Vt) of the transistor TR15 can be referred to. It can be set substantially equal to the data potential Vr.

In this manner, the threshold voltage Vt of the stack gate type transistor STR1 is changed to (Vdd-V
After setting the voltage so that t) becomes equal to Vr, the operation mode can be set.

In the operation mode, the input data line SL
The analog potential Vi corresponding to the input data is applied to 1, SL2,. This potential Vi is applied to the gate of the negative-side input transistor TR11 via the terminal IN11. Also, the reference data line RL
The power supply voltage Vdd is supplied to 1, RL2,. This power supply voltage Vdd is applied to the control gate of the stack gate type transistor STR11 via the terminal IN12. The power supply voltage Vdd is supplied to the write lines WL1, WL2,. This power supply voltage Vdd is supplied to the terminal IN14.
Is applied to the drain of the stack gate type transistor 11 through Then, the select lines SWL1, SWL
The transistors TR4 in the column selected by WL2,.
Is turned on.

As described above, the threshold voltage Vt of the stacked gate transistor STR11 is (Vdd−
Vt) is set to be equal to Vr, so that the transistors TR11 and STR15
, The reference analog data Vr (= Vdd−Vt) and the input analog data Vi
And a current output corresponding to the difference between

2-4. Modification Example of Second Embodiment of Analog Associative Memory In the above example, one reference data is stored in each analog operation element included in the analog associative memory, but a plurality of reference data can be stored. You may do it. That is, in the example shown in FIG. 9, one transistor serving as the memory of the reference data is the stack gate type transistor STR11.
In the example shown in FIG. 1, 3 is a memory for reference data.
Stack gate type transistors STR11a, ST
R11b and STR11c are connected in parallel. As described above, when the three stacked gate transistors STR11a, STR11b, and STR11c are provided, it is possible to hold three reference data for one differential amplifier circuit. The reference data to be calculated can be selected at any time from the reference data lines RL1a, RL1b, RL1c,.

In this example, the configuration of the current-voltage conversion circuits CV1, CV2, CV3,... Can be the same as that of the first example.

As in the case of FIG. 7, two analog operation elements A11a to A1na and A11b to A1nb are set so that the polarity of one data is opposite to that of the other.
And the analog operation elements A11a to A11a to
Two current mirror circuits CM1 that operate only when a positive current is output for A1na and A11b to A1nb
By providing 1a to CM1na and CM11b to CM1nb, the sum of absolute values of the differences can be obtained. In this case, since it is not necessary to apply a bias voltage to the output terminal, the switch circuits Sa11 to Sa1n, S1 in FIG.
b11 to Sb1n are unnecessary, and may be configured as shown in FIG.

3. Third embodiment of analog associative memory 3-1. Overall Configuration of Third Embodiment of Analog Associative Memory FIG. 13 shows a third embodiment of an analog associative memory to which the present invention is applied. In FIG. 13, the same parts as those in the first and second embodiments are denoted by the same reference numerals.

In this example, the analog operation elements A11 to A11
mn is an NMOS transistor T as shown in FIG.
R21, TR22, TR23, TR24, TR25;
And a stack gate type NMOS transistor STR21.

That is, FIG. 14 shows the analog operation elements A11, A12,..., A21, A22,.
Is shown in detail. In the analog operation elements A11, A12,..., A21, A22,. A transistor TR24 for selecting an element is connected between the power supply line and a differential amplifier circuit including the transistor TR21 and the stack gate type transistor STR21. A current mirror circuit including a transistor TR22 and a transistor TR23 is connected between the ground and a differential amplifier circuit including the transistor TR21 and the stack gate transistor STR21. Also, the stack gate type transistor TR21
An electrode is extracted from the floating gate of the switching transistor TR2.
5 is connected to the gate of the transistor 21.

A terminal IN21 for inputting data is derived from the gate of the transistor TR21. A terminal IN22 for storing reference data is derived from the control gate of the stacked gate transistor STR21. A terminal OUT21 for obtaining a current output is derived from a connection point between the stack gate type transistor STR21 and the transistor TR23. A terminal IN23 for selecting an element is derived from the gate of the transistor TR24. Transistor 2
From the gate of 5, a terminal IN24 for turning on the transistor 25 at the time of writing is led out.

As shown in FIG.
11 to Amn are arranged in a (m × n) two-dimensional matrix. Analog arithmetic elements A11 to Am arranged in the row direction
Terminals IN21 derived from 1, A12 to Am2,..., A1n to Amn are connected to input data lines SL1 to SLn, respectively. Further, analog arithmetic elements A11 to Am1, A12 to Am2,..., A1n to Amn arranged in the row direction
Are connected to the reference data lines RL1 to RLn, respectively.

Analog arithmetic elements A11-A arranged in column direction
Terminals OUT21 derived from 1n, A21 to A2n,..., Am1 to Amn are connected to the data lines DL1 to DLm, respectively. Further, the analog arithmetic elements A11 to A1n, A21 to A2n,.
Is derived from the select line SWL
1 to SWLm. Further, the analog operation elements A11 to An, A21 to A2n,.
Terminals IN24 derived from m1 to Amn are connected to switch lines CL1 to CLm, respectively.

At the ends of the data lines DL1 to DLm,
The current-voltage conversion circuits CV1, CV2,..., CVm are respectively connected. Analog operation elements A11 to A1n, A arranged in the column direction by current-voltage conversion circuits CV1 to CVm.
, Am1 to Amn are respectively added and converted into voltage outputs.

Outputs of the current-voltage conversion circuits CV1 to CVm are supplied to the WTA circuit 1. WTA circuit 1 output is P
It is supplied to the Q circuit 2. The output of the PQ circuit 2 is supplied to the ROM circuit 3. The output of the ROM 3 is output from the output terminal 4.

In the analog associative memory shown in FIG. 13, when signal processing such as image feature extraction and motion vector detection is performed, reference data of analog values form vectors (DRm1, DRm2,..., DRmn). And each of the analog operation elements A11 to A1n, A21 to A21
A2n,..., Am1 to Amn.

Reference data is stored in each of the analog operation elements A11 to A1n, A21 to A2n,.
Is stored in the input signal vector (DI1, DI2,
.. DIm) are supplied for each column through the input data lines SL1 to SLn.

When performing signal processing such as image feature extraction and motion vector detection, the analog arithmetic elements A11 to A1n, A21 to A2n,.
Amn, input data (DI1, DI2, ..., DIn)
, And reference data (DRm1, DRm2,..., D
Rmn). The analog operation elements A11 to A1n, A21 to A2n,.
The difference value between the input data of Amn and the reference data is added, and the sum of the difference values is used as the current-voltage conversion circuit C
V1, CV2,..., CVm.

The current-voltage conversion circuits CV1, CV2,.
The output of CVm is supplied to the WTA circuit 1, the PQ circuit 2, and the ROM circuit 3, and the address at which the sum of the absolute values of the differences between the input data and the reference data is minimized is obtained. From the address where the sum of absolute values of the difference between the input data and the reference data is the smallest, detection of a motion vector and extraction of image features are performed.

3-2. Third Example of Analog Arithmetic Element As described above, in the analog associative memory shown in FIGS. 13 and 14, the analog arithmetic elements A11 to Amn including the transistors TR21 to TR25 and the stack gate type transistor STR21 are arranged in a matrix. It is arranged in a shape. The difference between the input data and the reference data is obtained by these analog operation elements A11 to Amn. Image feature extraction and motion vector calculation are performed from the sum of the differences between the input data and the reference data thus obtained.

As described above, the analog operation elements A11 to Amn for obtaining the difference between the input data and the reference data
Will be described in more detail.

FIG. 15 shows a third example of the analog operation element. As shown in FIG. 15, the analog operation element has a configuration in which the positive side transistor of the differential amplifier circuit is replaced by a stack gate type transistor STR21, and the analog operation element has a floating gate of the stack gate type transistor STR21. By taking out the electrode, the potential of the floating gate can be set. The stack gate type transistor STR2 forming the positive side of the differential amplifier circuit
1 and the transistor TR21 forming the negative side of the differential amplifier circuit have the same channel width.

Stack gate type transistor STR21
And the transistor TR21, the gate potential Vi of the transistor TR21 on the negative side and the stack gate type transistor STR21
Is equal to the floating gate potential Vf of
The current capability of the transistor TR21 and the current capability of the stack gate type transistor STR21 become equal, and the current output of the differential amplifier circuit becomes “0”. Therefore, the floating gate potential Vf of the stack gate transistor STR21 and the gate potential Vf of the transistor TR21
A current output Iout corresponding to the difference (Vf-Vi) from i can be obtained from the node Nout.

For example, the stack gate type transistor S
If the current injection amount is controlled so that the floating gate potential Vf when the power supply voltage Vdd is applied to the control gate of the TR21 corresponds to the reference data Vr, the stack gate transistor STR21 functions as an analog memory for storing the reference data. Become like

As described above, the transistors TR21 to TR21
25 and a stack gate type transistor STR21, an analog operation element stores reference data in the stack gate type transistor STR21 and gives input data to the transistor TR21, thereby obtaining a difference between the input data and the reference data. A current output according to the difference can be obtained.

3-3. Operation of Third Example of Analog Associative Memory Next, an operation of writing reference data to each of the analog arithmetic elements A11 to Amn of the analog associative memory shown in FIGS. 13 and 14 will be described.

When writing reference data to each of the analog arithmetic elements A11 to Amn of the analog associative memory, a voltage Vr corresponding to the write data is supplied to the data lines SL1, SL2,. The voltage Vr corresponding to the write data is supplied to the negative side NMOS transistor TR of the differential amplifier circuit via the terminal IN21.
21 is applied to the gate. At this time, the power supply voltage Vdd is supplied to the reference lines RL1, RL2,. This power supply voltage Vdd is applied to the control gate of the stack gate type transistor STR21 via the terminal IN22. Then, the switch line CL1,
The power supply voltage Vdd is supplied to CL2,..., And the switching transistor TR25 is turned on.

When the switching transistor TR25 is turned on, the gate of the transistor TR21 and the floating gate of the stack gate type transistor STR21 are connected via the wiring L21. Thus, the potential Vr is similarly applied to the gate of the transistor TR21 and the floating gate of the stack gate type transistor STR21.

Stack gate type transistor STR21
Of the stack gate type transistor STR from the transistor substrate by the voltage applied to the control gate of
Electrons are taken in and out of the floating gate 21 and the potential of the floating gate shifts.

Thereafter, the switching transistor TR2
5 is turned off. When the switching transistor TR25 is turned off, the floating gate of the stack gate type NMOS transistor STR21 becomes floating. At this time, the stack gate type transistor STR
The floating gate 21 has the potential Vr at the time of the reference data. Therefore, the verify operation is unnecessary.

When the potential corresponding to the potential Vr of the reference data is written to the potential of the floating gate of the stacked gate transistor STR21 in this manner, the operation mode can be set.

In the calculation mode, the switch lines CL1,
CL2,... Are set to 0 V, and the switching transistor T
R25 is turned off. Input data lines SL1, SL
2, an analog potential Vi corresponding to the input data is applied. This potential Vi is applied to the gate of the negative-side input transistor TR21 via the terminal IN21. Also, reference data lines RL1, RL
The power supply voltage Vdd is supplied to 2,. This power supply voltage V
dd is applied to the control gate of the stacked gate transistor STR21 via the terminal IN22.
Then, the transistors TR24 in the selected column are turned on by the select lines SWL1, SWL2,.

As described above, the analog potential Vr serving as reference data when the voltage Vdd is applied to the control gate is stored in the floating gate of the stacked gate transistor STR21. Therefore, a current output corresponding to the difference between the potential Vr of the reference data and the potential Vi of the input data is obtained by the differential amplifier circuit including the transistor TR21 and the stack gate transistor STR21.

As described above, in this example, since the electrode is derived from the floating gate of the stack gate type transistor STR21, writing and verifying are not repeated, and the stack gate type transistor STR2 is not repeated.
There is an advantage that the analog potential Vr corresponding to the reference data can be stored in one floating gate.

However, in this example, since the floating gate of the stacked gate type NMOS transistor STR21 is connected to the diffusion layer of the transistor TR25 via the wiring L21, the charge cannot be held for a long time. Electric charges are discharged in a few milliseconds. Therefore, in this example, after writing the reference data, it is necessary to perform the arithmetic operation within a time that guarantees a discharge within an allowable range in terms of data accuracy.

3-4. Modified Example of Third Embodiment of Analog Associative Memory In the above-described example, one reference data is stored in each analog operation element included in the analog associative memory, but a plurality of reference data can be stored. You may do it. That is, in the example shown in FIG. 14, one transistor serving as the memory for the reference data is the stack gate type transistor STR21. However, in the example shown in FIG. 16, three stack gate type transistors STR21a serving as the memory for the reference data are used. S
TR21b, STR21c are connected in parallel, and stack gate type transistors STR21a, STR21b, ST
Three switching transistors TR25a, TR25 between each of R21c and the gate of transistor TR21.
25b and TR25c are provided. Thus, three stack gate transistors STR21a, STR21b, STR2 are provided for one differential amplifier circuit.
When 1c is provided, one differential amplifier circuit can hold three reference data.

The configuration of the current-voltage conversion circuits CV1, CV2, CV3,... In this example can be the same as that shown in the first and second examples.

As in the case of FIG. 7, two analog operation elements A11a to A1na and A11b to A1nb are set so that the polarity of one data is opposite to that of the other data.
And the analog operation elements A11a to A11a to
Two current mirror circuits CM1 that operate only when a positive current is output for A1na and A11b to A1nb
By providing 1a to CM1na and CM11b to CM1nb, the sum of absolute values of the differences can be obtained. In this case, in this example, there is no need to apply a bias voltage to the output terminal, so that the switch circuits Sa11 to Sa11 in FIG.
Sa1n and Sb11 to Sb1n are unnecessary, and may be configured as shown in FIG. 12 as in the above-described second embodiment.

[0164] 4. APPLICATION EXAMPLES As described above, in the analog associative memory to which the present invention is applied, an analog value can be directly calculated to perform image processing. Such an analog associative memory may be mounted on an image sensor.

That is, FIG. 17 shows a configuration of one pixel of the MOS image sensor. In the MOS image sensor, one pixel includes a photodiode PD1 and a MOS transistor Q1. MO like this
When an analog associative memory is mounted on the S image sensor, as shown in FIG. 17, the analog operation element A1 is provided so that the photoelectric conversion signal of the photodiode PD1 is directly input to the analog operation element A1.

By arranging the analog operation element A1 in this way, a differential amplifier circuit is inserted for each pixel, and the data line DL also serves as a signal line of the MOS image sensor. Is also possible.

In the above example, the analog operation element is constituted by the NMOS differential amplifier circuit.
The analog operation element may be configured by a differential amplifier circuit having a MOS configuration.

There are other methods for injecting charges into the floating gate of the stacked gate transistor, such as channel injection and hot electron injection. These methods are used to apply the method to the floating gate of the stacked gate transistor. Charges may be injected.

[0169]

According to the present invention, an analog storage element is provided on one side of a differential amplifier circuit having a current mirror type load circuit, and a value corresponding to reference analog data is stored in the analog storage element. A value corresponding to the input analog data is given to the other input of the dynamic amplifier circuit, and the differential amplifier circuit outputs a value corresponding to the difference between the value corresponding to the reference analog data and the value corresponding to the input analog data. An analog associative memory is formed by arranging such analog arithmetic elements in a matrix. When such an analog content addressable memory is used, the absolute value sum of the difference between the reference data and the input data can be obtained with a simple configuration, with high accuracy, and at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a first embodiment of an analog associative memory to which the present invention is applied.

FIG. 2 is a connection diagram showing an overall configuration of a first embodiment of an analog associative memory to which the present invention is applied;

FIG. 3 is a connection diagram illustrating a first example of an analog operation element.

FIG. 4 is a cross-sectional view illustrating a configuration of a stacked gate transistor.

FIG. 5 is a block diagram showing a modification of the first embodiment of the analog associative memory to which the present invention is applied;

FIG. 6 is a block diagram illustrating an example of a current-voltage conversion circuit according to the first embodiment of the analog associative memory to which the present invention is applied;

FIG. 7 is a connection diagram of an example of a circuit for obtaining a sum of absolute values of a difference;

FIG. 8 is a block diagram showing an overall configuration of a second embodiment of the analog content addressable memory to which the present invention is applied.

FIG. 9 is a connection diagram showing an overall configuration of a second embodiment of the analog content addressable memory to which the present invention is applied.

FIG. 10 is a connection diagram illustrating a second example of the analog operation element.

FIG. 11 is a block diagram showing a modification of the second embodiment of the analog content addressable memory to which the present invention is applied.

FIG. 12 is a connection diagram of another example of a circuit for calculating the absolute value sum of the difference.

FIG. 13 is a block diagram showing an overall configuration of a third embodiment of an analog content addressable memory to which the present invention is applied.

FIG. 14 is a connection diagram showing an entire configuration of a third embodiment of an analog content addressable memory to which the present invention is applied.

FIG. 15 is a connection diagram illustrating a third example of the analog operation element.

FIG. 16 is a block diagram showing a modification of the third embodiment of the analog content addressable memory to which the present invention is applied.

FIG. 17 is a connection diagram showing an example in which the present invention is applied to a solid-state imaging device.

FIG. 18 is a connection diagram used for describing an example of a conventional analog associative memory.

FIG. 19 is a cross-sectional view used to explain an example of a conventional analog associative memory.

FIG. 20 is a graph used to explain an example of a conventional analog associative memory.

FIG. 21 is a connection diagram of an example of a conventional analog associative memory.

[Explanation of symbols]

A11 to Amn: analog operation element, STR1, S
TR11, STR21 ... Stack gate type NMOS
Transistors, TR1 to TR4, TR11 to TR15,
TR21 to TR25 ... NMOS transistors

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/8247 H01L 27/10 434 29/788 29/78 371 29/792 H03F 3/45 F term (reference) 5F001 AA25 AB08 AC02 AC06 AD03 AH01 5F083 EP02 EP23 ER02 ER03 ER09 ER14 ER16 ER30 GA01 GA30 LA03 LA10 5J066 AA01 AA12 CA18 CA88 FA09 HA10 HA19 HA25 HA29 HA38 HA44 KA00 KA01 KA02 KA09 KA01 KA02 KA02

Claims (32)

[Claims] 1. An analog associative memory in which analog arithmetic elements for obtaining a difference between first analog data and second analog data are arranged in a matrix, wherein the analog arithmetic element is a current mirror type load circuit. An analog storage element is provided in one of the differential amplifier circuits having the following. A value corresponding to the second analog data is stored in the analog storage element, and the other input of the differential amplifier circuit is A value corresponding to the first analog data is provided, and the differential amplifier circuit outputs a value corresponding to a difference between the value corresponding to the second analog data and the value corresponding to the first analog data. Analog associative memory. 2. The analog associative memory according to claim 1, wherein said first analog data is input analog data, and said second analog data is reference analog data. 3. An analog storage element is provided on one side of a differential amplifier circuit having a current mirror type load circuit, and a value corresponding to the second analog data is stored in the analog storage element. A value corresponding to the first analog data is given to the other input of the differential amplifier, and the differential amplifier circuit corresponds to the difference between the value corresponding to the second analog data and the value corresponding to the first analog data. An analog operation element that outputs a value. 4. The analog operation element according to claim 3, wherein said first analog data is input analog data, and said second analog data is reference analog data. 5. An analog associative memory in which analog arithmetic elements for obtaining a difference between first analog data and second analog data are arranged in a matrix, wherein the analog arithmetic elements are a MOS transistor and a stack gate type. A differential amplifier circuit comprising a MOS transistor, and the first MOS transistor and a stack gate type MO.
A current mirror type load circuit connected between a differential amplifier circuit including an S transistor and a reference potential; a first input terminal derived from a gate of the MOS transistor; a control gate of the stack gate type MOS transistor And an output terminal derived from a connection point between the current mirror type load circuit and the stack gate type MOS transistor, and a floating gate potential of the stack gate type MOS transistor. Setting a predetermined potential to the value of the second analog data when the predetermined potential is applied to the control gate; applying a value corresponding to the first analog data to the first input terminal; The predetermined potential is applied to a second input terminal, and the second analog data is applied from the output terminal. Analog Associative memory so as to output a current corresponding to the data value and the first analog data value and the difference. 6. The analog associative memory according to claim 5, wherein said first analog data is input analog data, and said second analog data is reference analog data. 7. The analog associative memory according to claim 5, further comprising a current-voltage conversion circuit for adding output currents of the analog operation elements arranged in the same column direction and converting the output current into a voltage. 8. A first analog operation element for subtracting input analog data from reference analog data for one operation element, a second analog operation element for subtracting reference analog data from input analog data, A first and a second current mirror circuit provided for each of the first and second analog operation elements and outputting a current corresponding to the output current of the first and second analog operation elements only in one direction; 6. The analog associative memory according to claim 5, further comprising: a current-voltage conversion circuit for adding an output current of said first or second current mirror circuit arranged in the same column direction and converting the output current into a voltage. 9. A write potential is applied to the control gate of the stack gate type MOS transistor via the second input terminal, and a bias potential is applied to a source diffusion layer of the stack gate type transistor via the output terminal. The write operation is performed intermittently, and while the write operation is performed intermittently, the value of reference analog data is applied to the gate of the MOS transistor via the first input terminal, and the second input terminal The predetermined potential is applied to the control gate of the stack gate type MOS transistor via the above, and the current of the output terminal is detected, and the floating gate potential of the stack gate type MOS transistor sets the predetermined potential to the control gate. When applied, it corresponds to the second analog data. Analog associative memory according to claim 5 which is adapted to verify whether it is a value. 10. The analog content addressable memory according to claim 5, wherein a plurality of stack gate MOS transistors are connected in parallel to said stack gate MOS transistor. 11. A differential amplifier circuit comprising a MOS transistor and a stack gate type MOS transistor; and a first MOS transistor and a stack gate type MO transistor.
A current mirror type load circuit connected between a differential amplifier circuit including an S transistor and a reference potential; a first input terminal derived from a gate of the MOS transistor; a control gate of the stack gate type MOS transistor And an output terminal derived from a connection point between the current mirror type load circuit and the stack gate type MOS transistor, and a floating gate potential of the stack gate type MOS transistor. Setting a predetermined potential to the value of the second analog data when applied to the control gate; applying a value corresponding to the first analog data to the first input terminal; And applying the predetermined potential to the input terminal of the second analog data from the output terminal. Analog computation device so as to output a current corresponding to the value in the first analog data value and the difference. 12. The analog operation element according to claim 11, wherein said first analog data is input analog data, and said second analog data is reference analog data. 13. A write potential is applied to the control gate of the stack gate type MOS transistor via the second input terminal, and a bias potential is applied to the source diffusion layer of the stack gate type transistor via the output terminal. The write operation is performed intermittently, and while the write operation is performed intermittently, the value of reference analog data is applied to the gate of the MOS transistor via the first input terminal, and the second input terminal The predetermined potential is applied to the control gate of the stack gate type MOS transistor via the above, and the current of the output terminal is detected, and the floating gate potential of the stack gate type MOS transistor sets the predetermined potential to the control gate. Equivalent to the above second analog data when applied Analog computation device according to claim 11 which is as to verify whether or not it is that value. 14. The analog operation element according to claim 11, wherein a plurality of stack gate MOS transistors are connected in parallel to said stack gate MOS transistor. 15. An analog associative memory in which analog arithmetic elements for obtaining a difference between first analog data and second analog data are arranged in a matrix, wherein the analog arithmetic elements are a first MOS transistor and a first MOS transistor. A differential amplifier circuit including a second MOS transistor; a current mirror type load circuit connected between a differential amplifier circuit including the first MOS transistor and the second MOS transistor and a reference potential; A stack gate MOS transistor forming a source follower circuit for the gate of the second MOS transistor; a first input terminal derived from the gate of the first MOS transistor; a control gate of the stack gate MOS transistor A second input terminal derived from A third input terminal derived from the drain of the gated MOS transistor; and an output terminal derived from a connection point between the current mirror type load circuit and the second MOS transistor. A threshold voltage of the transistor is set so as to be a value of the second analog data when a predetermined potential is applied to the control gate, and a value corresponding to the first analog data is input to the first input terminal. Is applied, the predetermined potential is applied to the second input terminal, and a current corresponding to a difference between the value of the second analog data and the value of the first analog data is output from the output terminal. Analog associative memory. 16. The analog associative memory according to claim 15, wherein said first analog data is input analog data, and said second analog data is reference analog data. 17. The analog associative memory according to claim 15, further comprising a current-voltage conversion circuit for adding output currents of the analog operation elements arranged in the same column direction and converting the output current into a voltage. 18. A first operation for subtracting input analog data from reference analog data for one operation element.
, An analog operation element for subtracting reference analog data from input analog data, and a first analog operation element provided for each of the first and second analog operation elements. The first and second current mirror circuits that output currents according to the output current of the second analog operation element, and the output currents of the first or second current mirror circuits arranged in the same column direction are added. The analog associative memory according to claim 15, further comprising a current-voltage conversion circuit that converts the voltage into a voltage. 19. A write potential is applied to the control gate of the stacked gate MOS transistor via the second input terminal, and a bias is applied to the drain diffusion layer of the stacked gate transistor via the third input terminal. Writing is performed intermittently by applying a potential. While the writing is performed intermittently, the value of reference analog data is applied to the gate of the first MOS transistor via the first input terminal. The predetermined potential is applied to the gate of the second MOS transistor through the source follower of the first stacked gate MOS transistor, and the current at the output terminal is detected. When a predetermined potential is applied to the control gate, Analog associative memory according to claim 15 which is adapted to verify whether it is a value corresponding to the Reference analog data. 20. The analog content addressable memory according to claim 15, wherein a plurality of stack gate MOS transistors are connected in parallel to said stack gate MOS transistor. 21. A first MOS transistor and a second MOS transistor
A differential amplifier circuit including an OS transistor; a current mirror type load circuit connected between a differential amplifier circuit including the first MOS transistor and the second MOS transistor and a reference potential; A stack gate type MOS transistor forming a source follower circuit for the gate of the MOS transistor, a first input terminal derived from the gate of the first MOS transistor, and a control gate of the stack gate type MOS transistor A second input terminal, a third input terminal derived from the drain of the stack gate type MOS transistor, and an output derived from a connection point between the current mirror type load circuit and the second MOS transistor. And the above-mentioned stack gate type MOS transistor The threshold voltage of the first input terminal is set so as to become the value of the second analog data when a predetermined potential is applied to the control gate, and the value corresponding to the first analog data is input to the first input terminal. Applying the predetermined potential to the second input terminal, and outputting a current corresponding to a difference between the value of the second analog data and the value of the first analog data from the output terminal. Analog computing element. 22. The analog operation element according to claim 21, wherein the first analog data is input analog data, and the second analog data is reference analog data. 23. A write potential is applied to the control gate of the stack gate type MOS transistor via the second input terminal, and a bias is applied to the drain diffusion layer of the stack gate type transistor via the third input terminal. Writing is performed intermittently by applying a potential. While the writing is performed intermittently, the value of reference analog data is applied to the gate of the first MOS transistor via the first input terminal. The predetermined potential is applied to the gate of the second MOS transistor through the source follower of the first stacked gate MOS transistor, and the current at the output terminal is detected. When a predetermined potential is applied to the control gate, Analog computation device according to claim 21 which is adapted to verify whether it is a value corresponding to the Reference analog data. 24. The analog operation element according to claim 21, wherein a plurality of stack gate MOS transistors are connected in parallel to said stack gate MOS transistor. 25. An analog associative memory in which analog arithmetic elements for obtaining a difference between first analog data and second analog data are arranged in a matrix, wherein the analog arithmetic elements are a MOS transistor and a stack gate type. A differential amplifier circuit comprising a MOS transistor, and the first MOS transistor and a stack gate type MO.
A current mirror type load circuit connected between a differential amplifier circuit including an S transistor and a reference potential; a switching transistor provided between a floating gate of the stack gate type MOS transistor and the MOS transistor; A first input terminal derived from the gate of the MOS transistor, a second input terminal derived from the control gate of the stack gate type MOS transistor, the current mirror type load circuit and the stack gate type MOS transistor. An output terminal derived from a connection point of the second analog data when the floating gate potential of the stack gate type MOS transistor is applied to the control gate via the switching transistor. The first input terminal is applied with a value corresponding to the first analog data, the second input terminal is applied with the predetermined potential, and the output terminal is connected to the second terminal. An analog content addressable memory configured to output a current corresponding to a difference between the value of the second analog data and the value of the first analog data. 26. The analog associative memory according to claim 25, wherein said first analog data is input analog data, and said second analog data is reference analog data. 27. The analog content addressable memory according to claim 25, further comprising a current-voltage conversion circuit for adding output currents of said analog arithmetic elements arranged in the same column direction and converting the output current into a voltage. 28. A first method for subtracting input analog data from reference analog data for one operation element.
, An analog operation element for subtracting reference analog data from input analog data, and a first analog operation element provided for each of the first and second analog operation elements. The first and second current mirror circuits that output currents according to the output current of the second analog operation element, and the output currents of the first or second current mirror circuits arranged in the same column direction are added. 26. The analog associative memory according to claim 25, further comprising a current-voltage conversion circuit that converts the voltage into a voltage. 29. The analog associative memory according to claim 25, wherein a plurality of stack gate type MOS transistors are connected in parallel to said stack gate type MOS transistor. 30. A differential amplifier circuit comprising a MOS transistor and a stack gate type MOS transistor; and a first MOS transistor and a stack gate type MOS transistor.
A current mirror type load circuit connected between a differential amplifier circuit including an S transistor and a reference potential; a switching transistor provided between a floating gate of the stack gate type MOS transistor and the MOS transistor; A first input terminal derived from the gate of the MOS transistor, a second input terminal derived from the control gate of the stack gate type MOS transistor, the current mirror type load circuit and the stack gate type MOS transistor. And an output terminal derived from the connection point of the above. The floating gate potential of the stack gate type MOS transistor is changed to the value of the second analog data when a predetermined potential is applied to the control gate via the switching transistor. What The first input terminal is applied with a value corresponding to the first analog data, the second input terminal is applied with the predetermined potential, and the output terminal is connected to the second input terminal. An analog operation element configured to output a current corresponding to a difference between the value of the analog data and the value of the first analog data. 31. The analog operation element according to claim 30, wherein the first analog data is input analog data, and the second analog data is reference analog data. 32. The analog operation element according to claim 30, wherein a plurality of stack gate MOS transistors are connected in parallel to said stack gate MOS transistor.