JP2000295304A - Demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulator equipped with AGC capable of controlling the amplitude of a signal into prescribed value regardless of C/N at the output point of an intermediate frequency(IF) amplifier circuit by providing a feedback control loop for controlling the gain of the IF amplifier circuit. SOLUTION: An AGC loop is provided with an IF amplifier circuit 1, multipliers 5 and 6, low-pass filters(LPF) 7 and 8, A/D 9 and 10, a power detector(PWR) 17, a comparator(COMP) 18, an LPF 19 and a D/A 20. The output (digital number) of the PWR 17 becomes one input of the COMP 18 and is compared with a reference value ref as the other input of the COMP 18 and the compared result is outputted. The output of the COMP 18 is integrated by the LPF 19 and converted to an analog voltage by the D/A 20 and feedback control is performed to the gain of the IF amplifier circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for demodulating a signal which has been subjected to quadrature modulation in a digital radio communication system, and more particularly to an AGC in a demodulator.
(Automatic gain control) circuit.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional configuration of such a demodulator. Hereinafter, the configuration and operation of the conventional demodulator will be described with reference to FIG. A radio frequency signal that has been subjected to quadrature modulation and received by an antenna (not shown) is converted by a frequency conversion circuit (not shown)
The signal is converted into an intermediate frequency signal, and becomes a signal indicated as IF IN in FIG.
Since the part where the amplification gain for the received signal is the largest is the intermediate frequency amplifier circuit 201, the gain of the intermediate frequency amplifier circuit 201 is generally controlled in AGC. In the device shown in FIG. 2, the detector 20 is connected to the output point of the intermediate frequency amplification circuit 201.
2, a DC voltage proportional to the amplitude of the intermediate frequency signal output from the intermediate frequency amplification circuit 201 is generated, and the gain of the intermediate frequency amplification circuit 201 is negatively feedback-controlled by the DC voltage.

In the example shown in FIG. 2, a quasi-coherent detection system is used. That is, in the multipliers 205 and 206, synchronous detection is performed by multiplying the output of the intermediate frequency amplifier circuit 201 and the output of the local oscillator 203. In this case, the output frequency of the intermediate frequency amplifier circuit 201 and the output of the local oscillator 203 are output. Since the frequencies do not exactly match, the outputs of the multipliers 205 and 206 do not become DC components, and the phase rotation of the frequency difference between the output frequency of the intermediate frequency amplifier circuit 201 and the output frequency of the local oscillator 203 remains. become.

The output signal S of the intermediate frequency amplification circuit 201 is
_{S = Icosω 0 t + Qsinω 0} t ··· (1)
(Where I represents an in-phase signal component, Q represents a quadrature signal component, and in the case of a quadrature modulation method, I and Q are +1
Or -1), whereas the local oscillator 20
3 is L = cos ω ₁ t (2)
And the output R of the π / 2 transporter 204 is R
= Sin ω ₁ t (3)
Therefore, the output I _D of the multiplier 205 is I _D = I cos ω _{0
tcosω 1 t + Qsinω 0 tcosω 1} t ···
The output QD of the multiplier 206 can be expressed by (4).
Is Q _D = I cos ω ₀ t sin ω ₁ t + Q sin ω ₀
t sin ω ₁ t (5)

Cos ω ₀ t cos ω ₁ t, sin ω ₀ t
_{cosω 1 t, cosω 0 tsinω 1} t, sinω 0
tsin ω ₁ t includes a sum frequency (ω ₀ + ω ₁ ) component and a difference frequency (ω ₀ −ω ₁ ) component, but the sum frequency component is removed by the low-pass filters 207 and 208.
The output I _A of the low-pass filter 207 is given by
_A = (I / 2) cos θ + (Q / 2) sin θ
(6) and the output QA of the low-pass filter 208 from equation _{(4), Q A = (} Q / 2) cosθ- (I / 2)
sin θ (7)

Here, θ = (ω ₀ −ω ₁ ) t...
(8) represents the phase delay of L (Equation (2)) with respect to S (Equation (1)). If the phase is synchronized, θ = 0, and from Equations (6) and (7), I _A = I / 2 (9),
Q _A = Q / 2 (10) is obtained. Equation (6), I _A of the formula (7), Q _A is the formula (9), I _A of the formula (10), that remain phase rotation by θ relative to Q _A . Outputs of the low-pass filters 207 and 208 are analog-to-digital converters (A / D) 2
The signals are converted into digital signals by 09 and 210 and input to the complex multiplier 211.

The complex multiplier 211, AGC 212,
AGC 213, error detector 214, loop filter (L
PF) 215, NCO (Numerically Control)
The circuit of the lledOscillator (numerically controlled oscillator) 216 receives the signals (signals with the remaining phase rotation) shown in Expressions (6) and (7) and performs phase rotation by the complex multiplier 211 by rotationally symmetric conversion. , And the I-channel output (Ich OUT) and the Q-channel output (Qch
OUT) and an NCO
In step 216, cos θ + jsin θ (11) is generated, and the output of the A / D 209 and the output of the A / D 210 are calculated as I
_A + jQ _A ... (12), and performing complex multiplication of equation (11) and equation (12) gives [｛(I / 2) cos θ
+ (Q / 2) sin θ｝ + j ｛(Q / 2) cos θ−
(I / 2) sin θ｝] (cos θ + j sin θ) =
(I / 2) + j (Q / 2) (13), and I / 2 can be obtained as a real component of the output of the complex multiplier 211 and Q / 2 can be obtained as an imaginary component.

Since θ changes with time t as shown in equation (8), to perform the rotationally symmetric transformation shown in equation (13), an error signal is detected and a negative value is set so that the error signal becomes zero. Perform feedback control. That is, Ich OUT and Q
From the ch OUT, the error detector 214 detects the amplitude error of the Ich OUT and the amplitude error of the Qch OUT.
) And a phase error (represented by Pd) are calculated, the AGC 212 and the AGC 213 are negatively feedback-controlled by the amplitude error, the phase error is smoothed by the LPF 215, and the value of θ in Expression (11) is negatively feedback-controlled. . By the negative feedback control described above, θ in equation (11) changes following the change in θ in equations (6) and (7), and Ich OUT and Qch OU
T is as shown in Expression (13).

[0009]

Although the structure and operation of the conventional demodulator are as described above, there is a problem in the AGC part. FIG. 4 shows normal signal points (indicated by black circles)
FIG. 7 is a schematic diagram showing the relationship between the signal points (indicated by white circles) in the case of using the conventional AGC on a complex plane, wherein both the black and white circles indicate the signal amplitudes at the input points of A / D 209 and AD 210. The black circles are the output points of A / D 209 and AD 210, read counterclockwise from the upper right point, and (I = + 1, Q = + j),
(I = -1, Q = + j), (I = -1, Q = -j),
Although the digital encoding is accurately performed as (I = + 1, Q = −j), in the case of a white circle, the digital encoding is performed to a value smaller than (+1, + j).

The reason why the signal amplitudes at the input points of the A / D 209 and the AD 210 become like the white circles in FIG. 4 is due to the detector 202 which supplies the control input of the AGC. Since the detector 202 outputs a DC voltage proportional to the peak value of the output amplitude of the intermediate frequency amplification circuit 201, the detector 202 is controlled so that the peak value of the output amplitude of the intermediate frequency amplification circuit 201 becomes a constant value. C /
For a signal whose N (carrier-to-noise power ratio) is equal to or greater than a predetermined value, the ratio of the output amplitude peak value of the intermediate frequency amplification circuit 201 to the signal amplitude (referred to as peak factor).
Is kept almost constant, but this ratio increases as the C / N degrades.

In a digital radio communication system, various types of fading often occur during radio wave propagation. For example, when an electromagnetic wave is reflected on a conductor surface, the reflectivity is approximately 1 and the phase delay of the reflected wave is approximately 180 °, so that the propagation distance difference between the reflected wave and the direct wave is small (compared to the wavelength of the electromagnetic wave). At that location, the intensity of the composite electromagnetic wave, that is, the intensity C of the received carrier is significantly reduced. In order to obtain a predetermined signal power at the output point of the intermediate frequency amplifying circuit 201 in a state where C is significantly reduced, it is necessary to increase the gain of the intermediate frequency amplifying circuit 201, and white noise is also amplified. The noise power at the output point 201 increases. FIG. 5 is a diagram showing the relationship between the noise power and the peak factor at the output point of the intermediate frequency amplification circuit 201.

On the other hand, as shown in FIG.
The input range a of 10 is set with a margin for the A / D input peak power c. When C / N is normal,
If the output numerical value of A / D is set to 1 with respect to the value of 1 of the AD input signal power b, the peak value of the output of the intermediate frequency amplifier circuit 201 becomes constant when the C / N deteriorates. A / D input signal power b is C / N
Is lower than the value 1 when the signal is normal, and a signal point indicated by a white circle in FIG. 4 becomes an A / D output signal. Conversely, if the output value of the A / D is set to 1 with respect to the value of the AD input signal power b at the maximum point of the variation ΔP of the peak factor shown in FIG. 5, the C / N becomes normal. In this state, the output numerical value of the A / D becomes 1 or more, and there is a problem that the A / D is saturated. An object of the present invention is to solve the above-described problem in the conventional demodulation circuit, and to provide a demodulation provided with an AGC capable of controlling the signal amplitude to a predetermined value regardless of the C / N at the output point of the intermediate frequency amplification circuit 201. It is to provide a device.

[0013]

According to the demodulation device of the present invention, A
An AGC circuit for putting / D209 and A / D210 in an AGC loop was constructed. The output of A / D 209 is given by I _A = (I / 2) cos θ + (Q
/ 2) sin θ, and the output of the A / D 210 is Q _A = (Q / 2) cos θ− (I
/ 2) sin θ, the signal power P becomes P = (I _A ) ² + (Q _A ) ² = (1/4) (I ² + Q ² ) (14), which is irrelevant to θ Numeric value. In the present invention, the formula (1)
Negative feedback control is performed so that the value of P shown in 4) becomes a predetermined value. Accordingly, the value of P, that is, the values of I and Q are controlled regardless of the C / N of the output of the intermediate frequency amplification circuit 201.

That is, the digital demodulation device of the present invention amplifies an intermediate frequency signal generated by frequency-converting a received wave that has been modulated by the quadrature modulation method, and connects an AGC control signal input terminal for controlling the amplification gain. An intermediate frequency amplifier circuit, a local oscillator that generates a carrier signal phase-locked to the phase of the intermediate frequency signal, or a carrier signal having a frequency close to the center frequency of the intermediate frequency signal; , A first multiplier for multiplying the output of the intermediate frequency amplifier by the output of the local oscillator, and a second multiplier for multiplying the output of the intermediate frequency amplifier by the output of the phase shifter. , The first for extracting only low frequency components from the output of the first multiplier
, A second low-pass filter that extracts only low-frequency components from the output of the second multiplier, a first A / D that converts the output of the first low-pass filter into a digital signal, and a second A second A / D for converting the output of the low-pass filter into a digital signal, a power detector for calculating the power of the signal from the output of the first A / D and the output of the second A / D, and the power detector And a feedback control loop for controlling the gain of the intermediate frequency amplifier circuit so that the output of the intermediate frequency amplifier becomes a predetermined value.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
The parts denoted by reference numerals 15 and 16 are respectively denoted by reference numerals 201 and 201 in FIG.
203, 204, 205, 206, 207, 208, 2
09, 210, 211, 212, 213, 214, 21
5 and 216, and corresponds to the intermediate frequency amplifier circuit 1,
A local oscillator 3, a transporter 4, a first multiplier 5, a second multiplier 6, a first low-pass filter 7, a second low-pass filter 8, a first A / D 9, a second A / D 10, Complex multiplier 11, AGC 12, AGC 13, Error detector 1
4, the LPF 15 and the NCO 16, and the parts corresponding to each other operate in the same manner, and the duplicate description will be omitted.

In FIG. 1, reference numeral 17 denotes a power detector (abbreviated as PWR in the drawing), reference numeral 18 denotes a comparator (abbreviated as COMP in the drawing), and reference numeral 19 denotes LP.
F, symbol 20 is a digital-to-analog converter (hereinafter D / A
Abbreviated). That is, the AGC loop in FIG. 2 includes only the intermediate frequency amplification circuit 201 and the detector 202, but the AGC loop in FIG. 1 includes the intermediate frequency amplification circuit 201, the multipliers 5 and 6, and the low-pass filters 7 and 8. , A / Ds 9 and 10, power detector 17, L
It includes a PF 19 and a D / A 20. AGC
Since this difference in the loop configuration is the only difference between the conventional apparatus and the apparatus of the present invention, the configuration of the AGC loop shown in FIG. 1 will be mainly described below.

FIG. 3 is a block diagram showing an example of the configuration of the power detector 17. In FIG.
Is a second square circuit, and 173 is an adder circuit. First
Circuit 171 outputs the value of the square of the output of the first A / D 9, the second square circuit 172 outputs the value of the square of the output of the second A / D 10, and the addition circuit 173 outputs the square of The sum of the outputs of the circuits 171 and 172 is output. Adder circuit 17
The fact that the output of No. 3 becomes the active power of the signal is based on the equation (1)
This is as shown in 4). The gain of the intermediate frequency amplifier circuit 1 is controlled so that the active power of this signal becomes a predetermined value.

Output of power detector 17 (digital number)
Is one input of the comparator 18 and a reference value (represented by ref in the drawing) is the other input of the comparator 18.
And the comparison result is output. Comparator 1
The output 8 is normally output as a binary signal of "High" and "Low", integrated by the LPF 19, converted to an analog voltage by the D / A 20, and feedback-controlled the gain of the intermediate frequency amplifier circuit 1. That is, in the feedback loop shown in FIG. 1, the intermediate frequency amplifier circuit is set so that the signal power (the value of P in the equation (14)) output from the power detector 17 matches the reference value which is the other input of the comparator 18. A gain of one is controlled. Therefore, A / D9, A / D
A reference voltage value used for digital conversion at 10;
It is necessary that the signal power be set in relation to a predetermined value to be controlled (a reference numerical value which is the other input of the comparator 18).

The input of the first A / D 9 is I _A = (I /
2) cos θ + (Q / 2) sin θ (6), and the input of the second A / D 10 is Q _A = (Q / 2) co
is a sθ- (I / 2) sinθ ··· (7), and because I and Q is a +1 or -1, I _A also Q _A also both ± sin (θ ± π / 4 ) / √2 · ··· (15) Therefore, the range of A / D9, 10 is from + 1 / √2 to-
A / D reference voltage is determined so as to cover 1 / √2. With this reference voltage, I and Q are converted to +1 or -1. In this connection, from equation (14), P = (1 /
4) Since (I ² + Q ² ) = １ ／, the reference value (ref) which is the other input of the comparator 18 is set to １ ／. That is, when the C / N is normal, and when the reference voltage in which I and Q are converted into numerical values +1 or −1 in A / Ds 9 and 10 is used, the C / N of the intermediate frequency amplifier circuit 1 becomes worse. In the case of the circuit of FIG. 2 where the peak value of the output amplitude of the intermediate frequency amplification circuit 1 is controlled to the same value, the values of the signals I and Q decrease, but the circuit of FIG. The peak value of the output amplitude of the intermediate frequency amplifier circuit 1 is automatically amplified so that the value of P becomes a predetermined value, and the outputs of the A / Ds 9 and 10 are always maintained at the values given by the equation (15). .

Although the present invention has been described with reference to the preferred embodiments, it is needless to say that the present invention is not limited to the above-described embodiments. For example,
FIG. 1 shows that the present invention is applied to a quasi-synchronous detection circuit,
Although the AGC in the case where the phase rotation remains as shown in the equations (6) and (7) is described at the input of the A / D 10, the phase of the output of the local oscillator 3 (see the equation (2)) is changed. The present invention can also be applied to a synchronous detection circuit that is phase-locked to the phase of the intermediate frequency carrier (see equation (1)). FIG. 1 shows a case where the present invention is applied to a quadrature modulation type demodulation device.
keying) can also be applied to a demodulation device of a modulation method. That is, PSK can be considered to be a special quadrature modulation scheme in which Q = 0 in equation (1).

[0021]

As described above, according to the present invention, A
Since the A / D is included in the GC loop, even if the A / D input level fluctuates due to fading or disturbance due to white noise, the A / D output operates so as to converge to the reference level. Therefore, even if the A / D input level is set to the maximum, the A / D does not overflow. Further, since the AGC control signal is obtained from the digital signal after A / D, there is an effect that the temperature characteristic is less affected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional device.

FIG. 3 is a block diagram illustrating an example of a power detector of FIG. 1;

FIG. 4 is a schematic diagram showing a relationship between normal signal points of the quadrature modulation method and signal points detected by a conventional device.

FIG. 5 is a schematic diagram illustrating a relationship between a noise power included in a signal at an output point of the intermediate frequency amplifier circuit and a peak factor.

FIG. 6 is a schematic diagram showing the relationship between the A / D input range, the A / D input peak power, and the A / D input signal power in FIGS. 1 and 2;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 intermediate frequency amplifier circuit 3 local oscillator 4 π / 2 transporter 5 first multiplier 6 second multiplier 7 first low-pass filter 8 second low-pass filter 9 first A / D 10 second A / D 11 complex multiplier 12 AGC 13 AGC 14 error detector 15 LPF 16 NCO 17 power detector 18 comparator 19 LPF 20 D / A

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04Q 7/38 H04B 7/26 109N F term (Reference) 5J100 JA01 KA05 LA00 LA02 LA09 LA11 QA01 SA02 5K004 AA05 FG02 FH01 FH04 FH06 FJ08 5K020 AA08 CC03 DD21 DD23 EE04 EE05 EE16 FF00 GG16 LL01 LL07 5K061 AA04 AA13 BB12 BB14 CC11 CC14 CC23 CC27 CC52 5K067 AA03 BB02 DD51 EE02 EE10 GG11

Claims (6)

[Claims] An AGC (Automatic Gain Control) for amplifying an intermediate frequency signal generated by frequency-converting a received wave modulated by a quadrature modulation method and controlling the amplification gain thereof.
An intermediate frequency amplifier circuit having a (automatic gain control) control signal input terminal; a carrier signal phase-synchronized with the phase of the intermediate frequency signal;
A local oscillator for generating a carrier signal having a frequency close to the center frequency of the intermediate frequency signal; a phase shifter for giving a phase delay of π / 2 to a carrier wave output from the local oscillator; A first multiplier that multiplies an output by the output of the local oscillator; a second multiplier that multiplies an output of the intermediate frequency amplifier by an output of the phase shifter; A first low-pass filter that extracts only low-frequency components of the output, a second low-pass filter that extracts only low-frequency components of the output of the second multiplier, and an output of the first low-pass filter. A first analog-to-digital converter (hereinafter referred to as A / D) for converting to a digital signal
A second A / D for converting the output of the second low-pass filter into a digital signal, and the power of the signal from the output of the first A / D and the output of the second A / D. And a feedback control loop that controls the gain of the intermediate frequency amplifier circuit so that the output of the power detector becomes a predetermined numerical value. 2. The demodulator according to claim 1, wherein the power detector is a first square circuit that calculates a square value of an output of the first A / D, and an output of the second A / D. A demodulation device comprising: a second square circuit for calculating a square value of the second square circuit; and an addition circuit for adding an output of the first square circuit and an output of the second square circuit. 3. The demodulator according to claim 1, wherein the feedback control loop is a comparator that compares an output of the power detector with the predetermined numerical value; a loop filter that smoothes an output of the comparator; A digital-to-analog converter for converting the output of the digital-to-analog converter into an analog voltage; and a means for inputting the output of the digital-to-analog converter as a control signal to the AGC control signal input terminal of the intermediate frequency amplifier circuit. apparatus. 4. The demodulation device according to claim 1, wherein the reference voltage for digital conversion in the first A / D and the second A / D and the predetermined value serving as a control target value of the power detector. A demodulator characterized in that the numerical values are determined in relation to each other. 5. The demodulator according to claim 1, wherein the output of the intermediate frequency amplifier circuit is S = Icosω ₀ t.
+ Q sin ω ₀ t, and the output of the local oscillator is represented by L = cos ω ₁ t. The output of the first low-pass filter is I _A = (I / 2) cos (ω ₀ −ω ₁ ) t + (Q / 2)
sin (ω ₀ −ω ₁ ) t, and the output of the second low-pass filter is Q _A = (Q / 2) cos (ω ₀ −ω ₁ ) t− (I / 2)
sin (ω ₀ −ω ₁ ) t, and the output of the power detector (I _A ) ² + (Q _A ) ² = (1
/ 4) (I ² + Q ² ). 6. The demodulation device according to claim 5, wherein the output of the first A / D I _A = (I / 2) cos (ω ₀ −ω ₁ ) t + (Q / 2)
sin (ω ₀ −ω ₁ ) t and the output of the second A / D QA = (Q / 2) cos (ω ₀ −ω ₁ ) t− (I / 2)
sin (ω ₀ -ω ₁₎ and t, I _A + jQ to one input of the complex multiplier as _A, cos _{(ω 0} as the other input of the complex-multiplier -
ω ₁ ) t + jsin (ω ₀ −ω ₁ ) t, and receives a result of complex multiplication to obtain (１ ／) (I + jQ).