JP2000295089A - Output circuit and semiconductor device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit capable of realizing output amplitude exceeding breakdown strength with no illegal breakdown strength without making a process complicated nor bringing about the increase of power consumption and performance deterioration. SOLUTION: This output circuit has a level conversion circuit including a VDDH-ΔV amplitude generation circuit 3, a Vref=ΔV generation circuit 4, a VDDL-ΔV amplitude generation circuit 5, etc., and improves driving force because the levels of nodes N1 and N2 become equal to ΔV=VDDH-VDDL and the gate bias of PMOS transistors Qp1 and Qp2 can become the largest. Also, the circuit 5 makes the node N2 coincide with the node N1 to amplify it, an output signal OUT and the charging/discharging direction of the node N become opposite directions and the influence of coupling noise due to gate capacitance Cg can be canceled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit technology, and more particularly to an output circuit including a level conversion circuit capable of generating an output having an amplitude exceeding a withstand voltage without causing a withstand voltage violation in a device itself, and an output circuit including the same. The present invention relates to a technology that is effective when applied to a semiconductor device using a semiconductor device.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, a circuit for outputting a TTL level in an LSI has
In the case of using a MOS, a power supply voltage of 3 V or more is required. In general, a 3.3 V power supply has been used from the past.
However, with the advance of microfabrication technology, it became necessary to lower the withstand voltage of internal transistors.
It has been reduced from V to 2.5V and further to 1.8V. For this reason, it is considered that a general method is to leave a transistor formed by a process with a withstand voltage of 3.3 V in the output circuit and form the inside with a transistor of a low voltage and high speed process.

However, in this case, there is a problem that the process is complicated and the cost is increased by forming transistors of two types of processes. Also, considering the case where input / output is performed at the same voltage as the inside, since the input / output unit is driven at a voltage lower than the withstand voltage, there is a problem that a high speed corresponding to the voltage drop cannot be obtained. In order to solve this problem, the input / output section is also formed of transistors of the same low voltage (3.3 V or less) process as the inside, and by devising the circuit configuration, the 3.3 V output can be achieved without violating the withstand voltage. Possible output circuits are being considered.

An LSI having such an output circuit
Related technologies include, for example, August 20, 1992
"Basic ASIC glossary" published by CQ Publishing Co., Ltd.
And the like.

[0005]

By the way, the input / output section as described above is also formed by transistors of the same low voltage process as the inside, and an output circuit technique of a system capable of outputting 3.3 V without violating the withstand voltage. The result of the study by the inventor will be described based on an example of the system shown in FIG. 10 which is not publicly known but is studied by the inventor.

In FIG. 10, an output circuit is connected between an external power supply voltage VDDH (3.3 V) and a ground voltage.
The OS transistor Qp1, Qp2 and the NMOS transistor Qn3, Qn4 are connected in parallel with the resistor R61 and the NMOS transistor Qn61, Qn6.
2 and the input signal IN is connected to the inverter IV6
1 and an NMOS transistor Qn4 via an inverter IV62, and an output signal OUT is taken out from a connection node between the PMOS transistor Qp2 and the NMOS transistor Qn3. The gate of the PMOS transistor Qp1 is connected to a connection node between the resistor R61 and the NMOS transistor Qn61, and the PMOS transistor Qp2 and the NMOS transistors Qn3, Qn
The internal power supply voltage VDDL (2.5 V or
1.8 V).

In the output circuit of FIG. 10, the output signal OUT can actually output the amplitude of 0-external power supply voltage VDDH without violating the breakdown voltage of all the transistors. It is conceivable that various problems may occur.

The gate bias for turning on the PMOS transistor Qp1 is determined by the current ID flowing through the resistor R61.
Made by C. Therefore, power consumption by the current IDC occurs.

There is a problem with the accuracy of the resistor R61. If the accuracy is poor, the driving force of the PMOS transistor Qp1 changes, so that the performance of the output circuit itself also changes.

The gate bias of the PMOS transistor Qp2 is at most equal to the external power supply voltage VDDH-the internal power supply voltage V
Due to the DDL, the driving force on the H side (charging direction) of the output circuit is small, and the performance is inferior.

Therefore, an object of the present invention is to pay attention to the above-mentioned problems, and to reduce the output amplitude exceeding the withstand voltage without complicating the process, increasing power consumption or deteriorating the performance. It is an object of the present invention to provide an output circuit which can be realized without using the same and a semiconductor device using the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the output circuit according to the present invention comprises a PM
An input signal input to the gates of the OS transistor circuit and the NMOS transistor circuit has an amplitude voltage within a range between the internal power supply voltage and the ground voltage, and an output signal output from this connection node has a voltage value higher than the internal power supply voltage. The amplitude voltage within the range between the external power supply voltage and the ground voltage of the
The S transistor circuit and the NMOS transistor circuit do not violate the withstand voltage specified by the process due to the amplitude voltage within the range of the internal power supply voltage and the ground voltage, and the difference between the external power supply voltage and the ground voltage larger than the withstand voltage specified by the process It includes a level conversion circuit for generating an output signal having an amplitude voltage within the range.

In this configuration, the PMOS transistor circuit includes a first PMOS transistor and a second PMOS transistor connected in series, and the level conversion circuit is connected to a gate of the first PMOS transistor.
This configuration includes a first amplitude generation circuit that generates an output signal of an amplitude voltage within a range between an external power supply voltage and a reference voltage.

Specifically, the first amplitude generation circuit is connected to a cross-coupled latch circuit and this input / output stage, and a pair of
A third PMOS transistor and a circuit in which a third NMOS transistor, a first resistor, and a fourth NMOS transistor are connected in series; when the input signal goes high, the fourth NMOS transistor is turned on; A voltage obtained by subtracting the threshold voltage from the reference voltage is output to the connection node between the third PMOS transistor and the first resistor, and the third PMOS transistor and the P of the cross-coupled latch circuit are output.
The substrate node of the MOS transistor is separated from the power supply and short-circuited, the threshold voltage characteristics of each are matched, and the substrate is connected to the internal power supply voltage. The third PMOS transistor and the third PMOS transistor are arranged close to each other on the layout.

The level conversion circuit includes a second PMOS.
A second amplitude generation circuit is connected to the gate of the transistor and generates an output signal of an amplitude voltage within a range between the internal power supply voltage and the reference voltage.

Specifically, the second amplitude generation circuit is connected to the input stage, and has a fifth PMOS transistor and a fifth NM
OS transistor, second resistor, and sixth NMOS
When the input signal is at a high level, the connection node between the fifth PMOS transistor and the second resistor becomes a voltage obtained by subtracting the threshold voltage from the reference voltage, and the fifth PMOS transistor The threshold voltage characteristics of the transistor and the PMOS transistor in the output stage are matched to each other, and the substrate is connected to the internal power supply voltage.

Further, the level conversion circuit includes a reference voltage generation circuit for generating a reference voltage, the reference voltage generation circuit being embedded in an input / output buffer circuit, and a seventh PMO circuit.
It comprises a self-biasing stage composed of an S transistor and a seventh NMOS transistor, and a diode connection stage composed of an eighth NMOS transistor and an eighth PMOS transistor.

Further, a semiconductor device according to the present invention is configured such that an internal circuit is mounted together with the output circuit on one semiconductor substrate using the output circuit.

Therefore, according to the output circuit and the semiconductor device using the same, the first circuit includes the first amplitude generation circuit,
And when the second PMOS transistor is turned on, the voltage level of these gate nodes is equal to the reference voltage obtained by subtracting the internal power supply voltage from the external power supply voltage, thereby providing the first and second PMOS transistors. The gate bias of the transistor can be maximized, and the driving force can be improved.

Also, a second amplitude generating circuit is included, and the gate node of the second PMOS transistor is connected to the first PMOS transistor.
The amplitude is synchronized with the gate node of the transistor, and the charge / discharge direction of the output signal is opposite to the charge / discharge direction of the gate node of the second PMOS transistor. The influence of the coupling noise due to the gate capacitance can be canceled.

Furthermore, by including a reference voltage generating circuit, generating a reference voltage in a self-biasing stage, and compensating for variations in transistors in a diode connection stage, a voltage dividing method using a resistor can be adopted. By employing a bandgap method or the like, it is possible to improve the accuracy of the reference voltage and reduce the power consumption.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

FIG. 1 is a schematic circuit configuration diagram showing an output circuit according to an embodiment of the present invention, FIG. 2 is a schematic circuit configuration diagram showing an output circuit in which noise measures are taken in this embodiment, and FIG. A circuit diagram showing a VDDH-ΔV amplitude generation circuit;
FIG. 4 is a circuit diagram showing a VDDL-ΔV amplitude generation circuit, and FIG.
Is the Vref-ΔV generation circuit, Δ
FIG. 6 is a circuit diagram illustrating a bandgap reference voltage generation method, FIG. 7 is a diagram illustrating a method of forming a bipolar transistor, and FIG. 8 is a description illustrating an implementation example of a bandgap reference voltage generation circuit. FIG. 9 is a circuit diagram showing a reference voltage generation circuit.

First, an example of the configuration of the output circuit of the present embodiment will be described with reference to FIGS.

The output circuit according to the present embodiment is, for example, shown in FIG.
, The PMOS transistors Qp connected in series
1 and Qp2, an NMOS transistor circuit 2 connected in series with the PMOS transistor circuit 1 and NMOS transistors Qn3 and Qn4, and VDDH-ΔV connected to the PMOS transistor circuit 1. Amplitude generation circuit 3,
Vre connected to the VDDH-ΔV amplitude generation circuit 3
f = ΔV generation circuit 4 and the like, and the input signal IN is VDDH−ΔV amplitude generation circuit 3, N
The circuit configuration is such that the output signal OUT is input to the MOS transistor circuit 2 and output from the connection node between the PMOS transistor circuit 1 and the NMOS transistor circuit 2.

The PMOS transistor circuit 1 is a PMOS transistor circuit.
The transistor Qp1 includes a transistor Qp1 and a PMOS transistor Qp2.
H-ΔV amplitude generation circuit 3, source is external power supply voltage VDD
H, the drain is connected to the source of the PMOS transistor Qp2, the gate of the PMOS transistor Qp2 is Vref = ΔV generation circuit 4, and the drain is NMO.
Respectively connected to the drain of the S transistor Qn3,
Further, the substrate nodes of the PMOS transistors Qp1 and Qp2 are connected to the external power supply voltage VDDH.

The NMOS transistor circuit 2 includes an NMOS transistor
It comprises a transistor Qn3 and an NMOS transistor Qn4. The gate of the NMOS transistor Qn3 is an internal power supply voltage VDDL, and the drain is a PMOS transistor Qp.
The drain and source of the NMOS transistor Qn4 are connected to the drain of the NMOS transistor Qn4, respectively. The gate of the NMOS transistor Qn4 is connected to the input signal IN, and the source is connected to the ground voltage.

The VDDH-.DELTA.V amplitude generating circuit 3 is a circuit for generating an output signal of an amplitude voltage within a range between the external power supply voltage VDDH (maximum) and the reference voltage .DELTA.V (minimum).
The reference voltage ΔV from the ef = ΔV generation circuit 4 and the input signal IN having the amplitude of 0−the internal power supply voltage VDDL are input, the level is converted to the amplitude of the external power supply voltage VDDH−the reference voltage ΔV, and output as an output signal.

Vref = ΔV generation circuit 4 generates reference voltage Δ
And a reference voltage .DELTA.V having the amplitude of the external power supply voltage VDDH minus the internal power supply voltage.

In the above output circuit configuration, the node N
1 indicates that the amplitude of the low-level reference voltage ΔV and the amplitude of the high-level external power supply voltage VDDH are generated.
The node N2 indicates that the reference voltage ΔV is kept constant. Thereby, the PMOS transistor Qp
When 1, Qp2 is turned on to drive in the charging direction, a large driving force can be realized. However, this circuit has a problem that the node N2 receives coupling noise due to the gate capacitance Cg of the PMOS transistor Qp2. The mechanism is as described below.

Generally, PMOS transistors Qp1 and Qp2 and NMOS transistors Qn3 and Qn constituting an output stage
For n4, a transistor having a large gate width is used to charge and discharge a large capacity outside the LSI. Therefore, when the output signal OUT operates in the charging direction (in the direction of the arrow in FIG. 1), the gate capacitance Cg is considerably large.
Noise occurs in the direction in which the level of the node N2 rises via g. The same applies to the discharge direction. Therefore, as an outline of a circuit configuration that solves this problem, one shown in FIG. 2 can be considered.

The circuit configuration of FIG. 2 differs from the circuit of FIG. 1 in that the output of the Vref = ΔV generation circuit 4 and the input signal I
VD between N and the gate of the PMOS transistor Qp2.
The DL-ΔV amplitude generation circuit 5 is added. This VDDL- [Delta] V amplitude generation circuit 5 has an internal power supply voltage VDD.
This circuit generates an output signal having an amplitude voltage in the range between L (maximum) and reference voltage ΔV (minimum). Vref = ΔV from the ΔV generation circuit 4, 0−internal power supply voltage VDD
With an input signal IN having an amplitude of L as input, the internal power supply voltage V
The level is converted to the amplitude of DDL-reference voltage ΔV and output as an output signal.

With the addition of the VDDL-.DELTA.V amplitude generation circuit 5, the node N2 swings in synchronization with the node N1 (or the same even if the node N2 is synchronized with the input signal IN). And the charge / discharge direction of the node N2 is in the opposite direction, and therefore, there is an effect of canceling the influence of the coupling noise due to the gate capacitance Cg.

Next, referring to FIGS. 3 to 9, the VDDH-.DELTA.V amplitude generating circuit 3 and the VDDL-
An example of the configuration of the ΔV amplitude generation circuit 5 and Vref = ΔV generation circuit 4 will be described in detail.

As shown in FIG. 3, the VDDH-.DELTA.V amplitude generation circuit 3 includes a cross-coupled latch circuit 6, a pair of correction circuits 7, 8 connected to the input / output stage, and an inverter IV.
11 and the like. Cross-coupled latch circuit 6
Include PMOS transistors Qp11 to Qp14, NM connected between an external power supply voltage (VDDH) and a ground voltage.
OS transistors Qn11 to Qn14, resistors R11 and R
12 and the like are provided. A pair of correction circuits 7 and 8 have a PM connected between a reference voltage (ΔV) and a ground voltage.
OS transistors Qp15 and Qp16, NMOS transistors Qn15 to Qn18, resistors R13 and R14, and the like are provided. In the VDDH-ΔV amplitude generation circuit 3, the input signal IN is the NM of the cross-coupled latch circuit 6.
OS transistor Qn13 and N of a pair of correction circuits 7 and 8
The gates of the MOS transistors Qn16 and Qn17 are respectively input to the inverter IV11 of the input signal IN.
The inverted signal through the NMOS is connected to the NMOS of the cross-coupled latch circuit 6.
NMO of transistor Qn14 and a pair of correction circuits 7 and 8
The input signal is input to the gates of the S transistors Qn15 and Qn18, and an output signal is output from a connection node N1 between the PMOS transistor Qp12 and the PMOS transistor Qp14 of the cross-coupled latch circuit 6.

The VDDH-.DELTA.V amplitude generating circuit 3 calculates the .DELTA.
V as a reference voltage (Vref =
ΔV generation circuit), and 0 as the input signal IN.
The node N receives the amplitude of the internal power supply voltage (VDDL)
1 is a circuit for converting the level to VDDH-ΔV and outputting the result. All the transistors in the figure have a withstand voltage of VD.
DL. The main operation of the amplitude conversion circuit, which is the function of the VDDH-ΔV amplitude generation circuit 3, is performed by the cross-coupled latch circuit 6 in the figure. The cross-coupled latch circuit 6 is characterized in that it is stabilized at a level after conversion, and it is known that a latch is used. Ingenious.

That is, since the amplitude required for the node N1 is VDDH-.DELTA.V, in the cross-coupled latch circuit 6, the node N1 or the node N4 (hereinafter, for convenience of explanation, attention will be paid to the node N4. When a low level is attained, it is necessary not to drop to 0 V but to stay at ΔV. This is PMOS
This is realized as follows by the transistor Qp13.
When the input signal IN becomes high level, the NMOS transistor Qn13 turns on, so that the extraction of the node N4 starts. However, the level of the node N4 is equal to the gate level of the PMOS transistor Qp13, that is, the threshold voltage Vp.
thp in consideration of the level of the node N3 + | Vthp |
It only goes down to. Therefore, the level of the node N4 is Δ
To stay at V, the level of the node N3 must be ΔV− | Vth
p |. Therefore, the node N3 is ΔV− | Vt
It seems to be fixed to hp |, but this causes the following two problems.

First, when the node N4 becomes high level, that is, VDDH, a breakdown voltage violation occurs between the node N4 and the node N3. Second, the level of the node N4 varies due to the variation of Vthp. Two points. As can be seen from FIG. 2, the node N1 or the node N4 is an important factor that determines the driving force of the transistor in the output stage. Since the node N1 or the node N4 is in the series stage, the gate voltage must be applied deeply to the breakdown voltage. Therefore, it is important to eliminate the causes of variation as much as possible. In order to solve these two problems, a pair of correction circuits 7 and 8 shown in FIG. 3 are added. Hereinafter, the correction circuit 7 (the same applies to the correction circuit 8 because of the symmetry of the circuit) will be described.

In the correction circuit 7, when the input signal IN goes high, the NMOS transistor Qn17 is turned on, and the PMOS transistor Qp15 is diode-connected, so that ΔV- | Vthp | is output to the node N3. Further, the PMOS transistors Qp13 and P
By separating the substrate node of the MOS transistor Qp15 from the power supply and short-circuiting, the Vthp characteristics including the substrate effect of the PMOS transistors Qp13 and Qp15 are matched. PMOS transistors Qp13 and P
By arranging the MOS transistors Qp15 close to each other on the layout, the Vthp characteristics of both can be made substantially the same. Thereby, even if Vthp varies between chips or lots, the node N1 or the node N4
, An accurate ΔV level can be output.

That is, the above-mentioned problem can be solved. Next is the problem, node N
4 goes high when the input signal IN is low, and the NMOS transistor Qn15 at this time is
Turns on, the voltage at the node N3 becomes ΔV, and the bias between the node N4 and the node N3 becomes VDDL, so that the withstand voltage violation does not occur. That is, the problem was solved. Note that FIG.
The internal resistors R13 and R12 are connected to a PMOS transistor Qp1.
3, because it is for supplying a small current to keep Qp15 in a diode connection, it is necessary to make the resistance high. When there is no high-resistance process, a transistor having a small gate width may be replaced with a transistor in which multiple transistors are connected in series.

The VDDL-ΔV amplitude generation circuit 5 includes
PMO connected between ΔV and ground voltage as shown in
S transistor Qp21, NMOS transistor Qn2
1, Qn22, resistor R21, inverter IV21, and V
PMOS transistors Qp22, Qp23, NMOS transistor Qn2 connected between DDL and ground voltage
3, a resistor R22 and the like are provided. This VDDL-
In the ΔV amplitude generation circuit 5, the input signal IN is an NMOS
Transistors Qn22 and Qn23 and a gate of a PMOS transistor Qp22 are respectively input to the gates thereof.
The signal is input to the gate of the transistor Qn21, and an output signal is output from a connection node N2 between the PMOS transistor Qp22 and the PMOS transistor Qp23.

The operation principle of the VDDL-.DELTA.V amplitude generation circuit 5 is the same as that of the VDDH-.DELTA.V amplitude generation circuit 3 shown in FIG. 3, and the input signal IN is high so that the low level of the node N2 becomes .DELTA.V. Node N5 is ΔV
− | Vthp |. This is generated by the diode-connected PMOS transistor Qp21, and it is important to match the Vthp characteristics of the PMOS transistor Qp21 and the PMOS transistor Qp23. By connecting the substrates of the PMOS transistors Qp21 and Qp23 to VDDL, the substrate effect can be matched. Since it is VDDL, this does not cause a withstand voltage violation. The resistors R21 and R22 are PMO
When the S transistors Qp21 and Qp22 are diode-connected (when the level shifts by Vthp), the purpose is to flow a small current so as not to be cut off. This corresponds to R13, R1 in FIG.
Same as 2.

Vref = ΔV generation circuit 4 calculates ΔV = VD
A circuit for generating DH-VDDL as a reference voltage,
Accuracy is required, but current supply power is not as required as a general power supply circuit. Some examples are conceivable. Here, (1). External Vref supply type, (2). Internal Vre
The f-supply type-bandgap reference voltage generation method and (3). Internal Vref supply type-the proposed method will be described.

(1). External Vref supply type The simplest method, for example, as shown in FIG.
A level of ΔV generated externally by a voltage dividing method of the resistors R31 and R32 is supplied as a reference voltage. In this case, there are disadvantages that the user needs to mount a reference voltage generating circuit outside the LSI and that at least one I / O buffer cell needs to be used for the Vref supply pin inside the LSI.

(2) Internal Vref Supply Type-Bandgap Reference Voltage Generation Method As a method of generating a level inside the LSI, there is a method using a bandgap reference which is a known method.
For example, as shown in FIG. 6, a circuit using this band gap reference includes a current source V41 and transistors Q41 to Q4 connected between a power supply voltage VDD and a ground voltage.
3, resistors R41 to R43 and the like are provided. In this circuit, the potential generated at Vref is Vref = Vbe
(Q43) + R42 / R43 · kT / q · ln (I41
/ I42). This is Δ
Adjust the values of R42 and R43 to match V. LSI
As an internal mounting method, it is possible to form a bipolar transistor with a layout as shown in FIG. 7, for example, by using a triple well CMOS process.

That is, this bipolar transistor has an N-type well n-Well on a P-type substrate p-Sub,
A P-type well p-Well is formed.
A triple well structure in which a P-type region p + serving as a base and an N-type region n + serving as an emitter are formed in the -Well, and an N-type region n + serving as a collector is formed in the N-type well n-Well; Has become.

(3) Internal Vref Supply Type—Proposed Method The above-described bandgap reference voltage generation method has a triple well structure as shown in FIG. 7 and includes a general MOS used in the internal region. Since the transistor has a special layout in which the shape of the diffusion layer is different from that of the transistor, there is a problem of where to mount the transistor inside the LSI. In particular, in the case of a gate array, if a transistor of a special shape is provided in the internal region,
It cannot be used for general logic, and the gate usage rate decreases. Therefore, as shown in FIG. 8, for example, it is assumed that the area at the lower left corner is assigned to the bandgap reference voltage generation circuit. This makes it possible to use up the internal region for logic transistors.
However, the following problem still remains.

For example, in the case of a gate array, as shown in FIG.
Since it is not possible to predict in advance where the TTL-I / O buffer circuit will be used, the impedance of the peripheral circuit becomes high in the buffer circuit far from the lower left corner,
The level tends to be unstable. In order to solve this, the same circuit must be embedded in the four corners. However, it is often difficult to implement the four corners because a process monitor cell or a ring oscillator is often embedded in the four corners.

Therefore, in the proposed method, in order to avoid the above problem, a method of embedding a circuit for generating the reference voltage ΔV in the I / O buffer circuit has been considered. That is, if a special diffusion layer structure is provided, it cannot be used in a circuit other than the LV-TTL and is wasted. Therefore, a normal CMOS circuit has a circuit configuration as shown in FIG. 9, for example.

In this circuit, a self-biasing stage 9 composed of a PMOS transistor Qp51 and an NMOS transistor Qn51 connected between VDDL and a ground voltage, and a diode connection stage 10 composed of a reversely connected NMOS transistor Qn52 and a PMOS transistor Qp52. The self-biasing stage 9 adjusts the sizes of the PMOS transistor and the NMOS transistor so as to generate the reference voltage, and the diode connection stage 10 compensates for the variation between the NMOS transistor and the PMOS transistor.

For example, if the PMOS transistor is NMO
In the case where the drain current varies in a direction in which a large amount of drain current can be obtained with respect to the S transistor, first, feedback is applied in the self-bias stage 9, so that an increase in Vref is suppressed. Still Vr
When ef is tilted in the rising direction, the gate voltage of the PMOS transistor of the diode connection stage 10 is applied deeply, and works to stabilize Vref.
In this method, when Vref is close to 1/2 of VDDL, the adjustment is particularly easy and easy to use.

Since this circuit is a normal CMOS circuit, it can be formed using the transistors of each I / O buffer cell. Therefore, since it can be embedded in each of the LV-TTL I / O buffer circuits, there is no need for a peripheral line for supplying Vref, and the problem of the band gap reference generation circuit can be solved.

Therefore, according to the output circuit of the present embodiment, the PM composed of the PMOS transistors Qp1 and Qp2
OS transistor circuit 1, NMOS transistor Qn
And a level conversion circuit such as a VDDH-.DELTA.V amplitude generation circuit 3 and a Vref-.DELTA.V generation circuit 4 in addition to the NMOS transistor circuit 2 comprising the NMOS transistors 3 and Qn4. When the PMOS transistors Qp1 and Qp2 are turned on, the nodes N1 and N2 The circuit configuration is such that the level of .DELTA.V is equal to .DELTA.V = VDDH-VDDL, thereby generating an amplitude larger than the withstand voltage specified in the process without violating the withstand voltage, and maximizing the gate bias of the PMOS transistors Qp1 and Qp2. Therefore, the driving force can be improved.

Further, a VDDL-.DELTA.V amplitude generating circuit 5 is added to make the node N2 oscillate in synchronization with the node N1 so that the charging and discharging direction of the output signal OUT and the charging and discharging direction of the node N2 become opposite. With the circuit configuration, the influence of coupling noise due to the gate capacitance Cg can be canceled.

Further, in the Vref-.DELTA.V generation circuit 4, the generation of .DELTA.V is based on a known reference voltage generation circuit such as a bandgap method, and a voltage division method using a resistor is not employed, so that accuracy is improved and power consumption is reduced. realizable.
In this case, since ΔV is generated as the reference voltage as described above, it is assumed that a large current cannot be supplied from ΔV.

In a logic LSI including an output circuit as in this embodiment, a logic circuit and the like by logic circuit cells are arranged in an internal region, and an input and output circuit by input and output circuit cells are arranged around the logic circuit. For example, an external power supply voltage of 3.3 V is input, the input / output circuit is 2.5 V, and the logic circuit is
The circuit configuration is operable at 1.8V. As a result,
The output amplitude exceeding the withstand voltage can be realized without complicating the process and without increasing power consumption or deteriorating the performance without violating the withstand voltage. Points can be improved. Therefore, the competitiveness as an LSI product can be improved.

Further, the logic LSI (1.8 V to 1.5 V)
V) or a system in which another processor LSI, memory LSI, or the like is mounted on a board, for example, the voltage between the logic LSI and the processor LSI is 1.2 V to 0.4 V.
(GTL) or between 1.5 V and 0.5 V (GTL +), for example, between 3.3 V and 0 V (LV-
When a voltage specification between the logic LSI and another LSI, such as TTL) or 2.4 V to 0.4 V (SSTL), is used, such as 2.5 V to 0 V, the above-described features are applied to such a system. Is possible.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, the present invention uses a process having the same withstand voltage as the internal voltage to realize the performance improvement in accordance with the trend in the low-amplitude input / output and the conventional TT.
The feature is that the input / output of the L level amplitude is also possible. Therefore, as an example in which the effect of the present invention is exhibited, the low amplitude and the TTL amplitude are mixed, including the logic LSI and the system of the above embodiment. In some cases, a low-amplitude-only and TTL-only LSI may be designed in the same series.
An ASIC or the like is conceivable.

[0062]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). PMOS transistor circuit and NM
A level conversion circuit for generating an output signal having an amplitude voltage larger than the withstand voltage specified by the process without causing the OS transistor circuit to violate the withstand voltage specified by the process; Having a circuit configuration such that when the first and second PMOS transistors are turned on, the voltage levels of these gate nodes become equal to the reference voltage obtained by subtracting the internal power supply voltage from the external power supply voltage. The gate bias of the first and second PMOS transistors can be maximized, and the driving power can be improved.

(2) In the above (1), a second amplitude generating circuit is provided in the level conversion circuit, and the gate node of the second PMOS transistor is synchronized with the gate node of the first PMOS transistor to generate the amplitude. By making the circuit configuration such that the charge / discharge direction of the output signal is opposite to the charge / discharge direction of the gate node of the second PMOS transistor, the influence of coupling noise due to the gate capacitance of the second PMOS transistor is obtained. Can be canceled.

(3) In the above (1), a circuit configuration is provided in which a reference voltage generation circuit is provided in the level conversion circuit, a reference voltage is generated in a self-bias stage, and variations in transistors are compensated in a diode connection stage. As a result, it is possible to improve the accuracy of the reference voltage and reduce the power consumption by adopting a band gap method or the like without using the voltage dividing method using a resistor.

(4) According to the above (1) to (3), in the output circuit including the level conversion circuit and the semiconductor device using the same, the process is not complicated, the power consumption is increased and the performance is improved. The output amplitude exceeding the withstand voltage can be realized without causing the deterioration without violating the withstand voltage, thereby making it possible to improve the three points of manufacturing cost, power consumption and performance. Therefore, the competitiveness of the semiconductor device as a product can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing an output circuit according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram showing an output circuit in which noise suppression is performed in one embodiment of the present invention.

FIG. 3 shows VDDH-Δ in one embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a V amplitude generation circuit.

FIG. 4 shows VDDL-Δ in one embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a V amplitude generation circuit.

FIG. 5 shows Vref-Δ according to an embodiment of the present invention.
FIG. 4 is an explanatory diagram showing a ΔV generation method by external mounting of a V generation circuit.

FIG. 6 shows Vref-Δ according to an embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a band gap reference voltage generation method of a V generation circuit.

FIG. 7 shows Vref-Δ according to an embodiment of the present invention.
FIG. 4 is an explanatory diagram illustrating a method of forming a bipolar transistor in the V generation circuit.

FIG. 8 shows Vref-Δ according to an embodiment of the present invention.
FIG. 4 is an explanatory diagram illustrating an example of mounting a bandgap reference voltage generation circuit in a V generation circuit.

FIG. 9 is a circuit diagram showing a reference voltage generation circuit in one embodiment of the present invention.

FIG. 10 is a circuit configuration diagram showing an output circuit on which the present invention is based.

[Explanation of symbols]

Reference Signs List 1 PMOS transistor circuit 2 NMOS transistor circuit 3 VDDH-ΔV amplitude generation circuit 4 Vref-ΔV generation circuit 5 VDDL-ΔV amplitude generation circuit 6 Cross-coupled latch circuit 7,8 correction circuit 9 Self-bias stage 10 Diode connection stage Qp1, Qp2 , Qp11-Qp16, Qp21-Qp
23, Qp51, Qp52 PMOS transistors Qn3, Qn4, Qn11-Qn18, Qn21-Qn
23, Qn51, Qn52, Qn61, Qn62 NM
OS transistors R11 to R14, R21, R22, R31, R32, R
41 to R43, R61 Resistance IV11, IV21, IV61, IV62 Inverter V41 Current source Q41 to Q43 Transistor VDDH External power supply voltage VDDL Internal power supply voltage ΔV Reference voltage VDD Power supply voltage

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (7)

[Claims] 1. A PMOS transistor circuit and an NMOS transistor circuit are connected in series, an input signal is input to gates of the PMOS transistor circuit and the NMOS transistor circuit, and a connection between the PMOS transistor circuit and the NMOS transistor circuit is provided. An output circuit that outputs an output signal from a node, wherein the input signal is an amplitude voltage within a range between an internal power supply voltage and a ground voltage, and the output signal is an external power supply voltage having a voltage value higher than the internal power supply voltage. And the ground voltage, the PMOS transistor circuit and the NMOS transistor circuit do not violate the withstand voltage specified in the process by the amplitude voltage within the range between the internal power supply voltage and the ground voltage. The external power supply voltage larger than the withstand voltage specified in the process; Output circuit comprising a level conversion circuit for generating an output signal of the amplitude voltage of the range of the serial ground voltage. 2. The output circuit according to claim 1, wherein said PMOS transistor circuit comprises a first PMOS transistor connected in series.
A level conversion circuit that includes a MOS transistor and a second PMOS transistor, is connected to a gate of the first PMOS transistor, and generates an output signal having an amplitude voltage within a range between the external power supply voltage and a reference voltage; A first amplitude generating circuit, wherein when the first and second PMOS transistors are turned on, the voltage level of these gate nodes is equal to a reference voltage obtained by subtracting the internal power supply voltage from the external power supply voltage. An output circuit characterized by being configured. 3. The output circuit according to claim 2, wherein said first amplitude generation circuit is connected to a cross-coupled latch circuit, said input / output stage, and includes a pair of a third PMOS transistor and a third PMOS transistor. And a circuit in which a third NMOS transistor, a first resistor, and a fourth NMOS transistor are connected in series. When the input signal goes high, the fourth NMOS transistor is turned on, and the third PMOS transistor is turned on. A voltage obtained by subtracting a threshold voltage from the reference voltage is output to a connection node between the third PMOS transistor and the PMOS transistor of the cross-coupled latch circuit. And short-circuited separately from each other, matching the threshold voltage characteristics of each other, and connecting the substrate to the internal power supply voltage. The PMOS transistor of the switch circuit and the third PMOS transistor are
An output circuit, which is arranged in close proximity. 4. The output circuit according to claim 2, wherein said level conversion circuit is connected to a gate of said second PMOS transistor, and outputs an amplitude voltage within a range between said internal power supply voltage and said reference voltage. A second amplitude generation circuit for generating an output signal, wherein the amplitude of the gate node of the second PMOS transistor is synchronized with the gate node of the first PMOS transistor, An output circuit, wherein the charge / discharge direction of the gate node of the second PMOS transistor is opposite to the charge / discharge direction. 5. The output circuit according to claim 4, wherein said second amplitude generation circuit is connected to an input stage, and said fifth amplitude generation circuit is connected to an input stage.
OS transistor and fifth NMOS transistor, second
And a circuit in which a sixth NMOS transistor and a sixth NMOS transistor are connected in series. When the input signal is at a high level, a connection node between the fifth PMOS transistor and the second resistor is connected to a threshold from the reference voltage by a threshold voltage. The fifth PMOS transistor and the PMOS transistor in the output stage are matched with each other in a threshold voltage characteristic, and a substrate is connected to the internal power supply voltage. An output circuit characterized by the above. 6. The output circuit according to claim 2, wherein said level conversion circuit further includes a reference voltage generation circuit for generating said reference voltage, said reference voltage generation circuit being embedded in an input / output buffer circuit. A self-biasing stage composed of a seventh PMOS transistor and a seventh NMOS transistor for generating a reference voltage by adjusting the size, an eighth NMOS transistor and an eighth PMOS transistor for compensating for variations, and And a diode connection stage comprising: 7. A semiconductor device using the output circuit according to claim 1, wherein the internal circuit is mounted together with the output circuit on one semiconductor substrate. A semiconductor device characterized by the above-mentioned.