JP2000295051A - Offset adjusting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an offset adjusting circuit which has high input impedance and also a wideband and also whose circuit configuration is simple. SOLUTION: This offset adjusting circuit which adjusts the direct current component of an input signal and outputs it is provided with capacitance 20 connecting the input signal to an output terminal, a 1st source follower circuit 52 to which the input signal is inputted, a 1st offset control circuit 54 which controls the offset of an output of the 1st offset follower circuit and outputs it to the output terminal, a 2nd source follower circuit 53 to which a variable voltage is inputted, a 2nd offset control circuit 55 controlling the offset of an output of the 2nd source follower circuit and a bias control circuit 56 feeding a bias voltage to the 1st and 2nd offset control circuits so as to make an output of the 2nd offset control circuit a reference voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset adjusting circuit, and more particularly to an offset adjusting circuit having a high input impedance, a wide band, and a simple circuit configuration.

[0002]

2. Description of the Related Art A conventional offset adjustment circuit is a circuit for adjusting the offset of an input signal in order to adjust a DC component of an input signal input to an input circuit such as an oscilloscope and supply the DC component to a subsequent circuit.

FIG. 2 is a block diagram showing an example of such a conventional offset adjusting circuit. In FIG. 2, 1
Is a signal source for supplying an input signal, 2, 3, 6, 7, 8,
9, 12, 13, 16 and 17 are resistors, 4 and 10 are capacitors, 5 and 11 are operational amplifiers, 14 is a PNP transistor (hereinafter simply referred to as a transistor), 15 is a constant voltage source, and 18 is a junction type electric field. Junction Fiel
d Effect Transistor: Hereinafter, simply referred to as FET. ), 1
9 is a variable voltage source, 100 is an input terminal, 101 is an output terminal, and 102 is an offset voltage input terminal.

Further, 2, 3, 5 to 11 constitute a DC buffer circuit 50, and 12 to 18 constitute a source follower circuit 51, respectively.

[0005] One end of the signal source 1 is connected to the input terminal 100, and the input terminal 100 is connected to one end of the resistor 2 and one end of the capacitor 4. The other end of the resistor 2 is connected to one end of the resistor 3 and the non-inverting input terminal of the operational amplifier 5, and the output terminal of the operational amplifier 5 is connected to one end of the resistor 6 and one end of the resistor 8. The other end of the resistor 6 is connected to one end of the resistor 7 and the inverting input terminal of the operational amplifier 5.

The other end of the resistor 8 is connected to one end of the resistor 9, one end of the capacitor 10, and the non-inverting input terminal of the operational amplifier 11, and the output terminal of the operational amplifier 11 is connected to one end of the resistor 13.

On the other hand, the other end of the capacitor 4 is connected to one end of the resistor 16 and the gate of the FET 18, and the source of the FET 18 is connected to one end of the resistor 17. The other end of the resistor 16 is connected to the output terminal 101 and to the collector of the transistor 14 and the other ends of the resistors 7 and 17.

The emitter of the transistor 14 is connected to one end of the resistor 12 and the other end of the resistor 13,
Is connected to the negative output terminal of the constant voltage source 15. The positive output terminal of the variable voltage source 19 is connected to the offset voltage input terminal 102, and the offset voltage input terminal 102
Is connected to the other end of the resistor 9.

Further, the other end of the signal source 1, the other end of the resistor 3,
The other end of the capacitor 10, the inverting input terminal of the operational amplifier 11, and the negative output terminal of the variable voltage source 19 are grounded.
2 and the positive output terminal of the constant voltage source 15 are connected to the positive voltage source "V".
cc ", and the drain of the FET 18 is connected to a negative voltage source" Vee ".

Now, the operation of the conventional example shown in FIG. 2 will be described. The signal component of the input signal input from the signal source 1 is supplied to the source follower circuit 51 via the capacitor 4, and the DC component of the input signal is supplied to the DC buffer circuit 50.

The output of the DC buffer circuit 50 adjusts the offset voltage by injecting a control current into the emitter of the transistor 14 constituting the source follower circuit 51 and adjusts the offset voltage. Return will take. For this reason, the DC potential of the output signal appearing at the output terminal 101 is controlled to a constant value. Further, the output voltage of the variable voltage source 19 is subtracted from the output of the operational amplifier 5 and supplied to the emitter of the transistor 14.

For example, when the resistances of the resistors 2, 3, 6 and 7 are equal to each other and the resistances of the resistors 8 and 9 are equal, the voltage of the input signal is "Vin" and the voltage of the output signal is "Vout". ", The output voltage of the variable voltage source 19 is set to" Vof
s ", Vout = Vin-Vofs (1)

As a result, a negative feedback is applied to the DC component of the input signal to control the input signal to a constant value, and the control current value supplied to the source follower circuit for buffering the signal component by subtracting the output voltage of the variable voltage source is adjusted. By doing so, it is possible to freely adjust the offset of the input signal.

[0014]

However, in the conventional example shown in FIG. 2, since the control in the DC buffer circuit 50 for controlling the DC component of the input signal is complicated, the cost is high, and the input resistance of the offset adjustment circuit is a resistance. 2 and resistor 3
However, there is a problem that the input resistance value becomes low because of the series connection of the.

Further, a high frequency component may be applied to the operational amplifier 5 to cause a malfunction, and the shape of the low frequency waveform may be deteriorated. Further, there is a problem that the return of the circuit at the time of excessive input is delayed due to the presence of feedback in the signal path. Therefore, an object of the present invention is to realize an offset adjustment circuit having a high input impedance, a wide band, and a simple circuit configuration.

[0016]

According to a first aspect of the present invention, there is provided an offset adjusting circuit for adjusting a DC component of an input signal and outputting the adjusted signal. And a first source follower circuit to which the input signal is inputted,
A first offset control circuit for controlling the offset of the output of the first source follower circuit and outputting the output to the output terminal; a second source follower circuit for receiving a variable voltage; and a second source follower circuit A second offset control circuit for controlling an offset of the output of the first and second offset control circuits, and a bias control circuit for supplying a bias voltage to the first and second offset control circuits so that an output of the second offset control circuit becomes a reference voltage. Is provided, it is possible to output a voltage obtained by adding a constant voltage to the voltage of the input signal irrespective of temperature fluctuations and power supply fluctuations.

According to a second aspect of the present invention, in the offset adjusting circuit according to the first aspect, the first source follower circuit has a drain connected to a negative voltage source and the input signal input to a gate. By comprising a first voltage effect transistor and a first constant current source having one end connected to a positive voltage source and the other end connected to the source of the first voltage effect transistor, temperature fluctuation and power supply It is possible to output a voltage obtained by adding a constant voltage to the voltage of the input signal regardless of the fluctuation.

According to a third aspect of the present invention, in the offset adjusting circuit according to the first aspect, the second source follower circuit has a drain connected to a negative voltage source and the variable voltage input to a gate. By including a second voltage effect transistor and a second constant current source having one end connected to the positive voltage source and the other end connected to the source of the second voltage effect transistor, temperature fluctuation and power supply It is possible to output a voltage obtained by adding a constant voltage to the voltage of the input signal regardless of the fluctuation.

According to a fourth aspect of the present invention, in the offset adjusting circuit according to the first aspect of the present invention, the first offset control circuit is connected to an output of the first source follower circuit at one end. A third voltage effect transistor having a source connected to the positive voltage source, the other end of the first resistor connected to the drain, and an output of the bias control circuit connected to the gate; A third constant current source connected to the voltage source and having the other end connected to the drain of the third voltage effect transistor, so that the voltage of the input signal is constant regardless of temperature fluctuations and power supply fluctuations. It is possible to output a voltage obtained by adding the voltages.

According to a fifth aspect of the present invention, in the offset adjusting circuit according to the first aspect of the present invention, the second offset control circuit is connected to one end of an output of the second source follower circuit. A fourth voltage effect transistor having a source connected to the positive voltage source, the other end of the second resistor connected to the drain, and an output of the bias control circuit connected to the gate; A fourth constant current source connected to the voltage source and having the other end connected to the drain of the fourth voltage effect transistor, so that the voltage of the input signal is kept constant irrespective of temperature fluctuations and power supply fluctuations. It is possible to output a voltage obtained by adding the voltages.

According to a sixth aspect of the present invention, in the offset adjusting circuit according to the first aspect, the bias control circuit includes a constant voltage source for outputting the reference voltage, and an output of the second offset control circuit. Is connected to a non-inverting input terminal, the reference voltage is connected to an inverting input terminal, and an operational amplifier whose output is supplied as a bias voltage to the first and second offset control circuits is provided. It is possible to output a voltage obtained by adding a constant voltage to the voltage of the input signal irrespective of fluctuations and power supply fluctuations.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration circuit diagram showing an embodiment of the offset adjustment circuit according to the present invention. In FIG. 1, 1a is a signal source for supplying an input signal, 20 is a capacitor, 21, 23, 2
6 and 30 are MOS field effect transistors (Metal Oxide
Semiconductor Field Effect Transistor: Hereinafter, simply referred to as FET. ), 22, 25, 27 and 29 are constant current sources, 24 and 28 are resistors, 31 is an operational amplifier, 32 is a constant voltage source, 33 is a variable voltage source, 100a is an input terminal,
1a is an output terminal, 102a is an offset voltage input terminal,
103 is a reference voltage input terminal.

Reference numerals 21 and 22 denote a source follower circuit 52, reference numerals 27 and 30 denote a source follower circuit 53, and 2
3 to 25 constitute an offset control circuit 54, 26, 28 and 29 constitute an offset control circuit 55, and 31 and 32 constitute a bias control circuit 56, respectively.

One end of the signal source 1a is connected to the input terminal 100a, and the input terminal 100a is connected to one end of the capacitor 20 and the FET.
The source of the FET 21 is connected to one end of the constant current source 22 and one end of the resistor 24, respectively.

The other end of the resistor 24 is connected to the output terminal 101a and to the other end of the capacitor 20, one end of the constant current source 25, and the drain of the FET 23, respectively.

The positive output terminal of the variable voltage source 33 is connected to the offset input terminal 102a, and the offset input terminal 102a is connected to the base of the FET 30. FET
The source of 30 is connected to one end of the constant current source 27 and one end of the resistor 28, respectively.

The other end of the resistor 28 is connected to one end of the constant current source 29, the drain of the FET 26, and the non-inverting input terminal of the operational amplifier 31, respectively.
Connected to the gates of ETs 23 and 26. The inverting input terminal of the operational amplifier 31 is connected to the reference voltage input terminal 103, and the reference voltage input terminal 103 is connected to the positive output terminal of the constant voltage source 32.

Further, the other end of the signal source 1a, the constant voltage source 32
And the negative output terminal of the variable voltage source 33 are grounded, respectively, and the other ends of the constant current source 22 and the constant current source 27 and F
The source of ET23 and FET26 is a positive voltage source "Vd
d ", respectively, and the constant current source 25 and the constant current source 2
9 and the drains of FET21 and FET30 are connected to a negative voltage source "Vss".

Here, the operation of the embodiment shown in FIG. 1 will be described. The signal component of the input signal input from the signal source 1a is directly output from the output terminal 101a via the capacitor 20. On the other hand, the DC component is output to the output terminal 101a via the source follower circuit 52 and the offset control circuit 54.

If the output voltage of the operational amplifier 31, which is the bias voltage of the FET 23, is a constant value, the control current "I23" flowing through the FET 23 also becomes a constant value, so that the output current of the constant current source 25 is changed to "I25". If the current flowing through the resistor 24 is “I24”, then I24 = I23−I25 (2)

Therefore, the resistance value of the resistor 24 is set to “R24”,
If the voltage drop at the resistor 24 is “V24”, then V24 = R24 · I24 = R24 · (I23−I25) (3)

That is, the voltage of the input signal is set to "Vi
n ′ ″, the voltage of the output signal is “Vout ′”, and the FET 21
Assuming that the voltage between the source and the gate is “Vsg21”, Vout ′ = Vin ′ + Vsg21 + V24 = Vin ′ + Vsg21 + R24 · (I23−I25) (4)

As can be seen from equation (4), the voltage "Vout '" of the output signal is a voltage obtained by adding a constant voltage to the voltage "Vin'" of the input signal. The value is controlled by the control current “I23”.

However, the second and subsequent terms in equation (4) fluctuate due to temperature fluctuations, power supply fluctuations, and the like. For example, FE
The value of the source-gate voltage “Vsg21” of T21 changes due to temperature fluctuation or the like, and the voltage drop “V24” at the resistor 24 also fluctuates due to the temperature coefficient of the resistor 24. Further, for example, the voltage between the drain and the source of the FET 21 changes due to the power supply fluctuation.
Also, the source-gate voltage “Vsg21” of 21 changes.

On the other hand, the DC component input from the variable voltage source 33 is output to the non-inverting input terminal of the operational amplifier 31 via the source follower circuit 53 and the offset control circuit 55. Output voltage of
Vofs ′ ″, the voltage of the non-inverting input terminal of the operational amplifier 31, in other words, the output of the offset control circuit 55 is “
Vp ”, and the source-gate voltage of the FET 30 is set to“ Vsg
Assuming that the voltage drop is 30 "and the voltage drop at the resistor 28 is" V28 ", Vp = Vofs' + Vsg30 + V28 (5)

The reference voltage of the constant voltage source 32 is applied to the inverting input terminal of the operational amplifier 31.
Is connected to the gate of the FET 26, and F
Since the drain of the ET 26 is connected to the non-inverting input terminal of the operational amplifier 31, the voltage “Vp” at the non-inverting input terminal of the operational amplifier 31 is not only affected by temperature fluctuations and power supply fluctuations but also by the output voltage of the variable voltage source 33. Constant voltage source 32 regardless of
Of the reference voltage.

That is, the reference voltage of the constant voltage source 32 is set to "V
ref ", Vp = Vref (6), and rewriting using the output voltage"Vofs'"of the variable voltage source 33, Vp = Vofs' + (Vref-Vofs') (7).

Therefore, the voltage "Vp" of the non-inverting input terminal of the operational amplifier 31 is controlled by the control operation of the operational amplifier 31 regardless of the influence of temperature fluctuation, power supply fluctuation, etc., with respect to the voltage applied to the offset input terminal 102a. T "(Vref
-Vofs') "is the added voltage.

Therefore, the source follower circuits 52 and 53
If the circuit constants are matched, the control current "I26" flowing through the FET 26 becomes I26 = I23 (8), and the voltage "Vout" of the output terminal 101a is controlled by the operational operation of the operational amplifier 31 such as temperature fluctuation or power supply fluctuation. Regardless of the influence, the voltage is obtained by adding "(Vref-Vofs')" to the voltage applied to the input terminal 100a.

That is, Vout '= Vin' + (Vref-Vofs') (9)

As can be seen from the equation (9), the source-follower circuit 53 and the bias control circuit 54 operate, for example, to set the source-gate voltage “Vsg21” of the FET 21.
And voltage fluctuations caused by temperature fluctuations and power supply fluctuations of the voltage drop “V24” in the resistor 24 are removed.

For this reason, the output signal voltage “Vout ′” is changed to the input signal voltage “V” regardless of temperature fluctuation and power supply fluctuation.
in '"plus a constant voltage"(Vref-Vofs')".

As a result, the operation of the source follower circuit 53 and the offset control circuit 54 to which the offset voltage is applied by the bias control circuit 54 is controlled, and the source follower circuit 52 and the offset control circuit 55 to which the input voltage is applied are set to the same condition. , It is possible to output a voltage obtained by adding a constant voltage to the voltage of the input signal irrespective of temperature fluctuations and power supply fluctuations.

Further, since the input signal is directly connected to the gate of the FET 21, the input resistance can be made almost infinite, and since there is no feedback in the signal passage, the waveform quality can be kept good, and The return at the time of input can be made faster than in the conventional example.

Further, since the circuit configuration is simple, the source follower circuits 52 and 53 and the offset control circuits 54 and 5
5 can be constructed on an IC in which matching of circuit constants is easy.

In the embodiment shown in FIG. 1, a MOS field effect transistor is exemplified as the FET, but the present invention is not limited to this.
An ESFET or the like may be used.

[0047]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. According to the first to sixth aspects of the present invention, the bias control circuit controls the operations of the second source follower circuit to which the offset voltage is applied and the second offset control circuit, and the first voltage to which the input voltage is applied. By controlling the source follower circuit and the first offset control circuit under the same conditions, it is possible to output a voltage obtained by adding a constant voltage to the voltage of the input signal irrespective of temperature fluctuations and power supply fluctuations.

Further, since the input signal is directly connected to the gate of the voltage effect transistor, the input resistance can be made almost infinite, and since there is no feedback in the signal passage, good waveform quality can be maintained. Also, recovery from an excessive input can be made faster than in the conventional example. Furthermore, since the circuit configuration is simple, it is possible to construct an IC on which the circuit constants of the source follower circuit and the offset control circuit can be easily matched.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram showing one embodiment of an offset adjustment circuit according to the present invention.

FIG. 2 is a configuration block diagram illustrating an example of a conventional offset adjustment circuit.

[Explanation of symbols]

1,1a Signal source 2,3,6,7,8,9,12,13,16,17,2
4,28 resistance 4,10,20 capacitance 5,11,31 operational amplifier 14 PNP transistor 15,32 constant voltage source 18 junction type field effect transistor 19,33 variable voltage source 21,23,26,30 MOS field effect transistor 22 , 25, 27, and 29 are constant current sources 50 DC buffer circuits 51, 52, 53 source follower circuits 54, 55 offset control circuits 56 bias control circuits 100, 100a input terminals 101, 101a output terminals 102, 102a offset voltage input terminals

Claims (6)

[Claims] 1. An offset adjustment circuit for adjusting a DC component of an input signal and outputting the input signal, a capacitor connecting the input signal to an output terminal, a first source follower circuit receiving the input signal, A first offset control circuit for controlling an offset of an output of the first source follower circuit and outputting the output to the output terminal; a second source follower circuit to which a variable voltage is input; and an output of the second source follower circuit A second offset control circuit that controls the offset of the first and second offset control circuits, and a bias control circuit that supplies a bias voltage to the first and second offset control circuits so that an output of the second offset control circuit becomes a reference voltage. An offset adjustment circuit, comprising: 2. A first source follower circuit comprising: a first voltage effect transistor having a drain connected to a negative voltage source and the input signal being input to a gate; and a first voltage effect transistor having one end connected to a positive voltage source and the other end connected to a positive voltage source. 2. The offset adjustment circuit according to claim 1, further comprising a first constant current source connected to a source of said first voltage effect transistor. 3. The second source follower circuit includes: a second voltage effect transistor having a drain connected to a negative voltage source and the variable voltage input to a gate; and a second voltage effect transistor having one end connected to a positive voltage source and the other end connected to a positive voltage source. 2. The offset adjustment circuit according to claim 1, further comprising a second constant current source connected to a source of said second voltage effect transistor. 4. The first offset control circuit comprises: a first resistor having an output connected to one end of the first source follower circuit; and a first resistor having a source connected to a positive voltage source.
A third voltage effect transistor having the other end of the resistor connected to the drain and the output of the bias control circuit connected to the gate, and one end connected to the negative voltage source and connected to the drain of the third voltage effect transistor. 2. The offset adjustment circuit according to claim 1, further comprising a third constant current source connected to the other end. 5. The second offset control circuit comprises: a second resistor having an output connected to one end of the second source follower circuit; and a second resistor having a source connected to a positive voltage source.
A fourth voltage effect transistor having the other end connected to the drain and the output of the bias control circuit connected to the gate; and a fourth end connected to the negative voltage source and connected to the drain of the fourth voltage effect transistor. 2. The offset adjustment circuit according to claim 1, further comprising a fourth constant current source connected to the other end. 6. The constant voltage source for outputting the reference voltage, wherein the output of the second offset control circuit is connected to a non-inverting input terminal, and the reference voltage is connected to an inverting input terminal. 2. The offset adjustment circuit according to claim 1, further comprising an operational amplifier whose output is supplied as a bias voltage to said first and second offset control circuits.