JP2000294806A - Retiming circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a retiming circuit operative at a high speed over 100 GHz. SOLUTION: When a clock light is cast on a light absorptive layer 205, electron-hole pairs are generated to change the carrier density in this layer, causing the characteristic impedance of an electric signal transmission line 102 to be changed and hence the electric signal transmission speed to be changed, thus synchronizing data signals with the clock light. Among the electron-hole pairs generated by the light excitation, the electrons are extracted from a buffer layer 204, an electron running layer 203 and electron extraction layer 202 to extract electrodes 105, 106, while the holes are extracted from a diffusion buffer layer 206 to ground electrodes 103, 104 and the lives of these electrons and holes are short, independent of the recombination life.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a retiming circuit for synchronizing an electric data signal with a clock signal, and more particularly to a retiming circuit for achieving high speed.

[0002]

2. Description of the Related Art A retiming circuit is an indispensable element circuit for constituting a digital logic circuit.
This has been realized by a flip-flop circuit combining active elements such as a plurality of transistors. However, in a circuit in which a plurality of active elements are combined, the operation speed is limited to about 30% of the performance of the active element used, and the clock interval is as short as the data delay time required for the feedback loop operation in the circuit. It has been very difficult to realize a retiming circuit operating at, for example, 100 GHz for two reasons: the circuit does not operate stably.

In order to solve these problems, a substrate between an electric signal transmission line for transmitting a data signal and a ground or DC power supply electrode is used as a semiconductor substrate, and the semiconductor substrate is irradiated with a clock light signal. A retiming circuit that modulates the capacitance between the electric signal transmission line and the ground or DC power supply electrode and synchronizes the data signal with the clock light signal has been proposed in Japanese Patent Application No. 9-218986. I have.

FIG. 5 is a configuration diagram showing this conventional example. 1
101 is a semiconductor substrate, 1102 is a transmission line for data signals, 1103 and 1104 are lines (electrodes) to which ground or voltage is applied, and 1105 is an optical waveguide.

Now, the inductance component per unit length of the transmission line 1102 in the absence of clock light is represented by L
Assuming that o and the capacitance component per unit length are Co, the propagation speed v of the electric signal on the transmission line 1102 at this time is given by: v = 1 / (Lo · Co) (1)

In this circuit, when the optical waveguide 1105 is irradiated with clock light, the light leaking from the optical waveguide 1105 is absorbed by the semiconductor substrate 1101, so that electron-hole pairs are formed in the semiconductor. The generated transmission lines 1102 and the lines 1103 and 11 to which ground or voltage is applied
When the electric field between the electric field and the electric field 04 changes, the depletion layer capacitance increases to “Co + ΔC” as shown in FIG. At this time, the propagation velocity v ′ of the electric signal on the transmission line is given by v ′ = 1 / [Lo · (Co + ΔC)] (2) using equation (1). Will decrease,
The propagation speed of the electric signal can be modulated by the presence or absence of light.

Therefore, the intensity of the clock light signal is represented by a sine wave as shown in FIG.
Consider a retiming circuit in which the transmission line is designed such that the propagation speed of the signal traveling wave on the transmission line 1102 at the time of m is equal to the speed of light in the optical waveguide.

In this case, the hatched portion in FIG. 7 indicates that the propagation speed of the electric signal becomes slower than that of the clock light due to the increase in the depletion layer capacitance due to light irradiation, and the unmarked portion conversely causes the propagation of the electric signal due to the decrease in the depletion layer capacitance. The speed becomes faster than the clock light, and the two speeds coincide at the boundary (Im) between the hatched portion and the unmarked portion.

Therefore, at the input end of such a retiming circuit, at a timing as shown in the timing chart of FIG.
When an electric data signal having a timing jitter within 1/4 clock is input, an electric data signal synchronized with the clock light can be obtained at the output end, as shown in FIG. 8B.

Since such a retiming circuit does not use any active elements, there is no band limitation due to the performance of the active elements, and there is no feedback in the circuit, so that there is no speed limitation due to feedback delay. Operation becomes possible.

[0011]

However, the electron-hole pairs generated in the semiconductor by light irradiation do not disappear at the moment when the light irradiation is stopped. By recombination, energy corresponding to the band gap of the semiconductor is released into the semiconductor in the form of light or heat and disappears. This recombination process is stochastic, and the average time until the electron-hole pairs recombine is called the recombination lifetime, and is assumed to be used as a semiconductor in this retiming circuit. In the case of high-purity GaAs or InGaAs, the recombination lifetime is about 100 ps to 1 ns at room temperature.

In the conventionally proposed retiming circuit, since the depletion layer capacitance needs to change following the input clock frequency, the reciprocal of the input clock needs to be larger than the recombination life of the electron-hole pair. is there. Therefore, when a retiming circuit is manufactured using a compound semiconductor having high purity, the operating frequency is at most about 10 GHz.

[0013] The semiconductor in the retiming circuit
As a technique for shortening the recombination lifetime of a hole pair, it is conceivable that the semiconductor is doped with an impurity or the like which serves as a recombination center in advance to facilitate recombination. The heat generated in the semiconductor due to the bonding gives kinetic energy to the remaining electron-hole pairs and hinders recombination, so the annihilation rate of the electron-hole pairs immediately after the light irradiation stops is high. However, as the time elapses, the extinction rate decreases, and this cannot be a method of effectively increasing the operating frequency of the retiming circuit.

As described above, in the conventional retiming circuit, the recombination life of the electron-hole pairs in the semiconductor becomes the upper limit of the clock frequency, and it is very difficult to further increase the speed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to eliminate electron-hole pairs in a semiconductor at a high speed without causing heat to accumulate in the semiconductor.
An object of the present invention is to provide a retiming circuit that can operate at a high speed of not less than Hz.

[0016]

According to a first aspect of the present invention, a substrate between an electric signal transmission line for transmitting a data signal and a ground or DC power supply electrode is provided as a semiconductor substrate. Irradiating the substrate with clock light,
In a retiming circuit for modulating a capacitance between the electric signal transmission line and the ground or DC power supply electrode and synchronizing a data signal with a clock light, a layer structure of a semiconductor substrate immediately below the electric signal transmission line may have a band gap. A first semiconductor layer of a first conductivity type whose energy is smaller than the energy of the clock light; and a second semiconductor layer of a second conductivity type whose band gap energy is larger than the energy of the clock light and opposite to the first conductivity type. A second semiconductor layer and a lower impurity doping concentration than the first and second semiconductor layers between the first and second semiconductor layers, or a bandgap energy larger than the clock light energy without impurity doping. A third semiconductor layer, and a bandgap disposed in contact with the first semiconductor layer and on an opposite side of the third semiconductor layer. A first conduction type fourth semiconductor layer having a higher tap energy than the clock light energy, the ground or DC power supply electrode is ohmic-connected to the fourth semiconductor layer, and the second semiconductor layer is An ohmic extraction electrode, at least an insulating layer between the electric signal transmission line and the first semiconductor layer, and a structure in which the input clock light is absorbed by the first semiconductor layer. .

According to a second aspect of the present invention, in the first aspect, a bridge electrode is provided to connect between the ground or DC power supply electrode and the ohmic extraction electrode.

According to a third invention, in the first or second invention, between the first semiconductor layer and the third semiconductor layer,
A fifth semiconductor layer of the second conductivity type having the same impurity concentration as that of the first semiconductor layer and having a smaller thickness than the first semiconductor layer and the third semiconductor layer is provided.

According to a fourth aspect, in the first to third aspects, the second semiconductor layer is formed on an upper surface of a substrate, and an antireflection film is formed on a back surface of the substrate.

In a fifth aspect based on the first to third aspects, the band gaps of the semiconductor layers above and below the first semiconductor layer are gradually increased, and the optical refractive index of the first semiconductor layer is increased. The upper and lower semiconductor layers were made larger than those.

[0021]

FIG. 1 is a diagram showing a configuration of a retiming circuit according to one embodiment of the present invention. In the figure, 101 is a semiconductor substrate, 102 is a transmission line of a data signal,
Reference numerals 103 and 104 denote ground electrodes (or DC power supply electrodes) for extracting photoexcited holes formed with a coplanar transmission line having a predetermined characteristic impedance in combination with the transmission line 102, and 105 and 106 depict photoexcited electrons. Extraction electrodes 107 and 108 are electrodes 103 and 105
And a bridge electrode for maintaining the same potential between the electrodes 104 and 106.

FIG. 2 shows the retiming circuit of FIG.
It is sectional drawing cut | disconnected by the surface. In FIG.
From semi-insulating InP with mirror-polished surfaces on the opposite side
A semiconductor substrate 202 having an n-type impurity of 2 × 10¹⁸cm^-3Is
Electron extraction layer (second semiconductor)
Layers 203) and 203 have a lower impurity concentration than the electron extraction layer 202.
Consisting of semi-insulating InP with no or no doping
The electron transit layer (third semiconductor layer) 204 contains n-type impurities
2 × 10¹⁸cm^-3Doped InP with a thickness of about 10 nm
Buffer layer (fifth semiconductor layer) 205, p-type impurity
2 × 10¹⁸cm^-3Only Doped In_0.53Ga_0.47Light consisting of As
The absorption layer (first semiconductor layer) 206 is composed of 4 × 1 p-type impurities.
0¹⁹cm^-3Only Doped In_0.6Ga_0.4As_0.85P_0.15Consisting of
Diffusion barrier layer (acts as a barrier to electrons by diffusing holes
Fourth semiconductor layer), 207 is SiO ₂An insulating layer consisting of
208 is SiO₂/ TiO_TwoAnti-reflective coating made of
You. These substrates, layers or films 201 to 208 correspond to those of FIG.
A part of the semiconductor substrate 101 is formed.

Of the substrates, layers or films 201 to 208, the light absorption layer 205 has a band gap energy smaller than that of the clock light, and the others are larger. The buffer layer 204 is thinner than the other layers 202, 203, 205, 206. In addition, the ground electrodes 103 and 104 are
06, and the extraction electrodes 105 and 106 are also in ohmic contact with the electron extraction layer 202.

FIG. 3 shows the retiming circuit of FIG.
FIG. 4 is a potential diagram showing a potential of each layer when viewed in a direction. The buffer layer 204 makes the potentials of the electron traveling 203 and the light absorbing layer 205 substantially continuous.

In this circuit, after the layers 202 to 206 are grown on a semiconductor substrate 201 made of semi-insulating InP by metal organic chemical vapor deposition or molecular beam epitaxy, unnecessary portions are removed by etching. The electrodes 103 to 106 and the insulating film 207 are deposited by a metal lift-off method and a chemical vapor deposition method, and an anti-reflection film 208 is deposited.

In the retiming circuit of the present invention, when clock light having a wavelength of 1.55 μm is input from the back surface (lower surface) of the semiconductor substrate 101, the light is transmitted to the anti-reflection film 20.
8, substrate 201, electron extraction layer 202, electron transit layer 20
Third, the light passes through the buffer layer 204 without attenuation, is absorbed by the light absorbing layer 205, and is converted into an electron-hole pair. Here, since the light absorption layer 205 is doped with a p-type impurity and has holes before light irradiation, electrons and holes generated by light irradiation are called minority electrons and excess holes, respectively. These light-excited carriers lower the resistivity of the light-absorbing layer 205 and can be regarded as a conductor.

Since the light absorption layer 205 is connected to the ground electrodes 103 and 104 via the diffusion barrier layer 206,
When light is irradiated, a capacitance component generated between the signal transmission line 102 and the ground electrodes 103 and 104 increases. Accordingly, the speed of the electric data signal transmitted through the signal transmission line 102 has a relationship as shown in FIG. 4 with respect to the clock light intensity, and even when an electric data signal having timing jitter is input, the speed of the clock light signal is reduced. Synchronized electrical data signals can be extracted.

The minority electrons generated in the light absorption layer 205 are diffused and drifted and travel through the semi-insulating InP electron transit layer 203 and the n-type InP electron extraction layer 202 to the extraction electrodes 105 and 106. To be taken out. Excess holes generated in the light absorption layer 205 are extracted to the ground electrodes 103 and 104 via the diffusion barrier layer 206 by dielectric relaxation movement.

Therefore, the lifetime of the minority electrons and excess holes generated in the light absorption layer 205 does not depend on the recombination lifetime.
In this case, the time until the minority electrons and excess holes disappear from the light absorbing layer 205 is 1 time longer than the hole dielectric time of this layer.
It is determined by the diffusion time of a few electrons which is about an order of magnitude larger, but the paper "IEEE Photonics Technology Letters, Vo1.
10, p. 412-414, 1998,
By appropriately designing the structure of the light absorption layer 205, 2 ps
It is possible to do.

Therefore, it is possible to operate this retiming circuit even for a clock light of 100 GHz or more.

In this embodiment, since the wavelength of the clock light is assumed to be 1.55 μm, the semiconductor material is
InGaAsP system was used. However, the present invention is not limited to this. If the light absorption layer is formed of GaAs and the other layers are formed of AlGaAs, a suitable re-timing circuit can be formed, for example, when a light having a wavelength of 0.85 μm is used as clock light. It is clear that the clock light wavelength can be set to a value other than 1.55 microns by selecting a group V compound semiconductor.

In this embodiment, the clock light is emitted from the back surface of the semiconductor substrate 101 in a direction perpendicular to the signal transmission direction. However, the present invention is not limited to this. By gradually increasing the band gap of the portion, the refractive index of the light absorbing layer 205 is made larger than that of the upper and lower semiconductor layers 204 to 206, and directly below the transmission line 102 in the longitudinal direction of the transmission line 102. By forming an extending optical waveguide structure, it is also possible to adopt a structure in which light is irradiated from the lateral direction of the signal transmission direction (the direction perpendicular to the paper surface of FIG. 2).

Although the conductivity type of each semiconductor layer shown in FIG. 2 is reversed (p-type is changed to n-type and n-type is changed to p-type), the same operation can be performed. At this time, the diffusion barrier layer 206 functions as a barrier for holes and guides electrons to the electrodes 103 and 104 for electrons. Electron extraction layer 20
2 becomes a hole extraction layer.

Although the buffer layer 204 is provided in the retiming circuit shown in FIG. 2, it is not necessary when a material is used in which the conduction band of the light absorption layer 205 and the electron transit layer 203 is substantially continuous. .

Further, the bridge electrode 107 connecting between the electrodes 103 and 105 and the bridge electrode 108 connecting between the electrodes 104 and 106 do not necessarily need to be provided in the present retiming circuit.
The connection between the electrodes 05 and 05 and the connection between the electrodes 104 and 106 may be made.

[0036]

According to the present invention, when clock light is applied to the light absorbing layer to generate electron-hole pairs, the characteristic impedance of the electric signal transmission line is changed by the change in carrier density in this layer. It changes, the transmission speed of the electric signal changes, and the data signal is synchronized with the clock optical signal, thereby enabling retiming.

Further, the generated electron-hole pairs are quickly absorbed by the extraction electrode and the ground or DC voltage application electrode, respectively, and thus do not depend on the recombination lifetime of the semiconductor substrate.
Since the electron-hole pairs in the semiconductor can be eliminated at high speed without causing heat accumulation in the semiconductor substrate,
Higher speeds of 100 GHz or more can be easily realized.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration of a retiming circuit according to one embodiment of the present invention.

FIG. 2 is a sectional view taken along line A-A 'of FIG.

FIG. 3 is a potential distribution diagram of each layer along a line BB ′ in FIG. 2;

FIG. 4 is an explanatory diagram showing a relationship between a clock light intensity incident on the retiming circuit of the embodiment of the present invention and a transmission speed of an electric data signal transmitted through a signal transmission line.

FIG. 5 is a perspective view showing a configuration of a conventional retiming circuit.

FIG. 6 is an explanatory diagram showing a relationship between clock light intensity and depletion layer capacitance in a conventional retiming circuit.

FIG. 7 is an explanatory diagram showing the relationship between clock light intensity and electric data signal transmission speed in a conventional retiming circuit.

FIGS. 8A and 8B are explanatory diagrams showing the relationship between clock light, an input electrical data signal, and an output data electrical signal in a conventional retiming circuit.

[Explanation of symbols]

101: semiconductor substrate, 102: transmission line for data signal,
103, 104: ground electrode, 105, 106: extraction electrode for extracting photoexcited electrons, 107, 108: bridge electrode 201: semiconductor substrate made of semi-insulating InP, 202: n
Electron extraction layer made of InP doped with n-type impurities, 20
3: electron transit layer made of semi-insulating InP, 204: buffer layer made of InP doped with n-type impurity, 205: light-absorbing layer made of In _{0 .53} Ga _0.47 As doped with P-type impurities, 20
6: a diffusion barrier layer made of _{In 0.6 Ga 0.4 As 0. 85 P} 0.15 doped with P-type impurity, 207: insulating layer made of SiO _2, 20
8: antireflection film made of SiO ₂ / TiO _2, SiN, etc.

Claims (5)

[Claims] A substrate between an electric signal transmission line for propagating a data signal and a ground or DC power supply electrode is used as a semiconductor substrate, and the semiconductor substrate is irradiated with clock light so that the electric signal transmission line is connected to the electric signal transmission line. In a retiming circuit that modulates a capacitance between a ground or a DC power supply electrode and synchronizes a data signal with a clock light, a layer configuration of the semiconductor substrate immediately below the electric signal transmission line has a bandgap energy whose energy is the energy of the clock light. A first semiconductor layer of a smaller first conductivity type and a second semiconductor layer of a second conductivity type having a bandgap energy larger than the energy of the clock light and opposite to the first conductivity type.
A semiconductor layer having a lower impurity doping concentration between the first and second semiconductor layers and having a lower impurity doping concentration than the first and second semiconductor layers, or having a band gap energy larger than the energy of the clock light without impurity doping. 3
A first conductive type fourth semiconductor layer having a bandgap energy larger than the clock light energy and disposed on the opposite side of the third semiconductor layer in contact with the first semiconductor layer. The ground or DC power supply electrode is ohmic-connected to the fourth semiconductor layer, the second semiconductor layer has an ohmic extraction electrode, and is provided between the electric signal transmission line and the first semiconductor layer. Wherein at least an insulating layer is present, and the input clock light is absorbed by the first semiconductor layer. 2. The retiming circuit according to claim 1, further comprising a bridge electrode connecting between the ground or DC power supply electrode and the ohmic extraction electrode. 3. The semiconductor device according to claim 1, wherein said first semiconductor layer and said third semiconductor layer have an impurity concentration substantially equal to that of said first semiconductor layer and between said first semiconductor layer and said third semiconductor layer. The retiming circuit according to claim 1 or 2, wherein a fifth semiconductor layer of the second conductivity type having a small thickness is interposed. 4. The retiming circuit according to claim 1, wherein said second semiconductor layer is formed on an upper surface of a substrate, and an antireflection film is formed on a back surface of said substrate. 5. The semiconductor device according to claim 1, wherein the band gaps of the semiconductor layers above and below the first semiconductor layer are gradually increased, and the refractive index of the first semiconductor layer is made larger than that of the upper and lower semiconductor layers. 4. The retiming circuit according to claim 1, wherein: