JP2000293552A - Hardware design management device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a hardware design management device capable of managing the design of hardware by using a natural language as a language to be normally used for a designer. SOLUTION: This hardware design management device 112 is arranged together with plural work stations 1131 to 113N and personal computers 1141 to 114N owned by respective designers. The device 112 is provided with a data base for regulating the inherent names of respective constitutional parts of a circuit device to be designed and I/O relation. A designer inputs a sentence consisting of a natural language expressing respective constitutional parts of the circuit device from his (or her) own machine to retrieve the constitutional parts. When the constitutional parts have been already registered in the data base, the registered contents are used, and when no constitutional part is registered, the constitutional parts are decomposed to lower constitutional parts and design is executed by utilizing the data base. New designed constitutional parts are registered in the data base so as to utilize design resources.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a hardware design management apparatus for managing hardware design, and more particularly, to a hardware design capable of managing hardware design using a natural language. Regarding the management device.

[0002]

2. Description of the Related Art On the basis of circuit design requirements, designers design hardware such as electronic circuits that satisfy the requirements. Now, suppose that a design of "a device for multiplexing two North American digital tertiary group signals and multiplexing them into a quaternary group signal by a stuff synchronization method" is required. In this case,
Usually, a designer first designs an outline of a circuit that satisfies the requirements.

FIG. 16 shows an example of a circuit configuration as an outline of such an apparatus. This device comprises first and second stuff synchronization circuits 11 and 12 for multiplexing two North American digital tertiary group signals, and a multiplexing circuit 13 disposed at the subsequent stage. After the designer constructs a circuit as shown in FIG. 16, the individual stuff synchronization circuits 11 and 12 and the multiplexing circuit 13
A circuit that satisfies those input / output conditions will be embodied.

That is, for example, with respect to the first stuff synchronization circuit 11, a designer designs a circuit using a clock extraction circuit, a write counter, a buffer memory, a read counter, and other circuits. In this case, the designer further specifies the circuit configuration of the write counter or the like at the next stage, or requests another designer to realize the specified circuits as necessary.

In designing a logic circuit, a specific circuit can be created on the basis of such information by creating a state transition diagram or a flowchart, or by using a function description language. Further, for example, Japanese Patent Application Laid-Open No. 7-2
As disclosed in Japanese Patent No. 25783, it has also been proposed to generate a function description language by using figures, symbols, and characters, and to create a specific circuit based on the function description language.

[0006] When the design of one device is completed in this way, the designer saves data on the circuit or device designed at that time in a physical or electronic folder on his desk. And when there is a request for the next design,
When necessary, the data accumulated in the past was used personally to design hardware.

[0007]

The design of new hardware requires the brain activity of the person in charge. Brain activity is unique and depends on the knowledge and experience of each individual. Therefore, when designing individual circuits that constitute one device, it is usual for each designer to have individuality. For this reason,
In the past, hardware design was completely left to the individual and it was extremely difficult for one designer to design the hardware and use the results of the other design in another design. Was.

For this reason, when designing hardware that is similar to hardware once designed, it is requested to a designer in charge in advance and the previously filed data is used to reduce waste. It can be avoided. If a new designer, who was unrelated to the technology, was in charge of the circuit design due to a change of designer, etc., the same circuit design as the previously created circuit would be duplicated, resulting in considerable waste of time and effort. There was a problem that occurs. For example, after the previous designer has designed the apparatus shown in FIG. 16, the other designers are asked to multiplex three North American digital tertiary group signals and multiplex them into a quaternary group signal by a stuff synchronization method. That is the case when the design of the device is required. This is because there is only a difference between “multiplexing two North American digital tertiary group signals” or “multiplexing three North American digital tertiary group signals”.

FIG. 17 shows an outline of an example of an apparatus for realizing the latter request. This apparatus comprises first, second, and third stuff synchronization circuits 21, 22, and 23 for multiplexing three tertiary group signals of a North American digital system, and a multiplexing circuit 24 disposed at the subsequent stage thereof. can do. After constructing the circuit as shown in FIG. 17, the designer implements a circuit that satisfies the input / output conditions for each of the stuff synchronization circuits 21 to 23 and the multiplexing circuit 24.

However, depending on input / output conditions, the first, second, and third stuff synchronization circuits 21, 22, and 23 are replaced with the first and second stuff synchronization circuits 11, 22 shown in FIG.
12 can have the same or almost the same circuit configuration. Further, in the case of the same circuit configuration, it may be possible to design a more detailed circuit for realizing it as a unique circuit, but the circuit obtained when the circuit of FIG. Diversion is also possible. FIG.
When the circuit such as the stuff synchronization circuit 21 shown in FIG. 7 has substantially the same circuit configuration as the stuff synchronization circuit 11 shown in FIG. 16, for example, a part of the circuit that embodies the stuff synchronization circuit shown in FIG. It is highly possible that at least a part of the circuit embodying the synchronization circuit 11 can be configured with the exact same circuit.

However, in the past, as described above, from the viewpoint that the thinking content when humans configure hardware is unique, it is necessary to utilize the already designed circuit device for the design work of another person. Was not considered much. For this reason, considering companies and laboratories, there is considerable waste in hardware design,
For this reason, there has been a problem that the development cost of the apparatus and the speed up to the development cannot be made efficient.

[0012] Of course, the background of such a problem is that the function description language described above as a tool for transmitting a development request to a designer is difficult to use for each person's daily design. .

It is an object of the present invention to provide a hardware design management device capable of efficiently managing hardware design.

Another object of the present invention is to provide a hardware design management device that can utilize the asset value of hardware design.

Still another object of the present invention is to provide a hardware design management device capable of managing a hardware design using a natural language as a language which a designer usually uses. .

[0016]

According to the first aspect of the present invention, (a) the unique names of the components constituting the hardware, the signals input to those components, and the signals output from the components are described. Sentence input means for inputting a sentence composed of natural language sentences, (b) extracting means for extracting terms indicating names and input / output of signals from sentences input by the sentence input means, The hardware design management device is provided with circuit device generation means for generating circuit devices by connecting the components extracted by the extraction means in a relation meaning of terms indicating signal input / output.

That is, according to the first aspect of the present invention, when designing hardware, the unique names of the components constituting the hardware from the text input means, the signals input to those components, and the components and the like. The signal output from is composed of sentences composed of natural language and input. Then, the extraction means extracts the names of the components and the terms indicating the input / output of each component, and connects the components in relation to the input / output of signals to design hardware that satisfies a predetermined input / output relationship. I have decided. Each component has a unique name. For example, if a counter circuit satisfies a certain input / output characteristic, once the unique name is given, the circuit with that name is used as it is. can do. Moreover, since the natural language is used to specify the components, the hardware can be designed without using any special language.

According to the second aspect of the present invention, (a) the unique names of the components constituting the hardware, the signals input to those components, and the signals output from the components are written in sentences composed of natural languages. Sentence inputting means for inputting the composed one; (b) extracting means for extracting terms indicating the input and output of names and signals from the sentence input by the sentence inputting means; and (c) extracted by the extracting means. (D) a circuit device generating means for generating a circuit device by connecting component parts in a relationship defined by a term indicating input / output of a signal;
Display means for displaying the circuit device generated by the circuit device generation means; and (e) correcting the text input from the text input means when the circuit device displayed by the display means is defective. The hardware design management device is provided with correction means for correcting the circuit device generated by the means.

That is, according to the second aspect of the present invention, when designing the hardware, the unique names of the components constituting the hardware from the text input means, the signals input to the components, and the components and the like. The signal output from is composed of sentences composed of natural language and input. Then, the extraction means extracts the names of the components and the terms indicating the input / output of each component, and connects the components in relation to the input / output of signals to design hardware that satisfies a predetermined input / output relationship. I have decided. Each component has a unique name. For example, if a counter circuit satisfies a certain input / output characteristic, once the unique name is given, the circuit with that name is used as it is. can do. Moreover, since the natural language is used to specify the components, the hardware can be designed without using any special language. Also, the circuit configuration of the circuit device generated based on the input of the natural language is displayed on the display means, so if a circuit device having desired characteristics is not displayed due to a defect such as language expression or the like. This can be corrected by the correction means, and a satisfactory circuit device can be realized by natural language input.

According to the third aspect of the present invention, (a) for each component constituting the hardware, the condition that the input signal to be inputted to the component and the condition that the output signal should have and the component are realized. A database registered and given a unique name in association with the circuit device to be
(B) input means for inputting a condition of an input signal and a condition of an output signal for each component for configuring desired hardware; and (c) an input signal input by the input means. And (d) searching for a component that satisfies all of the conditions of the output signal from the database; A design data acquisition means for acquiring from a database to omit the design,
(E) For the component parts that do not match by the search means, input the conditions that the input signal has and the conditions that the output signal should have for each of the more specific components realizing the component to the input means. Then, the hardware design management device is provided with a component part materialization control unit that realizes the materialization of the component parts until the lower layer component parts exist in the database.

That is, according to the third aspect of the present invention, for each of the components constituting the hardware, the conditions for the input signals and the conditions for the output signals to be input to the components and the circuit for realizing the components are provided. A database is prepared which is registered with a unique name given in association with the device. When designing a new circuit device, the input / output relationship of each component constituting the circuit device is clarified so that it can be searched whether or not such a component is already registered in the database. ing. As a result of the search, if all or a part of the components constituting the circuit device are registered in the database, the design of those components can be omitted. In such a case, the design data may be obtained from the database by the design data obtaining means.

On the other hand, as a result of the search, a component found to be a new component not registered in the database is embodied by realizing the component using the component embedment control means. Also, input the conditions that the input signal has and the conditions that the output signal should have for each component to the input means, and make the components concrete until the components in the lower layer exist in the database. I have. In other words, even if the circuit device to be designed is a new one, if it is decomposed in order to the constituent components that make up the component device or the lower-level components that make up the component component, the resistance and By identifying the combination of component parts based on the principle of reaching a component part with a basic input / output characteristic like an AND circuit,
A new circuit device is designed while making the best use of known components from a database.

According to the fourth aspect of the present invention, (a) for each of the components constituting the hardware, the conditions of the input signals and the conditions of the output signals to be input to the components and the components thereof are realized. A database registered and given a unique name in association with the circuit device to be
(B) input means for inputting a condition of an input signal and a condition of an output signal for each component for configuring desired hardware; and (c) an input signal input by the input means. And (d) searching for a component that satisfies all of the conditions of the output signal from the database; A design data acquisition means for acquiring from a database to omit the design,
(E) For the component parts that do not match by the search means, input the conditions that the input signal has and the conditions that the output signal should have for each of the more specific components realizing the component to the input means. Then, the component materialization control means for realizing the component parts until the lower-level component parts exist in the database, and (f) the component materialization control means, a certain higher-level component part is stored in the database. A name assigning means for assigning a unique name by associating the higher order component with the lower order component when all the components are embodied by existing lower order components; The hardware design management device is provided with database registration means for registering the named hardware as one component in the database. That.

In other words, according to the present invention, for each of the components constituting the hardware, the conditions for the input signals and the conditions for the output signals to be input to the components and the circuit for realizing the components are provided. A database is prepared which is registered with a unique name given in association with the device. When designing a new circuit device, the input / output relationship of each component constituting the circuit device is clarified so that it can be searched whether or not such a component is already registered in the database. ing. As a result of the search, if all or a part of the components constituting the circuit device are registered in the database, the design of those components can be omitted. In such a case, the design data may be obtained from the database by the design data obtaining means.

On the other hand, as a result of the search, a component which is found to be a new component not registered in the database is embodied by realizing the component using the component embedment control means. Also, input the conditions that the input signal has and the conditions that the output signal should have for each component to the input means, and make the components concrete until the components in the lower layer exist in the database. I have. In other words, even if the circuit device to be designed is a new one, if it is decomposed in order to the constituent components that make up the component device or the lower-level components that make up the component component, the resistance and Based on the principle of reaching a component with a basic input / output characteristic such as an AND circuit, the combination of components is specified, and when that combination is finally realized by a known component The circuit device is provided as a component and a unique name is given to the circuit device by a name giving means.
Then, this component is registered in the database by the database registration means from the viewpoint of utilizing design resources. In this way, the contents of the database are enriched and the components of all levels are provided, so that it is possible to save the labor of designing circuit devices and components having the same input / output characteristics.

According to a fifth aspect of the present invention, in the hardware design management device according to the third or fourth aspect, the condition of the input signal input from the input means and the condition of the output signal are in a natural language. It is characterized by being described.

In other words, according to the present invention, the input / output characteristics of the component parts are input in a natural language and analyzed by the input / output characteristics, which are now improved in the input text analysis technology.
The aim is to realize a hardware design management device that facilitates input processing and can be used by any designer.

According to a sixth aspect of the present invention, in the hardware design management device of the first to fourth aspects, the natural language extracts nouns as components or signal names and extracts verbs between components. It is characterized in that it is extracted as meaning connection.

That is, in the invention according to claim 6, as a method of specifying a component from the input natural language, the name of the component, the name of the signal or the signal line is extracted by extracting the noun in the text. For the arrival path or connection of a signal, a verb is extracted and analyzed to identify a combination of component verbs.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows a configuration of a hardware design management system using a hardware design management device according to an embodiment of the present invention. The hardware design management system of the present embodiment includes a hardware design management device 112 arranged on a LAN (local area network) 111 and a plurality of workstations (WS) 113 ₁ to 113 similarly arranged on the LAN 111. 113 _N or multiple personal computers (PCs) 114 ₁
It can be constructed from ~114 _M. Here, the workstations 113 _{1 to} 113 _N and the personal computers 114 _{1 to} 114 _M are information terminals used by the designer for designing hardware.

In some cases, the designer uses an information terminal on another network 115 different from the LAN 111. In such a case, the communication server 116 or a designer's workstation or personal computer (both not shown) is connected to and integrated using a communication means such as a modem or router (not shown). It is also possible to configure a hardware design management system. That is, the hardware design management device 1 of the present invention
Reference numeral 12 is effective even when used in a relatively narrow range such as an individual or a single department, but by arranging it in a system in which a plurality of offices and the like are connected, information obtained by hardware design is obtained. , And more efficient hardware design management can be performed.

In this embodiment, the hardware design management device 112 is provided with storage means for storing data relating to hardware design and other data. We are trying to unify it. In the system configuration of the present embodiment, the workstation 113 ₁ is provided by providing the hardware design management device 112 that performs hardware design management exclusively.
~ 113 _N or personal computer 114 ₁ ~ 114 _M
, And it is also possible to use an information terminal having a simpler function. In this way, not only can one device centrally manage data related to hardware design, but also a dedicated server that stores only such data can be independently arranged on a network.

FIG. 2 shows an outline of the configuration of the hardware design management device of this embodiment. The hardware design management device 112 is a CPU having its central function.
(Central processing unit) 121. The CPU 121 operates through a bus 122 such as a data bus or the like, and
M) 123, an input circuit 124, a display control circuit 125, a disk control circuit 126, a communication control circuit 127, and a printer control circuit 128.

The input circuit 124 includes the keyboard 13
1 and a mouse 132 as a pointing device
And various data input. The display control circuit 125 is connected to a display (monitor) 133 such as a liquid crystal display, and visually outputs necessary information. The disk control circuit 126 is connected to a disk device such as a magnetic disk or an optical disk. The disk device 134 not only stores programs necessary for controlling the hardware design management device 112, but also stores a database for designing hardware. The communication control circuit 127 is connected to a communication cable forming the LAN 111, and
31 _{1 to} 113 _N and personal computers 114 _{1 to} 11
4 and performs transmission and reception of data to and from the _M.
The printer control circuit 128 controls the printer 136 to print out desired print data.

The designer works with the workstations 113 _1-
By accessing the hardware design management device 112 by operating the 113 _N and the personal computers 114 _{1 to} 114 _M , the resources of the past hardware can be utilized and the hardware design work can be performed using the natural language. Do. Of course, it is also possible to go directly to the hardware design management device 112 and directly operate it to perform the design work.

Now, it is assumed that a design for "an apparatus for multiplexing three North American digital tertiary group signals and multiplexing them into a quaternary group signal by a stuff synchronization system" as described with reference to FIG. 17 is required. . In a system using the hardware design management device of the present embodiment, the device is designed using a natural language, and if the device or circuit required at that time is new, the designer Are given sequentially. If a device or circuit to be designed exists in the database in the disk device 134 as an existing one, the design is saved as it is to save labor. Such a hardware design method will be described in accordance with the design requirements.

FIG. 3 shows an outline of a measuring procedure based on a hardware design technique used in the present embodiment. In this design procedure, first, the parameter n is initialized to "1" (step S201), and a first-level circuit design as the uppermost layer is executed (step S202). In this example,
This is the general design of the overall device, "a device for multiplexing three North American digital tertiary group signals and multiplexing them into a quaternary group signal by a stuffing synchronization method". If the desired circuit device (hereinafter, “circuit device” is simply abbreviated to “circuit” except for a predetermined case) is completed (step S203: Y), the process ends at this stage (END). .

On the other hand, if it is necessary to create a circuit of a lower layer (step S203: N), the parameter n is incremented by "1" (step S20).
4). In this example, after the circuit design of the first layer as the uppermost layer is performed, the circuit corresponding to the second layer is designed (step S202). In the same manner, by gradually realizing the circuit in the same manner, the design of a desired device is finally completed (step S203:
Y).

When a process goes down to a layer below a certain layer, it is usual that one circuit of the layer before going down is embodied into a plurality of circuits. An example is that the shift register is constituted by a plurality of flip-flop circuits.
Therefore, the circuit design of the n-th hierarchy in step S202 means that each circuit located in the n-th hierarchy is designed.

FIG. 4 shows an outline of the flow of hardware design in an n-th hierarchy as an arbitrary hierarchy. First, the function of the circuit in the hierarchy is specified (step S2).
21), using a database, to search whether or not a circuit having the same function already exists (step S22).
2). The function of the circuit is specified using a natural language. Since the processing is performed using a natural language, there may be an operation for correcting the meaning of the input language as needed. As a result of the search, if the circuit exists in the database (step S223:
Y), the corresponding circuit can be retrieved from the database together with its name, and the design of that circuit can be omitted (step S224).

On the other hand, when there is no circuit corresponding to the circuit whose function is specified in the database (step S223: N), it can be said that the circuit of the function is new. Therefore, a name is given to the circuit having the function (step S225). Then, the circuit is registered in the database in association with the name (step S226). As a result, when the same circuit as the current circuit becomes necessary in the future, the circuit managed by that name can be extracted from the database and used. It should be noted that the assignment of the name in step S225 may mean that the temporarily assigned name is determined.
That is, when the function of a circuit is specified in step S221, a temporary name of the circuit is given, and the process proceeds with that name, and a circuit having the same function does not finally exist in the database (step S221). S223: N) At this time, the temporary name may be promoted to a formal name, or may be changed to a formal name.

In this embodiment, it is required to design a "device for multiplexing three North American digital tertiary group signals and multiplexing them into a quaternary group signal by a stuff synchronization system". Therefore, first, a (temporary) name representing the function (hereinafter, this highest-level function is referred to as “main function”) is given. Then, the function of the circuit is specified.

FIGS. 5 and 6 show the flow of operations in designing hardware from a schematic circuit to a embodied circuit in this embodiment. Here, a description will be given as a series of flows focusing on the processing on the hardware design management device 112 side.

The hardware design management device 112 has a function
Waiting for input of the name of the function block to be
The name of the function block is entered from the keyboard 131 or
Any of the current processing targets on the LAN 111
Workstation 113 ₁~ 113_NOr pars
Null computer 114₁~ 114_MInput from
This is stored in the corresponding area of the RAM 123 (step
S301). First, the name of the "main function" as the top-level function
Since there is an input of the name, it is stored. Here is an example
For example, "Stack that multiplexes three North American digital tertiary group signals
Of the RAM 123, the name of the
It is stored in the corresponding area.

In the next step S302, in order to specify the function of the function block, the designer inputs the names of various input signals to be input to the function block, and similarly stores them in the corresponding area of the RAM 123. . In this example, for the sake of simplicity, it is assumed that the name of only the low-order group input signal is stored in the RAM 123 and this is referred to as "44.
736 Mbps digital tertiary group signal ".

Next, the hardware design management device 112 similarly inputs the names of various output signals output from the functional block to specify the functional block.
These input contents are similarly stored in the corresponding areas of the RAM 123 (step S303). Here, only the high-order group output signal is defined for convenience. However, since the output condition has not yet been defined, it is defined only as “digital fourth-order group signal”.

In the next step S304, the designer is made to input an outline of the relationship between each input signal and each output signal in a natural language. The hardware design management device 112 stores this content in R
It is stored in the corresponding area of the AM 123. The information to be stored is text information by text input or voice input representing an outline of the function of the entire apparatus. For example, "3 digital tertiary group signals each having an asynchronous nominal speed of 44.736 Mbps are slightly higher than 44.736 Mbps. Stuff-synchronous, and further multiplexes three synchronized signals into bits and maps them to frames of a digital quaternary group signal.

In the next step S305, the input contents for the given conditions of the various input signals are stored in the RAM.
123 is stored in the corresponding area. The designer will identify and enumerate the conditions that define the input signal from the specifications that define the input signal. In this embodiment, in order to simplify the explanation, the condition of the input signal is 44.736 Mb / s
It is a digital signal encoded in B20ZS of ± 20 PPM. " Actually, all the conditions described in the specifications such as the amplitude and pulse width of the input signal are listed.

In the next step S 306, conditions expected for output are defined, and the input contents of the designer are stored in the corresponding area of the RAM 123. Here, there is no condition for defining the output yet. Therefore, as a condition expected for the output, “the speed of the high-order group signal is 64 kb /
s, a plurality of 64 kb / s or more monitoring signals can be passed, synchronization information of 8 bits or more, and stuff control information of 5 bits for each low-order group That ".

In the next step S307, a condition to be included in the output signal is inputted from the condition expected for the output and the condition given to the input. These conditions are RAM1
23 are stored in corresponding areas. The condition to be provided for the output signal is specified from the condition expected for the output and the condition given to the input.

The conditional expression that defines the staff synchronization method must be found by searching a document, or must be specified by the designer himself. In this example, it is assumed that the output condition is defined from the “relational expression defining the stuff synchronization method” established by the inventor of this specification. For this output condition,
This is shown in “Consideration of Frame Configuration Method” by Yoshinori Rokugo, Norio Shino and Hiroshi Asano in the Institute of Electronics, Communication and Engineers on May 29, 1984 (hereinafter simply referred to as “prior literature”).
The present invention is independent of determining this condition. Therefore, a detailed description of the prior art is omitted.

Output conditions that satisfy this condition are defined as follows from the prior art. "The high-order group output signal frequency is 13
9.264 Mbps ± 15 ppm, the multiplicity is 3, and the high-order group frame length is 2100 [bits].
7 bits are allocated to frame information and control information.
5 bits, and the number of bits in one frame per low-order group is 675 bits. Also, the synchronization frequency per low-order group is 44.7634 [MHz], the maximum stuffable frequency is 66.3 [kHz], and the nominal stuff rate is 0.4136.

Table 1 below shows the parameters of the stuff synchronizer for multiplexing the North American digital tertiary group signal, and FIG. 7 shows the higher-order group frame format.

[0056]

[Table 1]

In FIG. 7, the 172th to 174th bits of the fifth subset are stuffable bits, the frame pattern of the first subset is "111101", and the frame patterns of the other subsets are "1111010".

In a frame configuration that satisfies this output condition,
Considering a 3-bit block, one frame can be divided into 700 blocks. Here, considering that the stuff control bits require 5 bits per tributary, it is preferable to divide one frame into five subsets. Thus, one subset is 14
It consists of 0 blocks. When 140 blocks are further divided into 5, 28 blocks are obtained. Therefore, the frame structure is composed of "5 subsets, each of which has the first two blocks used for the synchronization signal, the 57th block used for the transfer of the stuff control information, and the 85th block and the 113th block used for the other. The other blocks are used for transferring control information, and the other blocks are used for transferring tributary information.
Eight blocks are used as stuffable bits. Here, the first subset of the synchronization signals is “111101”, and the other subsets are set to “1111010”. ".

In the next step S308, a main function group for linking the input and the output is defined, a name is given to each main function, and the input contents representing those by the designer are stored in the corresponding area of the RAM 123. In this example, three stuff circuits and one multiplex circuit are defined as main functions. That is, "each of the asynchronous low-order group input signals 44.736 MHz is converted to the common synchronization frequency 44.7.
Three independent stuff circuits that synchronize to 634 MHz and a higher-order group frame based on the higher-order group frequency are generated, and a synchronization frequency of 44.7634 is applied to each stuff circuit.
A multiplexing circuit that generates and distributes MHz and bit-multiplexes synchronization data sent from a stuff synchronization circuit. "

In the next step S 309, the designer inputs in text a main function for connecting the input and the output and a connection relation for connecting the various inputs and the various outputs, so that the hardware design management device 112 stores the contents in the RAM 123. Store in the corresponding area.

Such an input sentence in a natural language is described, for example, as follows.
736 Mbps and 44.763 from the multiplexing circuit.
In response to the 4 MHz synchronization clock and the control signal indicating the stuffable position, synchronization data of 44.7634 Mbps is sent to the multiplexing circuit. The multiplexing circuit receives the synchronization data from each of the three stuff circuits, and synchronizes the synchronization data by three.
It multiplexes and adds overhead information to generate and transmit a higher-order group output signal. ".

In the next step S310, the contents entered by the designer are displayed on the display 133 shown in FIG. The designer checks this content and corrects any deficiencies.

That is, in the above-mentioned text, since the main functions connecting the input and the output and the connection relation connecting the various inputs and the outputs are described in the text in a natural language, the synchronization signal between the multiplex circuit and the stuff circuit is described. Information on where the stuff is located cannot be recognized on the multiplex circuit side. Therefore, this sentence is modified as follows. "Each stuff circuit has an external input signal of 44.736 Mb.
ps, a synchronization signal of 44.7634 MHz and a control signal indicating a stuffable position are received from the multiplexing circuit, and synchronization data "44.7634 Mbps"
Information on whether to perform the stuff at a given stuff available position is sent to the multiplex circuit. The multiplexing circuit receives the synchronization data from each of the three stuff circuits, multiplexes the synchronization data three times, adds overhead information, and generates and transmits a high-order group output signal. “At this time, among the overhead information, the stuff control information indicates that the stuff is present when the stuff is executed, and indicates that there is no stuff when the stuff is not executed”. Here, the text within the range enclosed by the parentheses "" and "" has been added in this correction.

In the next step S311, the designer breaks down each main function into a group of functions located below them, and inputs a name to each function. The input content is stored in the corresponding area of the RAM 123.

Here, a stuff circuit will be described as an example. "The stuff circuit provides the input signal 44.736.
A clock extraction circuit for decomposing Mbps into clock and data, a buffer memory for temporarily storing decomposed input data,
The write counter driven by the extracted clock and writes the input data to the buffer memory, the read counter driven by the 44.7634 MHz synchronization clock from the multiplexing circuit to read the buffer memory, and the phases of the write counter and the read counter are read. In comparison, if the phase of the clock of the read counter advances from the phase position specified by the write counter, a stuff request circuit for issuing a stuff request, and the synchronization clock is set to 1 at the position specified by the stuff request from the stuff request circuit. Time slot prohibition stuff execution circuit ". That is, it defines a clock extraction circuit, a buffer memory, a write counter, a read counter, a stuff request circuit, and a stuff execution circuit.

In the next step S312, the relationship between the input and output of each function is defined. Those input contents are RAM1
23 are stored in corresponding areas.

The definition of the relationship between the input and output of each function will be described here by taking a clock extraction circuit as an example. In this example, "the clock extraction circuit has the input of 44.736 Mb.
receiving the signal of the B8ZS code of ps, extracting and outputting the clock signal, further decoding the B8ZS code, and outputting the NRZ signal as data. " In addition, since the sizes of the buffer memory, the write counter, and the read counter defined in step 311 are not known, the tolerance to jitter, the gap generated by the overhead information included in the obtained frame configuration, and the design margin are considered. The designer must specify the size of the buffer memory. Here, it is assumed to be 8 bits.

The write counter and the read counter are racing counters for convenience. Actually, each of them is described in a sentence using a natural language similarly to the clock extraction circuit. Here, for the convenience of the following description, the write counter is referred to as “the write counter is 44.7634M.
Driven by a 50% duty cycle clock of
An eight-phase write signal having a different time slot width and one time slot width is generated and output for each time slot. Further, an x-th phase clock is output as a phase comparison signal. "
It is prescribed.

In the next step S 313, the designer similarly describes the functions that connect the input and output of each function and the connection relationship that connects the input and output with a sentence using a natural language. The input content is stored in the corresponding area of the RAM 123.

The sentence described in step S313 has already been stored for convenience in the buffer memory, the write counter,
Based on the assumption that the relationship between the input and output of each of the read counter, the stuff request circuit, and the stuff circuit is defined, the connection relationship between the input and output of each function and the connection between the input and output are defined. Write in sentences. That is, "the input signal of 44.736 Mbps is input to the clock extraction circuit, and the clock of 44.736 MHz which is the output of the clock extraction circuit is input to the write counter, and the output of the clock extraction circuit is 44.736.
Mbps data is input to all the temporary storage circuits of the buffer memory. 44.7 input to the write counter
The 36 MHz clock is frequency-divided by 8, and clocks having different phases for each time slot are sequentially input one by one to each temporary storage circuit of the buffer storage device. In the read counter, a stuffed synchronization clock of 44.736 MHz is input, frequency-divided by 8, and clocks having different phases every time slot are sequentially input one by one to each temporary storage circuit of the buffer memory. You. The data read from the buffer memory is transmitted as one piece of 44.736 Mbps data as the output of the stuff circuit. "
It becomes a sentence like this.

Here, the phase relationship between the write clock and the read clock to be input to the stuff request circuit has not yet been defined. Therefore, it is necessary for the designer to define this phase relationship in consideration of the jitter tolerance and the design margin. Here, the third phase of the write counter and the first phase of the read counter are used. Further, since there is a problem of jitter tolerance, the clock width of the read counter is set to 2 time slots.

Based on this condition, the relationship between the input and output of each function of the write counter is redefined. That is, "the phase comparison signal of the write counter and the phase comparison signal of the read counter are input to the stuff request circuit, and the phase of the rising edge of the phase comparison signal of the read counter is higher than the phase of the falling edge of the phase comparison signal of the write counter. Sends a stuff request signal to a stuff execution circuit, which receives an input signal from the multiplexing circuit, a 44.7634 Mbps synchronization clock, and a control signal indicating a stuffable position, According to the stuff request signal sent from the stuff request circuit, if there is a stuff request, 44.7634 Mbp
The synchronization clock of s is prohibited at one time slot at the designated position, the synchronization clock is stuffed, and the synchronization clock of 44.7634 Mbps stuffed as the output of the stuff execution circuit is output as the read counter drive clock. " .

In the next step S314, the above input contents by the designer are displayed on the display 133 shown in FIG. The designer checks whether there is any deficiency in this content. Correct any deficiencies.

Here, the output of the stuff request circuit specified in step S 313 is in a state in which the output is influenced by the influence of the overhead byte in one frame of the multiplex circuit, and the stuff request is not output. You can see that there is. Therefore, stuff requests need to be stored at the beginning of the frame. For this purpose, it is necessary to go back to step S309 and correct it. Therefore, the sentence in step S309 is described as “an individual stuff circuit has an external input signal of 44.736 Mb.
ps, a synchronization signal of 44.7634 MHz, a control signal indicating a stuffable position, and frame head position display information from the multiplexing circuit, and 44.763.
4 Mbps synchronization data is sent to the multiplexing circuit. The multiplexing circuit receives the synchronization data from each of the three stuff circuits, multiplexes the synchronization data three times, adds overhead information, and generates and sends a higher-order group output signal. It is corrected.

The sentence shown in step S313 is
"The input signal of 44.736 Mbps is input to the clock extraction circuit, and the output signal of the clock extraction circuit is 44.73.
The 6 MHz clock is input to the write counter, and the data of 44.736 Mbps, which is the output of the clock extraction circuit, is input to all the temporary storage circuits of the buffer storage.
The 44.736 MHz clock input to the write counter is frequency-divided by 8, and clocks having different phases for each time slot are sequentially input one by one to each temporary storage circuit of the buffer storage device. In the read counter, a stuffed 44.7634 MHz synchronized clock is input, frequency-divided by 8, and clocks having different phases every time slot are sequentially input one by one to each temporary storage circuit of the buffer memory. You. The data read from the buffer memory is transmitted as one data of 44.7634 MHbps as the output of the stuff circuit. The phase comparison signal of the write counter and the phase comparison signal of the read counter are input to the stuff request circuit, and the phase of the rising edge of the phase comparison signal of the read counter is earlier than the falling edge of the phase comparison signal of the write counter. Then, a stuff request signal is generated, stored for one frame, triggered by the rising edge of the frame head position display information sent from the multiplexing circuit, and sent to the stuff execution circuit. Also, it outputs the stuff signal to the multiplexing circuit. In the stuff execution circuit, a synchronization signal of 44.7634 Mbps, which is an input signal from the multiplexing circuit, and a control signal indicating a stuffable position are received. For example, the synchronization clock of 44.7634 Mbps is prohibited at a designated position by one time slot, the synchronization clock is stuffed, and the synchronization clock of 44.7634 Mbps stuffed as the main function of the stuff execution circuit is output as the read counter driving clock. " To correct.

As pointed out in step S313,
Since the phase relationship between the write clock and the read clock to be input to the stuff request circuit is not specified,
A phase relationship must be specified. Therefore, step S
Based on the consideration in 313, the write counter defined in step S312 is changed to “the write counter is 44.7.
It is driven by a 36 MHz clock with a duty of 50%, and generates and outputs an 8-phase write signal of 1 time slot width having a different phase for each time slot. Further, as the phase comparison signal, the rising edge of the 2 time slot width outputs the third phase clock. ".

In the next step S315, it is determined whether or not it is necessary to decompose the function into lower-order functions (hierarchies). If necessary (Y), the function is further decomposed into sub-functions. Here, the description is omitted.

On the other hand, if the circuit has a specific configuration at this stage (step S315: N),
If it is a digital circuit from the defined function or subfunction, flip-flop, NAND gate, NOR gate,
The circuit configuration is expressed by a logic circuit such as an AND gate or an OR gate, and the connection relation between them is input as a text.
(Step S316).

In other words, from a defined function or sub-function, if it is a digital circuit, these constituent circuits are represented by flip-flops, NAND gates and NOR gates or AND gates and or gates, and the connection relations of these constituent circuits are described in text. Expressed by Here, a description example is shown using a write counter as an example.

First, from the description shown in step S313, an eight-phase ring counter is assumed as a constituent circuit. Therefore, the designer first checks from the universal name of the ring counter whether there is any design asset stored in the database. If the same design has been made in the past as described above, this can be reused.

Here, a case where the first design is performed without design resources will be described. The ring counter may generate a waveform in which one time slot is “1” and the remaining seven time slots are “0”, and shift the time counter by one time slot every clock. To shift the waveform, D-type flip-flop circuits may be connected in multiple stages in series, and these flip-flop circuits may be driven by a common clock. Also, considering that the waveform in which one time slot is “1” and the remaining seven time slots are “0”, the eight stages of flip-flops shift the same waveform every clock, the first stage of the flip-flop circuit To the seventh stage are obtained by combining the outputs with a noagate. In addition, a waveform having a width of two timeslots whose rising edge is the third phase is obtained by calculating the OR of the outputs of the first and second stages of the flip-flop circuit and inputting the OR to the flip-flop circuit. It can be realized by driving the circuit.

FIG. 8 shows the configuration of a write counter composed of the eight-phase ring counter described above. This write counter includes "8 flip-flop circuits in a cascade, and names the individual flip-flop circuits as a first flip-flop circuit, a second flip-flop circuit to an eighth flip-flop circuit, and the flip-flop circuits are commonly used. That is, a common clock is input to each clock input terminal of the first flip-flop circuit, the second flip-flop circuit to the eighth flip-flop circuit.
Of the seventh flip-flop circuit is input to each input of a seven-input one-output NOR gate on a one-to-one basis. The output of the NOR gate is connected to the input of the first flip-flop circuit. An output of the first flip-flop circuit is connected to a second flip-flop circuit. Thus, the output of the preceding flip-flop circuit is connected to the input of the subsequent flip-flop circuit. The output of each flip-flop circuit is an eight-phase clock output. Further, the output of the first flip-flop circuit and the second
Is input to a two-input one-output OR gate. The output of the OR gate is input to the ninth flip-flop circuit, driven by a common clock, and used as a phase comparison signal. ". If there is a design resource for the 4-bit ring counter as a search result, 8
Expand to a bit ring counter and add necessary functions.

In the next step S317, the designer determines the device to be used in consideration of the operating speed in use, and determines the matters to be considered in designing the board.

That is, a device to be used is determined based on the contents specified in step S316 in consideration of the operation speed. Here, since the operation speed is 45 MHz, FAST
TTL. In addition, notes on printed circuit board design are described because of the high speed. That is, "a bypass capacitor having a band extending up to 500 MHz per IC is placed between the power supply and the ground. The wiring length is made as short as possible. The common clock is made as short as possible so that stubs are not generated. One side is grounded. Plane. "

In the next step S318, the step S3
16 and the circuit specified in step S317 are assembled in hardware to actually evaluate or confirm that a specified output is obtained by a simulator.
If the expected result is not obtained, the cause is pursued based on the observation data, the sentence input in step S316 is corrected, and the evaluation is performed again. In the same manner, a correction operation is performed until an expected value is obtained. Here, the description is omitted.

In the next step S319, a universal name is given to the circuit finally evaluated and determined in step S318. Then, a data sheet using this name is created. Here, the details are omitted.

In the next step S320, if the defined function or sub-function is an analog circuit, it is expressed by a resistor, an inductance, a capacitance, a transistor or an operational amplifier, and the connection relation between them is similarly described in text. Express. Here, the details are omitted.

In the next step S321, step S3
A device to be used is determined based on the contents specified in 20 in consideration of a use operation speed. Also, considerations for board design are determined. Here, the details are omitted.

In the next step S322, a step S3
The circuit specified in step 20 and step S321 is assembled into hardware and evaluated, or a simulator is used to confirm that a specified output is obtained. Here, the details are omitted.

In the next step S323, step S3
A data sheet is created by giving a universal name to the circuit created based on the evaluation result at 18. here,
The details are omitted. The data sheet created in both step S323 and the previous step S319 will be used as an asset for the next and subsequent designs.

In the next step S324, a main function is constructed by combining the evaluated functions or sub-functions, and the hardware is evaluated or it is confirmed that a specified output is obtained by the simulator. .
If the specified output cannot be obtained, the cause is analyzed from the obtained data, the input deficiencies are corrected, and the main function, function or subfunction is reworked. This operation is repeated until a predetermined output is obtained. Details about this will be omitted.

In the last step S325, the main functions are combined with each other in accordance with the contents described in step S309 to form a whole system, and the system is evaluated. Then, it is confirmed that the expected output described in step S307 is obtained. If the expected output is not obtained, the cause is analyzed from the obtained data, the incomplete items in the contents input to the hardware design management device 112 are corrected, and the main function, function or sub-function is reworked. . This process is repeated until the expected output is obtained. Thus, a series of hardware design work is completed.

FIG. 9 shows an outline of the flow of processing for creating a circuit diagram from a sentence created in a natural language. Here, as the design of the first layer, step S30
8, the input processing of the low-order group of signals 44.736 MHz, which has been input by the hardware design management device 112 in steps S309 and S310, to the common synchronization frequency 44.736 MHz.
Three independent stuff circuits that synchronize to 7634 MHz and a higher-order group frame based on the higher-order group frequency are generated, and a synchronization frequency of 44.7634 is applied to each stuff circuit.
Multiplexing circuit for generating and distributing MHz and bit-multiplexing the synchronization data sent from the stuff synchronizing circuit "and" each stuffing circuit receives an external input signal 44.73. "
6Mbps and 44.7634M from multiplexing circuit
Upon receiving a synchronization clock of Hz and a control signal indicating a stuffable position, it sends to the multiplexing circuit synchronization data of 44.7634 Mbps and information on whether or not to perform stuff at the given stuffable position. The multiplexing circuit receives the synchronization data from each of the three stuff circuits, multiplexes the synchronization data three times, adds overhead information, and generates and transmits a high-order group output signal. At this time, the stuff control information in the overhead information indicates that the stuff is present when the stuff is executed, and indicates that there is no stuff when the stuff is not executed. The circuit represented by this sentence is that shown in FIG.

First, in step S401, the name of the hardware is extracted from the text to be processed. Each hardware is given a name and these are registered. First, the sentences already registered in the design of the first layer “each asynchronous low-order group input signal 44.736 MHz
, And three independent stuff circuits for stuff synchronization with a common synchronization frequency of 44.7634 MHz, a higher-order group frame is generated based on the higher-order group frequency, and a synchronization frequency of 44.7634HMz is generated and distributed to each stuff circuit. By extracting proper nouns from "a multiplexing circuit that bit-multiplexes synchronization data sent from a synchronizing circuit", a "stuff circuit" and a "multiplexing circuit" are extracted. If there is a hardware name that is not extracted,
These are registered each time.

As shown in FIG. 17, the "stuff circuit" includes first, second, and third stuff synchronization circuits 21, 22, and 23 in total. This is analyzed from the sentence "3 independent stuff circuits" indicating the number of circuits. Further, as described later, the number of circuits may be determined from the connection relation of signal lines or the input / output relation of signals.

In the next step S402, various input signals or output signals are extracted from the following sentences. That is, "the individual stuff circuits receive external input signals 44.
736 Mbps and a multiplexing circuit 44.7634
In response to a synchronization clock of MHz and a control signal indicating a stuffable position, synchronization data of 44.7634 Mbps is sent to the multiplexing circuit. The multiplexing circuit receives the synchronization data from each of the three stuff circuits, multiplexes the synchronization data three times, adds overhead information, and generates and transmits a high-order group output signal. , An “input signal”, a “synchronization clock”, a “control signal”, a “synchronization data”, an “overhead information”, and a “high-order group output signal” are extracted. Thus, the suffix "signal", "clock", "data",
Nouns with words such as "information" are to be extracted.

In the next step S403, a verb used to connect the circuits is extracted from the text. The words "receive", "send" and "send" correspond to the above-mentioned sentences.

In the next step S404, an input signal and an output signal are connected to each extracted hardware while referring to the extracted verb. That is, as shown in FIG. 10, first, three stuff synchronization circuits 21 to 23 and one multiplexing circuit 24 are arranged. The stuff synchronization circuits 21 to 23
The multiplexing circuit 24 receives the input signals and synchronizes the data.
To the stuff synchronization circuits 21 to 21 on the side closer to the input side.
23 are arranged, and the multiplexing circuit 24 is arranged on the side closer to the output side.

When the positions of the hardware have been determined in this way, each input / output signal is connected to these hardware in a verb connection relationship. FIG. 11 shows an example of a state in which the final connection relationship is determined as an example. If the text indicating the circuit configuration is incomplete and there is something wrong with the configured circuit, the text is further corrected (step S314).

As for the stuff synchronizing circuit, "the stuff circuit is inputted at the step S311.
A clock extraction circuit for decomposing 4.736 Mbps into a clock and data, a buffer memory for temporarily storing decomposed input data, a write counter driven by the extracted clock and writing input data to the buffer memory, Driven by the 44.7634 MHz synchronization clock, the buffer counter reads the buffer memory, compares the phases of the write counter and the read counter, and, when the read counter clock phase advances from the designated phase position of the write counter. 9 is a stuff request circuit that issues a stuff request, and a stuff execution circuit that inhibits the synchronization clock by one time slot at a position designated by the stuff request from the stuff request circuit. Do.

FIG. 12 shows an arrangement of each circuit constituting the stuff synchronous circuit obtained by the above.
First, in step S401 in FIG. 9, "clock extraction circuit", "buffer storage", "write counter", "read counter", "stuff request circuit", and "stuff execution circuit" are extracted. Signal lines and buses are connected to these extracted circuits based on the names of input / output signals and connection operations, thereby completing the circuits.

FIG. 13 is a block diagram showing a schematic configuration of a stuff synchronization circuit finally designed for reference.
The stuff execution circuit shown in FIG.
It is embodied by the correction of the sentence indicated by, and further corrections thereafter.

The write counter forming a part of the stuff synchronizing circuit is embodied based on the natural language shown in step S316. The embodied circuit is as shown in FIG.

FIG. 14 shows an outline of a search operation for giving names to main functions, functions, circuits and the like.
As described above, in the present invention, hardware can be designed using natural language, and assets designed in the past are utilized. For this reason, the names of the circuits and the like managed by the hardware design management device 112 need to be unique in combination with their functions and the like.

Therefore, prior to using the name in various places such as step S301, the designer inputs the name for search (step S451), and retrieves the name from a database of names of circuits and the like managed by the hardware design management device 112. A search is made for the same name (step S452). If there is a registered name (step S453:
Y), the display 1 shown in FIG.
33 and printed out by the printer 136 (step S454). As a result, if it is found that the circuits have the same contents (step S455), it can be used, and there is no need to use a new name.

On the other hand, if the names are not related to circuits or the like having the same contents (step S455: N), a new name is considered and the name is again searched (step S451).

On the other hand, if there is no circuit or the like having the same name in step S453 (N), a registerable display is displayed on the display 133 shown in FIG. 2 (step S453).
456). However, if the same circuit is actually registered in the database in duplicate even if the name is different, the resources cannot be used effectively. Therefore, in this case, the name is used as a temporary name. Then, when the contents of the circuit or the like are substantially searched from the input / output conditions or the like and it is found that the same contents do not exist, the name is actually registered and used.

Finally, FIG. 15 illustrates the relationship between the database and the registered proper noun groups in this embodiment. The hardware design management database that constitutes a part of the disk device 134 includes a component provided with a proper noun consisting of an existing component itself, such as an AND circuit of a predetermined standard, and an existing component. There is a combination of components and a component with a proper noun, which is a combination of components with proper nouns (including a single existing component). In any case, the components of the circuit device whose contents have been completely designed are registered in the database, and when a circuit device whose contents are completed is newly designed, these are newly registered as the components. Will be.

In the above-described embodiment, the hardware is designed using the Japanese natural language. However, the hardware can be similarly designed even if other languages such as English are partially or entirely used. Of course, it can be designed.

[0110]

As described above, according to the first aspect of the present invention, when designing hardware, the unique names of the components constituting the hardware and the names of those components are determined by the text input means. Since signals to be input and signals to be output from their components are composed and input in sentences composed of natural languages, hardware design can be performed without using a special language. It is possible to expand the frame of the designer who is a target when managing the component parts constituting the. Therefore, it is possible to avoid the waste of designing the same circuit device or component part redundantly as much as possible.

According to the second aspect of the present invention, when the circuit devices are generated by the circuit device generating means by inputting the components constituting the circuit device and their connection relations in a sentence composed of a natural language, Is displayed on the display means, it is possible to check a connection error or the like, and when necessary, the correction means can correct the text input from the text input means. Therefore, the input operation can be easily performed using the natural language, and a satisfactory circuit device can be realized by the input of the natural language by using the natural language together with the correction operation. In addition, it is possible to extend the scope of hardware design management to a designer who does not know a special language or an input operation rule.

Further, according to the third aspect of the present invention, for each of the components constituting the hardware, the conditions of the input signal and the conditions of the output signal to be input thereto and the components to be realized are realized. Since a database registered and assigned with a unique name in association with a circuit device to be prepared is prepared, the efficiency of management and the number of components can be reduced by standardizing component parts. Also,
Since there is no need to design if the same parts are used, redundant design work can be eliminated, and when designing a new circuit device, the design time can be reduced by omitting the design of existing components. Can be.

Further, even when a new circuit device not registered in the component data is designed, it is decomposed into constituent components, and some or all of these components are new components. In this case, since the components are specified by disassembling the components in order to the lower layers, the circuit device can be easily realized by combining existing components by utilizing the database.

According to the fourth aspect of the present invention, not only the same effects as those of the third aspect of the invention can be obtained, but also a combination of constituent parts is specified, and finally the combination is known. When the circuit device is realized by the components described above, the circuit device is given a unique name by the name assigning means as one component, and the unique name is registered in the database. Since the components are continually enriched and provided with components of all levels, there is an effect that it is possible to save labor in designing circuit devices and components having the same input / output characteristics.

According to the fifth aspect of the present invention, in the hardware design management device according to the third or fourth aspect, the condition of the input signal input from the input means and the condition of the output signal are provided. Now that the input sentence analysis technology has been improved because it is described in natural language, input and output characteristics of components are input in natural language and analyzed to facilitate input processing, A hardware design management device that can be used by any designer can be realized.

Further, in the invention according to claim 6, the names of the components, the names of the signals or the signal lines are extracted by extracting the nouns in the text, and the verbs are extracted for the arrival routes or the connections of the signals. By performing the analysis, the combination of the component verbs is specified, so that the component can be easily specified in the natural language utilizing the conventional grammatical analysis method.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing a configuration of a hardware design management system using a hardware design management device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an outline of a configuration of a hardware design management device according to the embodiment.

FIG. 3 is a flowchart showing an outline of a design procedure based on a hardware design technique used in the embodiment.

FIG. 4 is a flowchart showing an outline of a flow of hardware design in an n-th hierarchy as an arbitrary hierarchy in the embodiment.

FIG. 5 is a flowchart showing a first half of a work flow when designing hardware from a schematic circuit to a embodied circuit in the embodiment.

FIG. 6 is a flowchart showing a latter half of a work flow when designing hardware from a schematic circuit to a embodied circuit in the embodiment.

FIG. 7 is an explanatory diagram showing a format of a higher-order group frame used in the present embodiment.

FIG. 8 is a block diagram showing a configuration of a write counter composed of an eight-phase ring counter designed in the present embodiment.

FIG. 9 is a flowchart showing an outline of a flow of processing for creating a circuit diagram from a sentence created in a natural language in the present embodiment.

FIG. 10 is an explanatory diagram showing how to arrange three stuff synchronization circuits and one multiplex circuit from a sentence composed of a natural language.

11 is a circuit diagram showing an example in which a specific connection state is completed from the circuit arrangement shown in FIG.

FIG. 12 is a circuit layout explanatory diagram showing the layout of each part of a stuff synchronous circuit forming a part of the circuit shown in FIG. 11;

FIG. 13 is a block diagram illustrating a schematic configuration of a stuff synchronous circuit designed in the present embodiment.

FIG. 14 is a flowchart showing an outline of a search operation for giving names to main functions, functions, circuits, and the like.

FIG. 15 is an explanatory diagram illustrating a relationship between a database and a registered proper noun group in the present embodiment.

FIG. 16 is a block diagram showing an outline of a device in which two North American digital tertiary group signals are multiplexed.

FIG. 17 is a block diagram showing an outline of an apparatus in which three North American digital tertiary group signals are multiplexed.

[Explanation of symbols]

112 hardware design management device 113 _{1 to} 113 _N workstation 114 _{1 to} 114 _M personal computer 121 CPU 123 RAM 131 keyboard 132 mouse 133 display 134 disk device (database)

Claims (6)

[Claims] 1. A text input means for inputting a unique name of a component constituting hardware, a signal input to the component, and a signal output from the component formed by a text composed of a natural language. Extracting means for extracting terms indicating the input and output of the name and the signal from the text input by the text inputting means; meanings of the terms indicating the input and output of the signal between the components extracted by the extracting means And a circuit device generating means for generating a circuit device by connecting in a relationship. 2. Text input means for inputting a unique name of a component constituting hardware, a signal input to the component, and a signal output from the component formed of a text composed of a natural language. Extracting means for extracting terms indicating the input and output of the name and the signal from the text input by the text inputting means; meanings of the terms indicating the input and output of the signal between the components extracted by the extracting means Circuit device generating means for generating a circuit device by connecting in a relationship, display means for displaying the circuit device generated by the circuit device generating means, and when the circuit device displayed by the display means is defective, Correction means for correcting the text input from the text input means to correct the circuit device generated by the circuit device generation means. Hardware design management apparatus that. 3. For each component constituting the hardware, a condition that an input signal to be input to the component has, a condition that an output signal should have, and a circuit device that realizes the component are associated with each component. And input means for inputting the condition of the input signal and the condition of the output signal for each component for configuring the desired hardware, and inputting by the input means. Searching means for searching the database for a component that satisfies all of the conditions of the input signal and the output signal. Means for acquiring design data from the database to omit a new design; For the components that did not match by the means, input to the input means the condition that the input signal has and the condition that the output signal should have for each of the more specific components that realize the component, A hardware design management apparatus further comprising: a component part embodied control unit for embodiing a component until a lower layer component exists in the database. 4. For each component constituting the hardware, a condition that an input signal to be input to the component has, a condition that an output signal should have, and a circuit device that realizes the component are associated with each component. And input means for inputting the condition of the input signal and the condition of the output signal for each component for configuring the desired hardware, and inputting by the input means. Search means for searching the database for a component that satisfies all the conditions of the input signal and the output signal, and for a component matched by the search means, data on a circuit device that realizes the component is replaced with data of the circuit device. Means for acquiring design data from the database to omit a new design; For the components that did not match by the means, input to the input means the condition that the input signal has and the condition that the output signal should have for each of the more specific components that realize the component, Further, a component embedment control means for embodiing a component until a lower tier component exists in the database, and a lower tier in which a certain upper component exists in the database by the component embodiment control means A name assigning means for assigning a unique name by associating a higher-order component with these lower-level components when all the components are embodied, and hardware to which a unique name is assigned by the name assigning means And a database registering means for registering as one component in the database. Total management device. 5. The condition of an input signal input from the input means and the condition of an output signal are described in a natural language.
The described hardware design management device. 6. The natural language according to claim 1, wherein nouns are extracted as names of component parts or signals, and verbs are extracted as meaning connection of the component parts. Item 6. The hardware design management device according to item 4.