JP2000293495A - Network device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of transmitting efficiency due to network competition in a multi-stage joint computer network device (inter-node connecting device). SOLUTION: The transmission side of each node 100 is provided with a function part 122 which selects the detour path of a cross bar switch from the competition information of each stage cross bar switch received from reception data, and adds path designation to transmission data and a function part 240 which transfers data according to the path designation to each stage cross bar switch 200 and adds the competition information at that time to the transfer data for communicating this competition information to a reception side. The reception side of each node 100 is provided with a function part 123 which stores the competition information added to the received data, and uses the competition information for the detour path selection at the next time of transmission, and operates time stamp to the competition information for dynamically operating detour path selection in operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a network device,
In particular, the present invention relates to a computer global network device for interconnecting a plurality of computers to transfer data.

[0002]

2. Description of the Related Art A conventional example of a network device for interconnecting a plurality of computers to transfer data is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-54762, entitled "Network Configuration".

[0003] Such a conventional network device will be described with reference to the configuration diagram of FIG. In this conventional network device, a large number of processors 2 are connected to a plurality of network LSIs (large-scale integrated circuits) 1 via cables 3. These many processors 2 are divided into a plurality of groups and interconnected by rings 4.

That is, a network for interconnecting a large number of processors 2 comprises a plurality of complete crossbars corresponding to each group for connecting the processors in each group obtained by dividing the many processors 2 into appropriate units. Connect the switch and multiple groups in a ring. Furthermore, the groups adjacent to each other on the ring are connected by a number equal to the number of processors 2 belonging to the group. It has a data path used for connection between processors belonging to different groups.

In the network, the data path is a one-way transfer path, and a packet input from a processor belonging to the first group is transferred from one of the data paths at the next stage of the first group to the first group. Output to the first
A circuit and a second circuit for outputting a packet from a data path from a group at a stage preceding the first group to the first group to a processor belonging to the first group or to a data path to a group at the next stage. It has a configuration.

Next, a network for a parallel computer includes a plurality of network LSIs 1 used by connecting a plurality of processors, and a plurality of these network LSIs.
And a plurality of one-way transfer data paths that connect the two in a ring. The network LSI 1 has a plurality of input ports and output ports connected to a number of processors equal to the number of the plurality of processors 2, and a complete crossbar switch connection network connecting the plurality of input ports and output ports. The number of data connections is equal to the number of processor LSIs 1 between any adjacent network LSIs 1. The connection between the processors belonging to different network LSIs 1 is configured to be made via a data path.

Next, a circuit connecting the network LSI 1 to any one of a plurality of data paths from the input port to the next-stage network LSI 1 and a circuit connecting the output port of the plurality of data paths from the previous-stage network LSI 1 to the next or next. It is configured to have a circuit that connects to a data path to the network LSI 1 of the stage.

[0008] With this network configuration method, a group can be formed in units of a processor group existing in a mounting range in which complete crossbar connection can be easily performed, and communication between processors in the group is efficiently performed by complete crossbar connection. I can do it. On the other hand, the connection between processors belonging to different groups whose physical distances are far from each other only requires connection between adjacent groups. Therefore, in order to reduce the wiring length and increase the amount of wiring by a small ring-type coupling, each L
The wiring length between the SIs is kept within a certain limit, and the scale of the parallel computer system can be increased only by increasing the number of units in groups without being restricted by the wiring length and the wiring amount.

[0009]

In the above-described conventional network device, there is a problem that the transfer efficiency is reduced when the access through the same intermediate route frequently occurs despite the crossbar network which is completely connected. The reason for this is that processors are grouped in order to avoid a decrease in transfer efficiency due to network competition of crossbar connection of complete connection. However, when access from a plurality of distant processors through the same intermediate route frequently occurs, there is no means for avoiding contention, so that contention occurs and transfer efficiency is reduced.

Also, in a general computer network device, if a plurality of processors frequently access the same intermediate path, the transfer efficiency is reduced. The reason is that the transfer route is statically set in advance, and if there is frequent access from multiple processors through the same intermediate route, there is no means to select a detour route even if there is a free route, This is because competition occurs and transfer efficiency is reduced.

An object of the present invention is to provide a network device having a high transfer efficiency even when access from a plurality of processors through the same intermediate route frequently occurs.

[0012]

In order to solve the above-mentioned problems, a network device according to the present invention employs the following characteristic configuration.

(1) A network device in which a multi-stage crossbar switch is arranged between a plurality of nodes each including a processor unit and data is transferred from one of the plurality of nodes to another node. Each node includes a transmission circuit that performs data transmission and reception between the processor unit and the crossbar switch, a reception circuit, a path analysis circuit that analyzes path information in transmission data, and determines an optimal path, and a reception circuit. A network device, comprising: a time stamp circuit for writing a data reception time; each crossbar switch including an arbitration circuit for controlling a transmission order when a conflict occurs, and a conflict recording circuit for adding the number of times of waiting due to the conflict to passing data.

(2) The network device according to (1), wherein the crossbar switches are arranged in a matrix between the plurality of nodes.

(3) The network device according to (1) or (2), wherein each of the crossbar switches has a buffer for temporarily storing data on an input side.

(4) The network device according to (1), wherein the route analysis circuit selects the shortest route when there is no conflicting part.

(5) The network device according to (1), wherein the route analysis circuit updates the conflict information based on the time of the time stamp circuit.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a network device according to the present invention will be described below in detail with reference to FIGS.

FIG. 1 is an overall configuration diagram of a preferred embodiment of a network device according to the present invention. FIG. 2 is a detailed configuration diagram of each node in FIG. FIG. 3 is a detailed configuration diagram of one of the plurality of crossbar switches shown in FIG.

The network device according to the present invention comprises, for example, as shown in FIG.
It is composed of nine 8 × 8 crossbar switches 200.
As will be described later with reference to FIG. 2, each node 100 is a computer device (electronic computer system), and is provided via a plurality of crossbar switches 200 for the purpose of sharing operation data among the plurality of nodes (computer devices) 100. Interconnected.

The crossbar switch 200 is a device for connecting a plurality of nodes 100 (cross-connecting each other). Variable-length packet data (unit data)
Performs data transfer between the nodes 100. Generally, the crossbar switch 200 is a node 1 connected to the crossbar switch 200.
It is a device configured to be able to perform data communication between 00 and 00, and can take various forms (configurations). In this embodiment, the configuration of the crossbar switch (8 × 8, 4 ×
(4, anomalous type configuration, etc.) itself, but not in the configuration of the data input / output port of the node 100 and the configuration in the crossbar switch 200, and the data configuration thereby.

In FIG. 1, a plurality of network devices (1
The eight (8) nodes 100 and the multiple (9) crossbar switches 200 may have the same configuration.

Next, the detailed configuration of each node 100 in FIG. 1 will be described with reference to FIG. Each node 100 includes a processor (arithmetic processing) unit 110 and a transfer control unit 120. Further, the transfer control unit 120 includes a transmission circuit 121 serving as a data transmission unit, a path analysis circuit 1 for performing path analysis
22, a time stamp circuit 123 and a receiving circuit 124 as data receiving means. Processor unit 1
The CP transmission data 11 is transmitted from 10 to the transmission circuit 121, and the transmission data 12 is output from the transmission circuit 121.
Also, the reception data 13 is input to the reception circuit 124,
CP reception data is input from the reception circuit 124 to the processor unit 110.

Next, referring to FIG. 3, a detailed configuration of a plurality of crossbar switches 200 constituting the network device of FIG. 1 will be described. Each crossbar switch 200 has an input port and an output port. Eight buffers 210 to 217 are connected to the input port. Outputs of the buffers 210 to 217 are connected to corresponding data switching circuits 220 to 227 and input to the control circuit 230. The output of the control circuit 230 is input to the conflict recording circuit 240. The output of the control circuit 230 is input to the data switching circuits 220 to 227 as the switching signal 20. The other output of the control circuit 230 is
It is output to the conflict recording circuit 240 as the number of waits 21.
Further, the competition recording circuit 240 is output to the output port as the passage information 22.

Next, the operation of the network device according to the present invention will be described with reference to FIGS. Each node 100
Is a general computer device. When transferring data to another node, the CP transmission data 11 including the transfer destination, the transfer amount, and the data is transferred to the transfer control unit 1.
20 to the transmission circuit 121. Another node 1
When receiving data from 00, CP reception data 14 including a transfer source and a transfer amount is received from the reception circuit 124.

The transfer control unit 120 includes a processor unit 110
The transmission / reception of the CP transmission data 11 and the CP reception data 14 is performed via the crossbar switch 200. The transmission circuit 121 receives the CP from the processor unit 110.
When the transmission data 11 is received, the crossbar switch 20
In order to set the transfer route by controlling 0, the transfer destination 15 is notified to the route analysis circuit 122, and the transfer route designation 16 from the route analysis circuit 122 is added to the routing control (route control) unit of the CP transmission data. The data is transmitted to the crossbar switch 200 as the transmission data 12.

The time stamp circuit 123 has an internal clock, and sends the reception time 18 to the reception circuit 124 when receiving data. Further, the receiving circuit 124 includes the crossbar switch 20
When the received data 13 is received from 0, the data portion is passed to the processor portion 110 as the CP received data 14, the header portion and the routing control portion are added with the reception time 18 from the time stamp circuit 123, and the route analysis circuit Send to 122.

The route analyzing circuit 122 stores the past data transfer route information 19 received from the receiving circuit 124. A relatively vacant route is selected from the route information in which the route from the transmission circuit 121 to the transfer destination 15 is stored, and the transfer route designation 16 is passed to the transmission circuit 121. To select a route, the shortest route is searched based on the transfer destination 15 sent from the transmission circuit 121, and the number of waiting times for each passing point (crossbar switch at each stage) of the route is checked from accumulated data. Further, based on the time stamp of the reception time from the time stamp circuit 123, data that has passed a certain time or more is invalidated. If the stored data does not exist or is invalidated, the shortest path is selected.

Next, the crossbar switch 200 shown in FIG. 3 will be described. The crossbar switch 20 of this specific example
0 is an 8 × 8 crossbar, each having eight input ports and output ports. The connected node 100 or the next-stage crossbar switch 200 uses a pair of input port and output port. Therefore, a total of eight nodes 100 or crossbar switches 200 can be connected to each crossbar switch 200. Buffers 210 to 21
Numeral 7 temporarily stores data received from the input port, that is, a part of the transmission data 12 in FIG. 2, and is a well-known general buffer that absorbs a time for arbitration and a time difference of a transmission path described later. It is. Data switching circuits 220-22
7, according to the switching signal 20 from the arbitration circuit 230,
The data in the buffers 210 to 217 is switched and transmitted to the output port.

The arbitration circuit 230 is configured to
The switching data 20 is output from the transmission data 12 input to the switch 17 so that the transfer data is output to the output port specified by the route specification while looking at the header part and the routing control part of the data. At this time, if a plurality of transfer data specifying the same output port occurs, a priority determination is made and one of the transfer data is selected, and the rest are kept waiting. As the arbitration method for this priority determination, there are some general known methods. For example, there are a fixed system and a cyclic system. This is called a contention, and the number of times of waiting in the contention is set as the number of waits 21 and the contention recording circuit 240
Send to If the wait count is 0, there is no contention. On the other hand, the number of competitive recordings 240 is
At 227, the passage information 22 including the passage route of the data selected by the routing control unit, the number of competitions, and the route count is embedded.

Next, the operation of the entire network device (system) according to the present invention will be described with reference to FIGS. First, an example in which data is transferred from node # 1 to node # 15 will be described. Processor 1 in node # 1
10 specifies the node # 15 as the transfer destination address and
When the communication data 11 is sent to the transmission circuit 121, the transmission circuit 12
1 sends the transfer destination 15 to the route analysis circuit 122. The route analysis circuit 122 selects an optimum route from the shortest route and the accumulated data route information, and sends a transfer route designation 16 to the transmission circuit 12.
Pass to 1. The transmission circuit 121 that has received the transfer path designation 16 adds the transfer path designation 16 to the head of the transfer data as a routing control unit and sends the transmission data 11 to the crossbar switch 200.

Next, the crossbar switch 200 that has received the transmission data 11 first takes in the transfer data 11 into the buffer 210 and notifies the arbitration circuit 230 that the data has been received. The arbitration circuit 230 looks at the transfer destination of the routing control unit, sends the switch signal 20 to the data switch circuit 226, and instructs the data switch circuit 226 to output the transfer data of the buffer 210 to the port. At the same time, the number of waits 21 is sent to the competition recording circuit 240. The conflict recording circuit 240
The transit time, the number of conflicts, and the path count are embedded in the routing control unit of the transfer data of the data switching circuit 226 and sent to the crossbar switch 200 at the next stage.

According to the route of the routing control unit, the node # 15 receiving the transferred data,
When the reception data 13 is received by the reception circuit 124, the header section and the routing control section are added with the reception time 18 from the time stamp circuit 123 and sent to the path analysis circuit 122 as the path information 19, and the transfer source, the transfer amount, the data section To the processor 110. Path analysis circuit 122
Stores (stores) the route information 19 from the receiving circuit 124 in the past transfer, and uses the route information 19 as route analysis data for route selection when data is sent from the own node next time.

Next, the header section and the routing control section added to the transfer data will be described with reference to FIGS. FIG. 4 shows the crossbar switch 2 of each stage.
00 shows a header part (a) and a routing control part (b) as viewed from the input side. The header section and the routing control section at the entrance of the first-stage crossbar switches (# 1 to # 3) are those of the transmission data 12 added by the transfer control section 120 of the node 100.

The header section (a) includes a transfer destination address 41, a transfer source address 42, and a transfer amount 43 specified by the processor section 110. The routing control unit (b) sets the port number that the route selected by the route analysis circuit 122 based on the transfer destination is desired to be transmitted to the left with the crossbar switch at the passing point. The leftmost route specification 44
Is the first-stage crossbar switch 200 (# 1 to # 3)
Is the routing for The second route designation is a route designation for the second-stage crossbar switch 200 (# 4 to # 6). The third route designation 45 is a route designation for the third-stage crossbar switch 200 (# 7 to # 9). In the crossbar switch 200, the output port of the own crossbar switch is written at the leftmost position. When the output port is passed to the next-stage crossbar switch, the routing control unit is shifted left and the route of the next-stage route is switched. Make sure that the setting is on the left. FIG. 4C shows the data section 48.

FIG. 5 shows a crossbar switch 200.
3 shows the header part (a), the routing control part (b), and the data part (c) as seen by the receiving circuit 124 of the receiving node 100. The header part of FIG. 5A indicates that the received time 50 is added by the time stamp circuit 123. Each time the routing control unit in FIG. 5B passes through the crossbar switch 200,
The route designation portion is left-shifted and cut away, and instead, the passing routes 52a to 52c and the competition information 53a to 53c are written right-justified. Further, the path count 54 is incremented by +1 (counting up) each time the signal passes through the crossbar switch 200 so that the numbers of the passing paths 52 and the competition information 53 can be determined (that is, in order to determine the information of some bits). still,
The initial value is 0.

The next-stage crossbar switch 200 (# 4 to # 4)
# 9) is also right-justified and the passage route 52 and the competition information 53
Is written, and the path count 54 is incremented by 1, so that when the data is passed to the receiving side of the node 100, the result is as shown in FIG.
FIG. 5C shows the data.

Next, referring to FIG. 6 and FIG.
The transition of the routing control unit when data is transferred from node 11 to node # 15 will be described. FIG.
FIG. 7 shows the data flow by physical or constituent elements.
Indicates it as data.

Data is transferred from node # 1 to node # 15 in the order of node # 1, crossbar switch # 1, crossbar switch # 4, crossbar switch # 5, crossbar switch # 8, and node # 15 in FIG. As shown in FIG.

The transmission data 11 of the node # 1 becomes a routing control unit shown in FIG. That is, the output port numbers from the crossbar switches # 1, # 4, # 5, and # 8 are 7, 4, 6, and 5, respectively. When the transfer data of (a) is passed to the first-stage crossbar switch # 1, there is an instruction to output the data to the port 7, and the data is output to the port 7 and the routing control unit is shifted to the left. A conflict occurs in the output, and the fact that it has been waited twice is recorded as passage information, and at the same time, the path count is set to +1. When the signal passes to the next-stage crossbar switch # 4, it becomes a routing control unit shown in FIG. 7B.

That is, as described above, the path information of the next stage is shifted to the left, and comes to the left end. Hereafter, crossbar switch #
In steps 5 and # 8, the same operation is repeated as shown in FIGS. 7 (c) and (d). Finally, upon arriving at node # 15,
The reception data 13 becomes a routing control unit as shown in FIG. That is, there are route designation, passage information, and route count data on the right justified from the left. The path counts in FIGS. 7A to 7E are 0 to 4, respectively.

The configuration and operation of the preferred embodiment of the network device according to the present invention have been described above. As understood from the above description, by stacking the transfer between the nodes, it is possible to sequentially bypass the competing crossbar switches. Also monitor the timestamp,
Prevents selection of a detour route in a race condition at an old time. If there is little contention, the shortest path is selected, so there is no performance degradation due to this function. In addition, even when the load is high, the balance between what is being waited for by the arbitration circuit inside the crossbar switch and what comes out earlier is maintained. As a result, it is possible to avoid a situation in which a plurality of nodes all select the bypass route, and consequently the other crossbar switches are congested.

The present invention should not be limited to only the preferred embodiments described above, and it will be easily understood by those skilled in the art that various modifications can be made without departing from the gist of the present invention. .

[0044]

As is clear from the above description, the following remarkable effects can be obtained according to the network apparatus of the present invention.

First, the balance is made according to the data transfer load between nodes, so that the data transfer efficiency is improved. The reason is that by stacking the inter-node transfer, the conflict information of the crossbar switch is accumulated in a timely manner, and the bypass route is selected based on the accumulated data.

Next, even when the load is small or when the load changes from a high load to a low load, the data transfer efficiency can be improved in a well-balanced manner. The reason is that in the crossbar switch, the time is added to the conflict information, and the conflict information of the old time is invalidated and constantly updated (updated), so that the detour route based on the information of the old time is erroneously made. This is to eliminate the prisoners who choose. Also, when there is little contention, the shortest route is selected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the entirety of a preferred embodiment of a network device according to the present invention.

FIG. 2 is a detailed block diagram of one of a plurality of nodes of the network device shown in FIG. 1;

FIG. 3 is a detailed block diagram of a plurality of crossbar switches of the network device shown in FIG. 1;

FIG. 4 is an explanatory diagram of a data format on an input side of a crossbar switch used in the present invention.

FIG. 5 is an explanatory diagram of a data format on a node side that has passed through a crossbar switch used in the present invention.

FIG. 6 is a diagram illustrating an example of a data transfer path from a node # 1 to a node # 15 of the network device illustrated in FIG. 1;

FIG. 7 is a diagram showing data in the case of the data transfer shown in FIG. 6;

FIG. 8 is a block diagram of a conventional network device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 node 110 processor unit 121 transmission circuit 122 path analysis circuit 123 time stamp circuit 124 reception circuit 200 crossbar switch 210 to 217 buffer 230 arbitration circuit 240 competition recording circuit

Claims (5)

[Claims] 1. A network device for arranging a multistage connection crossbar switch between a plurality of nodes each including a processor unit and transferring data from one of the plurality of nodes to another node. A node configured to transmit and receive data between the processor unit and the crossbar switch, a reception circuit, a path analysis circuit that analyzes path information in transmission data and determines an optimal path, and data of the reception circuit. A time stamp circuit for writing a reception time, wherein each of the crossbar switches is
A network device comprising: an arbitration circuit for controlling the transmission order when a conflict occurs; and a conflict recording circuit for adding the number of times of waiting due to the conflict to passing data. 2. The network device according to claim 1, wherein the crossbar switches are arranged in a matrix between the plurality of nodes. 3. The network device according to claim 1, wherein each of said crossbar switches has a buffer for temporarily storing data on an input side. 4. The network device according to claim 1, wherein said route analysis circuit selects a shortest route when there is no conflicting part. 5. The network device according to claim 1, wherein the route analysis circuit updates the conflict information based on the time of the time stamp circuit.