JP2000286369A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JP2000286369A JP2000286369A JP11090851A JP9085199A JP2000286369A JP 2000286369 A JP2000286369 A JP 2000286369A JP 11090851 A JP11090851 A JP 11090851A JP 9085199 A JP9085199 A JP 9085199A JP 2000286369 A JP2000286369 A JP 2000286369A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor chip
- high thermal
- semiconductor
- fabric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明が属する技術分野】本発明は、高密度表面実装タ
イプの高集積半導体装置及びその製造方法に関するもの
である。特に、放熱性及び応力緩和性に優れる高密度表
面実装タイプの高集積半導体装置及びその製造方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density surface-mount type highly integrated semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a high-density surface-mount type highly integrated semiconductor device having excellent heat dissipation and stress relaxation, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】エレクトロニクス産業は著しい発展を遂
げ、様々な電子機器が工場、事務所或いは家庭に入り込
んでいる。これらの電子機器は、小型で高性能であるこ
とが強く求められている。BACKGROUND OF THE INVENTION The electronics industry has undergone significant development, with a variety of electronic devices entering factories, offices or homes. These electronic devices are strongly required to be small and have high performance.
【０００３】これに対応するため、半導体チップの高集
積化やパッケージの軽薄短小化が進行している。一方、
基板搭載方法は、半田溶融温度まで上昇する表面実装へ
と移行している。つまり、チップはより繊細に保護層は
より薄くなる一方半導体装置に加わる熱応力は大きくな
っている。この結果、半導体装置は熱応力により機能不
良を起こしたり、半導体装置そのものが破壊されたりす
る問題を生じている。こうした背景から、半導体装置の
信頼性を飛躍的に高める技術、即ち放熱性及び熱応力緩
衝性に優れる高熱伝導弾性体が強く要求されている。In order to cope with this, semiconductor chips are becoming more highly integrated and packages are becoming lighter and smaller. on the other hand,
The board mounting method has shifted to surface mounting where the temperature rises to the solder melting temperature. That is, the chip is more delicate and the protective layer is thinner, while the thermal stress applied to the semiconductor device is larger. As a result, there is a problem in that the semiconductor device may malfunction due to thermal stress or the semiconductor device itself may be destroyed. From such a background, there is a strong demand for a technology for dramatically improving the reliability of a semiconductor device, that is, a high thermal conductive elastic body having excellent heat dissipation and thermal stress buffering properties.
【０００４】半導体装置の小型化要求に対して、様々な
取組がされている。例えば、半導体ベアチップを基板に
直接取り付けるフリップチップ方式やキャリアテープ方
式等が知られてる。又、従来のワイヤーボンディング方
式でも超小型パッケージが開発されている。これら各種
高密度実装パッケージはチップサイズパッケージ（ＣＳ
Ｐ）という名で総称され日進月歩している。さらに、ウ
エハー段階での実装も本格検討されるようになってきて
いるVarious approaches have been taken to meet the demand for miniaturization of semiconductor devices. For example, a flip chip method, a carrier tape method, and the like in which a semiconductor bare chip is directly attached to a substrate are known. Ultra-small packages have also been developed using the conventional wire bonding method. These various high-density mounting packages are chip-size packages (CS
It is collectively referred to as P) and is evolving. In addition, mounting at the wafer stage is also being considered in earnest
【０００５】半導体装置の高密度化に伴って、半導体自
身から発生する熱を如何に発散させるかが問題となって
いる。チップの高集積化により単位面積当たりの発熱量
が増加するが、一方パッケージの軽薄短小化により放熱
空間が少なくなっている。つまり、今まで以上に効率的
に放熱することが必要になってきた。[0005] With the increase in the density of semiconductor devices, how to dissipate the heat generated by the semiconductor itself has become a problem. The amount of heat generated per unit area increases due to the high integration of the chip, but the heat radiation space is reduced due to the lightness and small size of the package. That is, it is necessary to radiate heat more efficiently than ever.
【０００６】市販品としては、放熱性接着剤、放熱シー
トや放熱グリース等を手に入れることができる。これら
は熱伝導性充填剤を配合した樹脂組成物であり、高い放
熱性を得るためには充填剤を多量に配合することが必要
で柔軟性の低下が伴う。つまり、高熱伝導性のものは応
力緩和性に劣るという欠点を有している。As commercially available products, a heat-radiating adhesive, a heat-radiating sheet, a heat-radiating grease, and the like can be obtained. These are resin compositions containing a thermally conductive filler, and in order to obtain high heat dissipation, it is necessary to blend a large amount of the filler, resulting in a decrease in flexibility. That is, a material having high thermal conductivity has a drawback of being inferior in stress relaxation.
【０００７】放熱問題を解決する新しい方法も提案され
ている。例えば、特開平１０−１６３３７９は柔軟性物
質の表面に熱伝導性物質が付与された構造。特開平１０
−１６３６００は放熱性布に柔軟性接着剤を含浸させた
構造、特開平１０−３０３３４０は金属バネ構造を提案
している。しかしながら、これら提案は実用性に乏し
い。第１の提案は表面と内部の熱伸縮が異なるため耐久
性の面で問題があり、第２の提案は放熱性と応力緩和性
が互いに犠牲となる構造を有しており、第３の提案は接
触面積が少なく放熱性が劣る欠点を有している。又、い
ずれの提案もコスト的に高いものである。[0007] New methods have been proposed to solve the heat dissipation problem. For example, Japanese Patent Application Laid-Open No. 10-163379 discloses a structure in which a heat conductive substance is provided on the surface of a flexible substance. JP Hei 10
JP-163600 proposes a structure in which a heat-radiating cloth is impregnated with a flexible adhesive, and JP-A-10-303340 proposes a metal spring structure. However, these proposals are not practical. The first proposal has a problem in durability due to the difference in thermal expansion and contraction between the surface and the inside. The second proposal has a structure in which heat dissipation and stress relaxation are sacrificed each other. Has the disadvantage that the contact area is small and the heat dissipation is inferior. Further, both proposals are costly.
【０００８】[0008]
【発明が解決しようとする課題】本発明は、こうした問
題を解決する、小型で高性能しかも低コストの半導体装
置及びその製造方法を提供するものである。即ち、放熱
性と応力緩和性に優れる低コストの半導体装置及びその
製造方法を提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a small-sized, high-performance and low-cost semiconductor device and a method of manufacturing the same, which solve these problems. That is, an object of the present invention is to provide a low-cost semiconductor device excellent in heat dissipation and stress relaxation, and a method of manufacturing the same.
【０００９】[0009]
【課題を解決するための手段】本発明は、半導体チップ
と外装部材との間に、高熱伝導性の弾性体を直接且つ大
面積で介在させたことを特徴とする半導体装置である。
該弾性体として、弾性を有する金属又は高熱伝導性セラ
ミックスよりなる織物又は編物類を介在させたことを特
徴とする半導体装置である。SUMMARY OF THE INVENTION The present invention is a semiconductor device characterized in that an elastic body having high thermal conductivity is interposed directly and over a large area between a semiconductor chip and an exterior member.
A semiconductor device in which a woven or knitted fabric made of a metal having elasticity or a high thermal conductive ceramic is interposed as the elastic body.
【００１０】金属又は高熱伝導性セラミックスよりなる
織物又は編物を構成する主元素としては、半導体装置で
使用実績のあるアルミニウム、鉄、ニッケル、銅、及び
これらの合金類から選ばれた少なくとも１種であること
が好ましい。高熱伝導性セラミックスとしては、例え
ば、酸化鉄、アルミナ、窒化アルミニウム等を挙げるこ
とができる。The main element constituting the woven or knitted fabric made of a metal or a high thermal conductive ceramic is at least one selected from aluminum, iron, nickel, copper, and alloys thereof, which have been used in semiconductor devices. Preferably, there is. Examples of the high thermal conductive ceramics include iron oxide, alumina, aluminum nitride and the like.
【００１１】弾性を有する金属又は高熱伝導性セラミッ
クスよりなる織物又は編物類の繊維はそれ自体が弾性を
示す形状、即ち、バネ状又はコイル状のものを用いるこ
とが好ましい。It is preferable to use a woven or knitted fiber made of a metal having elasticity or a ceramic having high thermal conductivity having a shape showing elasticity itself, that is, a spring-like or coil-like fiber.
【００１２】また、本発明の半導体装置を製造する際
に、金属又は高熱伝導性セラミックスよりなる織物又は
編物類を半導体又は及び外装部材に、半田、低融点金
属、熱伝導性接着剤、熱伝導性グリース等で固定（仮止
めを含む）することを特徴とする製造方法である。金属
又は高熱伝導性セラミックスよりなる織物又は編物類を
外装部材の内面に爪又はくびれを設けて固定し半導体装
置を製造することもできる。Further, when fabricating the semiconductor device of the present invention, a woven or knitted fabric made of metal or high thermal conductive ceramic is applied to a semiconductor or an exterior member by soldering, a low melting point metal, a thermally conductive adhesive, It is a manufacturing method characterized by fixing (including temporary fixing) with a grease or the like. A semiconductor device can also be manufactured by fixing a woven or knitted fabric made of a metal or a high thermal conductive ceramic by providing claws or constrictions on the inner surface of the exterior member.
【００１３】固定のため用いる熱伝導性接着剤や熱伝導
性グリースとしては、金属微粉末や金属酸化物を高充填
したエポキシ樹脂やシリコーン樹脂系の製品が市販され
ている。例えば、シリコーン樹脂系グリースとしは、Ｇ
７４７（信越化学工業）、ＹＧ６１１１（東芝シリコー
ン）を挙げることができる。As a heat conductive adhesive or a heat conductive grease used for fixing, epoxy resin or silicone resin products highly filled with metal fine powder or metal oxide are commercially available. For example, as a silicone resin-based grease, G
747 (Shin-Etsu Chemical) and YG6111 (Toshiba Silicone).
【００１４】図１は、本発明の半導体装置の実施形態例
である。半導体１は、バンプ１０を介して回路基板２に
固定されている。バンプ１０は、半導体チップ電極３と
回路基板電極５を接続するとともに半導体チップを回路
基板に固定している。半導体チップは樹脂層８により保
護されている。外装部材９と半導体チップとは高熱伝導
性の弾性体（金属編物）６を介して接続している。FIG. 1 shows an embodiment of a semiconductor device according to the present invention. The semiconductor 1 is fixed to the circuit board 2 via the bump 10. The bump 10 connects the semiconductor chip electrode 3 and the circuit board electrode 5 and fixes the semiconductor chip to the circuit board. The semiconductor chip is protected by the resin layer 8. The exterior member 9 and the semiconductor chip are connected via an elastic body (metal knit) 6 having high thermal conductivity.
【００１５】[0015]
【発明の効果】高熱伝導性の弾性体を半導体チップと外
装部材の間で大面積接触させることにより、半導体装置
で発生する熱を発散させることができ、熱応力を緩和す
ることもでき、半導体装置の信頼性が抜群に高まる。高
熱伝導性の弾性体の構造を単純にし且つ簡単に固定する
ことにより低コストの半導体装置が得られるAccording to the present invention, the heat generated in the semiconductor device can be dissipated and the thermal stress can be reduced by bringing the elastic member having high thermal conductivity into large-area contact between the semiconductor chip and the package member. The reliability of the equipment is remarkably improved. A low-cost semiconductor device can be obtained by simplifying and easily fixing the structure of the elastic body having high thermal conductivity.
【図１】本発明の実施形態の一例を示す図である。FIG. 1 is a diagram showing an example of an embodiment of the present invention.
１ 半導体チップ ２ 回路基板 ３ 半導体チップ電極 ５ 回路基板電極 ６ 高熱伝導性の弾性体 ８ 樹脂層 ９ 外装部材 １０ バンプ DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Circuit board 3 Semiconductor chip electrode 5 Circuit board electrode 6 High thermal conductive elastic body 8 Resin layer 9 Exterior member 10 Bump
Claims (5)
有する金属又は高熱伝導性セラミックスよりなる織物又
は編物類を介在させたことを特徴とする半導体装置。1. A semiconductor device comprising a woven fabric or a knitted fabric made of an elastic metal or a highly heat-conductive ceramic between a semiconductor chip and an exterior member.
る主元素がアルミニウム、鉄、ニッケル、銅、及びこれ
らの合金類から選ばれた少なくとも１種であることを特
徴とする請求項１に記載の半導体装置。2. The method according to claim 1, wherein the main element constituting the metal or the high thermal conductive ceramic is at least one selected from aluminum, iron, nickel, copper and alloys thereof. Semiconductor device.
維を用いたものであることを特徴とする請求項１又は請
求項２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the woven or knitted fabric uses spring-like or coil-like fibers.
装部材とを、半田、低融点金属、熱伝導性接着剤、熱伝
導性グリース等で固定することを特徴とする請求項１か
ら請求項３のいずれか１項に記載の半導体装置の製造方
法。4. A woven or knitted fabric and a semiconductor chip or an exterior member are fixed with solder, low melting point metal, heat conductive adhesive, heat conductive grease or the like. 3. The method for manufacturing a semiconductor device according to claim 3.
物又は編物類を固定することを特徴とする請求項１から
請求項３のいずれか１項に記載の半導体装置の製造方
法。5. The method for manufacturing a semiconductor device according to claim 1, wherein a nail or a constriction is provided on an inner surface of the exterior member to fix a fabric or a knit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11090851A JP2000286369A (en) | 1999-03-31 | 1999-03-31 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11090851A JP2000286369A (en) | 1999-03-31 | 1999-03-31 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000286369A true JP2000286369A (en) | 2000-10-13 |
Family
ID=14010093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11090851A Pending JP2000286369A (en) | 1999-03-31 | 1999-03-31 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000286369A (en) |
-
1999
- 1999-03-31 JP JP11090851A patent/JP2000286369A/en active Pending
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