JP2000285696A - Memory test device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory test device which can test a memory such as a mask ROM having a large capacity and the like even if expected value memory capacity existing in the test device is small. SOLUTION: Externally attached value memories 5A-5D are externally attached to a memory test device 1 as an expected value memory storing data of a memory 12 to be tested, and the addressing of the externally attached expected value memory is performed in a flip-flop 2 and counters 3, 4. The read-out data of the externally attached expected value memory is compared with read-out data of the memory 12 to be tested, and the result is outputted to a fail memory in the memory test device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus for performing various inspections on a memory, particularly a large-capacity mask ROM.

[0002]

2. Description of the Related Art Generally, a memory test apparatus includes an expected value memory storing expected value data, a comparator for reading data from a memory under test and comparing the data with the expected value data, and a defect in the memory under test based on the comparison result. And a fail memory for storing data.

FIG. 1 shows a configuration diagram of a conventional memory test apparatus.

[0004] The algorithmic pattern generator 20
It generates X and Y addresses for addressing the expected value memory and the memory under test, and further generates control data for reading. Waveform shaper 26
A shapes the control signal from the algorithmic pattern generator 20 and outputs it to the memory under test via the driver 29A. The address signal from the algorithmic pattern generator 20 is waveform-shaped by the waveform shaper 26B and output to the memory under test via the driver 29B. The selector 21 is an algorithmic pattern generator 2
A necessary one of the address signals from 0 is selected and output to the expected value memory 22. The expected value memory 22 stores expected value data, and has at least the size of the memory to be inspected. In addition, an extremely high-speed SRAM or the like is adopted as the expected value memory 22. The selector 23 is
A necessary one of the address signals from the algorithmic pattern generator 20 is selected and output to the fail memory 24. The fail memory 24 stores a result of mismatch between expected value data and data read from the memory under test.
The switch 25 switches between data from the algorithmic pattern generator 20 and data from the expected value memory 22 and supplies the data to one input of the waveform shaper 26C and the comparator 27. The output of the switch 25 is waveform-shaped by the waveform shaper 26C, and then output to the memory under test via the driver 29C.

The data read from the memory under test is converted to a logical level by the comparator 30 and is output to the comparator 2.
7 is output to the other input terminal. The comparator 27 compares the data read from the memory under test with the data in the expected value memory 22 read via the switch 25 to determine a mismatch, and stores the result in the fail memory 24. Reference numeral 28 denotes a timing generator which generates all necessary timings in the test apparatus.

[0006]

The conventional memory test apparatus having the above configuration is under the following circumstances.

(1) When the memory to be inspected is a mask ROM, which is a representative of a read-only memory, the memory capacity of the expected value memory for storing the expected value becomes enormous, and the price of the test apparatus rises. Has occurred. As the memory to be inspected, products of 256 Mbits or more have already been mass-produced, and it is expected that the capacity will continue to expand in the future. At present, a test device having an expected value memory of about 256 Mbits can correspond to a mask ROM having the largest capacity. If the capacity is further increased, there is no test device capable of testing the same.

(2) In the memory test apparatus, it is necessary to provide a fail memory as shown in FIG. 1, but as the capacity of the mask ROM increases, the capacity of the fail memory also needs to be increased.

(3) As the miniaturization progresses, a plurality of types of mask ROMs may be mixedly mounted on one wafer. In such a case, there is a demand for increasing the capacity of the expected value memory. For example, as shown in FIG. 2, when four types (A, B, C, and D) of ROMs are created on one mask, a case where eight probe cards of four rows and two columns are simultaneously measured. Considering that, from the touchdown at the right end of the first row (contact to the chip of the probe card), moving to the right end from the second row changes the chip arrangement at the time of simultaneous measurement of eight chips. That is, the ROM of the chip at the upper left of the probe card is changed from A to B. Therefore, it is necessary to appropriately change the ROM data of each chip depending on the touchdown location.
The task of storing all data and switching between them according to the chip can only be handled by increasing the capacity of the expected value memory.

(4) When used as a boot ROM of a personal computer, a plurality of mask ROMs are mounted in parallel on a card board. However, a card having a wide bit width (memory card) has a limited number of bits. Can not be tested with existing memory test equipment with

As described above, the memory test apparatus in which the expected value memory and the fail memory are previously built in the test apparatus main body has a problem that it cannot cope with the rapid increase in the capacity of the mask ROM. For this purpose, there has been a problem that an expected value memory and a fail memory provided in advance inside the test apparatus must be replaced with a very high-cost test apparatus having a large capacity. Further, in order to support a memory card having a large number of bits, it is necessary to replace the test apparatus with a large number of bits.

An object of the present invention has been made in view of the above situation, and even if the expected value memory capacity existing in the test apparatus main body is small, a large mask RO is required.
It is an object of the present invention to provide a new memory test device capable of testing memories such as M.

Another object of the present invention is to provide a novel memory test apparatus which can also test a memory card having a wide bit width (mask ROM card) using a conventional test apparatus having a small expected memory capacity. To provide.

[0014]

In order to solve the above problems, the present invention comprises the following means.

(1) An expected value memory storing expected value data, a comparator for reading data from the memory under test and comparing with the expected value data, and a fail memory storing defective data of the memory under test based on the comparison result And a memory test apparatus having an external expected value memory external to the test apparatus main body, and comparing an address counter of the external expected value memory with read data of the memory and read data of the memory under test. And an output circuit for outputting the result of the comparison to a fail memory of the memory test apparatus main body.

According to the present invention, the memory test device itself uses a memory test device that exists regardless of the capacity of the memory to be tested. That is, the expected value memory provided in the memory test apparatus is not used for the test itself, but an externally attached external expected value memory is used for the test instead. In this case, there is no need to use an externally attached external expected value memory having a speed higher than that of the memory to be inspected. Therefore, as long as a relatively low-speed memory such as a mask ROM is used as the memory to be inspected, the external expected value memory need not be high-speed. Therefore, even if the memory to be inspected has a large capacity, it is possible to avoid an increase in the cost of the external expected value memory.

In order to externally connect an external expected value memory,
An address counter for this addressing is also prepared as an external circuit, and a comparison circuit for comparing the read data of the external expected value memory with the read data of the memory under test is also prepared as an external circuit. The fail memory in the test apparatus main body is used as it is, and an output circuit for outputting the same is also provided as an external circuit. The fail memory stores the defective data (defective address) of the memory to be inspected, but the data can be compressed and stored here. If such a compression method is used, it is not necessary to make the capacity of the memory under test and the capacity of the fail memory one-to-one, and the capacity of the memory under test versus the capacity of the fail memory = n: 1 (n is a compression ratio). It can be. Therefore, by appropriately setting the compression ratio n, it is possible to sufficiently cope with an increase in the capacity of the memory to be inspected.

(2) A plurality of external expected value memories can be connected, and a selection circuit for selecting one of the external expected value memories as a usable memory is provided.

A plurality of external expected value memories can be connected, and a selection circuit for selecting any one of the memories is provided.
One memory test device can be used. Also,
If the configuration is such that the external expected value memory is switched for each chip with respect to a wafer having a plurality of mask ROMs as shown in FIG. 2, a test can be easily performed on these plurality of mask ROMs.

(3) The address counter includes a counter for directly counting the address of an external expected value memory corresponding to a unit area for redundancy repair of the memory under test.

Normally, the memory under test is subjected to redundancy repair, and the redundancy repair is generally performed in units of banks of a specific capacity in the column direction or row direction of the memory. It is. In the present invention, the address counter provided as an external circuit includes a counter that directly counts the address of the external expected value memory corresponding to the unit area (bank unit area) for redundancy rescue. By providing such a counter, it is possible to easily and reliably read data from the external expected value memory when performing the redundancy relief.

[0022]

FIG. 3 is a block diagram of a memory test apparatus according to an embodiment of the present invention.

Referring to FIG. 1, reference numeral 1 denotes a memory test device main body, which is the conventional memory test device itself shown in FIG. 12 is a memory under test (MUT),
Here, a serial mask ROM will be described as an example. The serial mask ROM is based on page access. One page is 256 words (× 16 bits), for example, and 256 sequential accesses are possible within the page. Address and data are multiplexed on the data bus.
FIG. 4 shows a timing waveform of the serial mask ROM.

The control signals are ALEH, ALE
L and / RD, and the rest is an address / data bus 16
It consists of bits (AD0 to AD15). The address signal is divided into an upper address and a lower address, and the MUT 12
Set to. The upper address is captured at the falling edge of the ALEH signal, and the lower address is captured at the falling edge of the ALEL signal. After fetching the lower address, 256 data can be sequentially read only by changing the / RD signal with only the read latency (t ₁ ). The time from the falling of the / RD signal to the output of the data is the access time (t _RD ).

FIG. 5 shows an internal configuration image of a 128-Mbit serial mask ROM. One page has 256 words, and is composed of 32K pages. In this example, replacement is performed in units of banks consisting of 64 addresses in the column direction.

In FIG. 3, reference numerals 5A to 5D denote external expected value memories. Each external expected value memory has a capacity of 128 Mbits, similar to the MUT 12.

The memory test apparatus main body 1 generates a signal necessary for testing the MUT 12 and a signal necessary for operating each external circuit according to the embodiment of the present invention.
As external circuits for addressing the external expected value memories 5A to 5D, a 9-bit flip-flop 2, a 6-bit up counter 3, and an 8-bit up counter 4 are provided. The flip-flop 2 latches the upper address of the memory and is reset every time one page test is performed. The counter 3 latches the upper bits (8 to 13) of the lower address and simultaneously counts up automatically according to the clock signal. 4 is an 8-bit up counter, and the lower bits (0 to 7) of the lower address
And automatically count up according to the clock signal.

The comparison circuit of the present invention comprises a 16-bit flip-flop 7.8, an XOR gate 9, and a multiplexer 10. The flip-flop 7 latches an output from the external expected value memory at a clock timing, and the flip-flop 8 latches output data from the MUT 12 at a clock timing. The XOR gate 9 performs a mismatch determination for each bit of the flip-flops 7 and 8, and outputs the result. When they do not match, 1 is output, and the multiplexer 10 switches 16-bit data at a time.
The 16-bit output of the R gate 9 is selected.

A multiplexer 6 serving as a selection circuit of the present invention is provided at a stage preceding the flip-flop 7, and an external expected value memory 5 is provided based on a switching signal 6S.
Select one of a to 5d.

S output from the memory test apparatus main body 1
TROB1 and STROB2 are output to flip-flops 8 and 7 via OR gate 11.

The switch 1 as an output circuit of the present invention
3A and 13B operate in conjunction with the SW signal from the memory test apparatus main body 1 and turn on 13A off and 13B on when supplying an address to the MUT 12;
When the output of the gate 9 is taken into the memory test apparatus main body 1, 13A is turned on and 13B is turned off.

The counter 3 for addressing the external expected value memory counts up the upper bits (8 to 13) of the lower address as described above. The count-up direction is the column direction in FIG. That is, the column direction (bank direction) of the external expected value memories 5A to 5D corresponding to the relief bank shown in FIG.
Is directly and continuously counted. The counter 3 is for reading out data of an external expected value memory corresponding to a bank of 64 addresses × 1 bit including the defective bit by directly and continuously counting up when a defective bit is found in the MUT 12. is there. By counting up the counter 3, the data of the external expected value memory corresponding to the bank having the defective bit is read, the data of the defective bank is prepared, and the data is stored in the redundant area on the MUT 12 in a later step. The data can be written (by laser trimming or the like).

A configuration in which a plurality of mask ROMs are connected like the external expected value memories 5A to 5D is used, for example, in a case where each mask ROM is simultaneously tested on a wafer on which a plurality of types of mask ROMs are mixed as shown in FIG. Useful for In the example shown in FIG. 2, since four types of mask ROMs A to D are mixed, in this case, four types of mask ROMs corresponding to these A to D are used as external expected value memories. External expected value memories 5A to 5D are connected.

The multiplexer 6 is used to switch an external expected value memory corresponding to a mask ROM to be inspected, and the switching is performed by a switching signal 6s output from the memory test apparatus main body 1.

In the flip-flops 7 and 8 and the XOR gate 9 constituting the comparison circuit, the MUT 12 and the external expected value memories 5a to 5a to 1 word (see FIG. 5) are provided.
Compared to any one of 5d, when the values do not match, 1 is set at the output of the XOR gate 9.

The multiplexer 10 selects the output of the XOR gate 9 according to the MPX signal during the test. When reading the corresponding data of the bank to be relieved from the external expected value memory, the output of the flip-flop 7 is selected.

Switches 13A and 13B serving as output circuits
Turns off 13A when sending address data of the upper address and the lower address to the MUT 12;
B is turned on, and on / off switching is performed during the read latency t _L. This is to prevent the data output from the MUT 12 from colliding with the output of the multiplexer 10 when the MUT is in the read mode, so that the output of the multiplexer 10 can be correctly taken into the test apparatus main body 1. Note that since the read latency is about 1 us, this switch 13A, 1
3B can be easily configured by using a semiconductor switch.

STROB from memory test apparatus main unit 1
Reference numeral 1 denotes a clock for incrementing the counter 4, which increments the addresses of the external expected value memories 5a to 5d in synchronization with the in-page counting operation of the MUT 12. STROB2 is a clock for incrementing the counter 3, and is used to continuously read data from the external expected value memory corresponding to the bank to be relieved as described above. Also, upper address data for determining a page is supplied to the flip-flop 2.

FIG. 6 shows an operation timing chart.

The upper address of $ 00 ($ represents hexadecimal notation) by the signal of ALEH,
00 is output to the MUT 12 and read
The switches 13A and 13B are switched during the period of the latency t _L , and the mode shifts to the read mode of the MUT 12. Also,
$ 00 for flip-flop 2 and $ 00 for counter 3
Are set respectively. After the read latency t _L period has elapsed, the counter 4 is synchronized with the STROB1 signal.
Starts counting up to $ 01, $ 02, and $ 03. In accordance with this, data is read from the external expected value memory. Data is also read from the MUT 12. These data are latched by the flip-flops 7 and 8, respectively, and compared by the XOR gate 9.

In the example shown in FIG. 6, the output from the MUT 12 is $ 3332 with respect to the expected value data $ 3333 at the lower address $ 02, so that the data corresponding to bit 0 of the MUT 12 is defective. Is determined. This result is stored in the fail memory (see FIG.
Reference 24). The fail memory 24
In FIG. 5, the bank area shown in FIG. 5 is compressed to 1 bit and stored. Therefore, in the subsequent read test,
Lower address in the range of 64 addresses in the column direction $ 02
No change occurs in the data stored in the fail memory 24 even if a failure occurs in the bit 0 of the memory. The fail memory 24
As for the data compression of A, a known method can be adopted, and thus a specific configuration and method will not be described here.

After the test mode is completed, the bank area corresponding to the bit standing in the fail memory 24 is regarded as a bank to be rescued, and it is necessary to know the address to replace the data in the area. Understand. That is, when the address of the bank to be relieved is known, it is necessary to read data (expected value data) from the external expected value memory corresponding to the bank. To execute this, after the test mode is completed, the selection signal of the multiplexer 10 is set as the output signal of the flip-flop 7 by the MPX signal, the top page address of the bank to be relieved is set in the flip-flop 2, and the counter 3 Is continuously read out by counting up by the STROB2 signal. At this time, an address corresponding to the bank position in the page address direction (row direction) is set as a fixed address in the counter 4.

When a plurality of external expected value memories are connected, they are switched by a switching signal 6 s. This switching is performed not by the signal from the memory test apparatus main body 1 but by the ROM data of the MUT 12. Can be automatically performed by a signal that directly identifies

In the above configuration, the MUT 12 is exemplified by a 128-Mbit serial mask ROM, but if the capacity increases, the capacity of the external expected value memory also increases accordingly. However, MUT
As long as 12 is a relatively low-speed memory such as a ROM, it is not necessary to use an expensive memory as the external expected value memory 5. At least the speed of the MUT 12 may be sufficient.
Also, depending on the capacity of the MUT 12, it is necessary to increase the number of bits of the address counter, the comparison circuit, and the like. And it is easy to replace the element itself if necessary. Further, the MUT 12 is not limited to a serial mask ROM, but can be a normal ROM in which addresses and data are separated. In addition, application to a memory card having a wide bit width can be easily achieved only by providing a plurality of circuits shown in FIG. 3 and changing the selection of an external expected value memory for each circuit. Since the memory test apparatus main body 1 generally has a multiple simultaneous measurement function, the number of drivers, comparators, and the like does not run short.

Further, as the external expected value memory 5,
If a rewritable memory such as an SRAM or a flash memory is used that is sufficiently fast to access, it is possible to perform the writing operation from the memory test apparatus main body 1 at the start of the test. Since the data is written only once, even if it takes some time, the test processing performance is not affected at all. In this case, the data can be easily handled by transferring data to the large-capacity external expected value memory while rewriting the data of the small-capacity expected value memory in the memory test apparatus main body several times. Further, the circuit shown in FIG. 3 can be mounted in a place such as a probe card or a performance board connected to the memory test apparatus main body 1. In this case, MUT1
2 can be made sufficiently small, so that a test can be performed with high accuracy and at high speed.

Since the circuit shown in FIG. 3 intervenes between the MUT 12 and the memory test device main unit 1, the device main unit 1
However, this can be easily dealt with by inserting a buffer into the signal line.

[0047]

According to the present invention, a memory test of a large-capacity mask ROM or the like can be performed at low cost by using an existing memory test apparatus having a very high-speed and expensive expected value memory.

Further, by providing a selection circuit for selecting a plurality of external expected value memories, it is possible to automatically select an expected value memory according to a memory to be inspected. For example, a plurality of mask ROMs are mixedly mounted on a wafer. Can be easily handled.

Further, even when a mask ROM capable of redundancy repair is used as the memory to be inspected, expected value data necessary for the redundancy repair can be easily read.

In addition, by merely arranging a plurality of address counters, comparison circuits, and output circuits in parallel with respect to the external expected value memory, a memory card in which a plurality of mask ROMs are arranged in parallel to increase the bit width is used. Can be easily tested.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a conventional memory test apparatus.

FIG. 2 is a diagram showing a touchdown image when simultaneously testing a wafer on which several types of mask ROMs are mixed and eight wafers.

FIG. 3 shows an example of a timing waveform of a serial mask ROM.

FIG. 4 is a configuration diagram of a memory test device according to an embodiment of the present invention;

FIG. 5 is an internal configuration image diagram of a 128M bit mask ROM.

FIG. 6 is an operation timing chart.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA08 AC03 AE07 AE08 AE10 AE12 AG07 AH03 AH04 AK03 AL01 AL16 5L106 AA07 DD22 DD24 FF05 GG05 9A001 BB03 JJ45 KK37 LL05

Claims (4)

[Claims] An expected value memory storing expected value data, a comparator for reading data from a memory under test and comparing the data with the expected value data, and a fail memory storing defective data of the memory under test based on the comparison result. , An external expected value memory external to the test apparatus main body is provided, and an address counter of the external expected value memory is compared with read data of the memory and read data of the memory under test. A memory test device, comprising: a comparison circuit; and an output circuit that outputs a result of the comparison to a fail memory of the memory test device main body. 2. The memory test apparatus according to claim 1, wherein a plurality of external expected value memories can be connected, and a selection circuit for selecting one of the external expected value memories as a usable memory is provided. 3. The memory test apparatus according to claim 1, wherein said address counter includes a counter for directly counting an address of an external expected value memory corresponding to a unit area for redundancy repair of a memory under test. 4. The memory to be inspected is a serial mask ROM.
The memory test device according to claim 1, wherein: