JP2000285082A - Central processing unit and compiling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a central processing unit(CPU) capable of effectively executing speculative processing while furthermore reducing the storage quantity of information, the quantity of hardware or throughput. SOLUTION: The CPU provided with plural operation execution units 8 to 11 and capable of allocating respective units 8 to 11 in the case of executing an interpreted instruction is also provided with a group value generation part 6 for providing a group value for identifying which instruction group obtained by dividing an instruction string of a program by a specific instruction includes an instruction concerned to the instruction at the time of executing it, speculation judging parts 12 to 15 for judging whether the execution of an instruction is speculative or not by using the group value applied to the instruction and a register retreating part 16 for storing information for restoring a register updated by a speculatively executed instruction to a state held before the execution of the instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a central processing unit capable of executing a plurality of instructions in parallel and a compiling method for generating a program executed by the central processing unit.

[0002]

2. Description of the Related Art Improving the degree of instruction parallelism is one of the methods for improving the performance of a computer system. As a method of increasing the parallelism at the instruction level, there are basically two different methods, that is, a VLIW (Very Long Instruction) which statically allocates and uses resources at compile time.
Tion Word) system and a superscalar system that dynamically allocates resources at the time of execution.

A program executed by a VLIW processor or a superscalar processor usually contains a large number of conditional branch instructions and load / store instructions. Execute the next instruction by predicting the branch destination of the conditional branch instruction before the branch destination is determined, or execute the subsequent instruction before it is guaranteed that the load / store instruction does not generate a page fault. In such a case, the execution of these instructions is speculative, but by enabling speculative instruction execution, the instruction parallelism of the system is further improved.

Conventionally, there are a reorder buffer method and a checkpoint method as speculative instruction execution methods. Hereinafter, these methods will be described.

[0005] The reorder buffer method uses the conventional out
-Of-order This is a method used in a superscalar processor. This superscalar processor includes a reorder buffer as a mechanism for ensuring that the operation results executed in out-of-order are reflected in the state of the processor in program order.
In order to describe a speculative instruction execution method using a reorder buffer, first, an out-of-order execution method using a reorder buffer will be described.

An out-of-order superscalar processor selects as many executable instructions as possible from a group of decoded instructions whose input operands are fixed, and executes them simultaneously. An instruction can be executed as long as its operands are available and the operation execution unit (arithmetic unit) has room, even if the preceding instruction is not executable. So the instruction is sometimes out-of-order
Executed in Regardless of whether it is speculative or not, the operation result is not directly written in the register but is once registered in the reorder buffer.

When registering an operation result in the reorder buffer, a unique virtual register name is assigned to each operation result. That is, even in a plurality of operations that output the same register, the virtual registers corresponding to the operation results are different from each other. In the subsequent instruction execution, the input register name is changed to the virtual register name, and the value is read from the reorder buffer and the register. This is called a register renaming mechanism.

For example, in the program shown in FIG. 43, the output register r for the instruction "li" of the instruction number 1
2 and the output register r in the instruction “lw” of the instruction number 3
2 is $ 10 and $ when reorder buffer is registered
Assuming that a virtual register name such as "12" is assigned, when the instruction "add" of the instruction number 2 is decoded, r
Register renaming from $ 2 to $ 10 is performed, and when the instruction "sll" of instruction number 4 is decoded,
Register renaming from r2 to $ 12 is performed. When the instructions 2 and 4 read the register, if the operation result corresponding to the virtual register exists in the reorder buffer, the result is read. Otherwise, the value of the real register r2 is read. It is.

The result of the instruction registered in the reorder buffer is reflected in the register after confirming that the results of all the preceding instructions in the program order have been written in the register. This guarantees that the result calculated by out-of-order is reflected in the state in the order of programming.

In the out-of-order execution method using the reorder buffer described above, speculative execution of an instruction is realized as follows (M. Johnson).
n, “Superscalar Microproce
ssor Design ”, Prentice-Hal
1, 1991).

If the branch prediction of the conditional branch instruction is incorrect, or if the load / store instruction generates a page fault, the operation speculatively executed becomes erroneous, and the result is not reflected in the register. Need to cancel. In this case, the processor waits for the completion of the instruction located before the instruction in which the branch prediction error or the page fault is confirmed, and then traps the instruction. In the trap, first, all instructions being executed in the pipeline are canceled.

The result registered in the reorder buffer is also canceled at the time of trap. The result of the instruction before the instruction causing the trap does not exist in the reorder buffer because it has already been completed. On the other hand, the result of the speculatively executed instruction after the instruction causing the trap is not reflected in the register due to cancellation of the reorder buffer. In this way, it is possible to cancel only the operation performed speculatively.

When the cancellation of the pipeline and the reorder buffer is completed, the program counter is changed to the correct branch destination address in the trap of the conditional branch instruction and to the address of the instruction in the trap of the load / store instruction. The trap processing ends.

If the speculatively executed operation is correct, the result is reflected in the register after completion of all previous instructions.

As described above, speculative execution using the reorder buffer is realized.

On the other hand, the checkpoint method is a method used in both conventional superscalar processors and VLIW processors. In this method, the state of the processor at that time is stored at a checkpoint on the program. The result of speculative instruction execution is directly reflected in the register.

When the speculative instruction execution is found to be incorrect by the execution of the conditional branch instruction or the load / store instruction, a trap is generated, and the processor of the processor reaches a checkpoint before the result of the speculative instruction execution is reflected. By returning the state, the result of the speculative execution is cancelled. And by re-executing non-speculatively until the instruction that caused the trap,
Again, it is ensured that malfunction due to speculative execution does not occur. Unnecessary checkpoint states are discarded when the speculatively executed instruction is guaranteed to be correct.

Regarding how to checkpoint,
First, a method of counting the number of elapsed clocks and the number of executed instructions and taking a checkpoint when the number reaches a certain number is available. In this method, if the interval for taking checkpoints is long, many instructions must be executed at the time of re-execution, and if the interval is short, processing for taking checkpoints becomes a heavy load.

As a method of solving this problem, it is necessary to analyze in advance how much information needs to be stored for executing an instruction, and to add the information to a code to reduce the information to be stored. In addition, there is also proposed a method of executing non-speculatively when there is not enough area to store the information (“Processor St”).
structure and Method for Ch
ekpointing Instructions
to Maintain Precision Stat
e ", U.S. Pat. No. 5,659,721. This method is applicable to both conventional in-order instruction issuing superscalar processors and VLIW processors.

In a general checkpoint method, all states of a processor including a state register are stored for each checkpoint. When an instruction is executed speculatively over a plurality of checkpoints, it is necessary to save the state of all checkpoints between them. Thus, speculative execution is limited to the number of states that can be saved.

On the other hand, in the method of storing all the registers, it is possible to prepare a plurality of sets of hardware registers and provide a checkpoint state for each set. According to this method, the operation of returning the state of the processor to the checkpoint can be performed only by switching the register set to be used, so that there is an advantage that the state can be restored at a high speed.

[0022]

Among the speculative execution methods described above, the reorder buffer method has a problem in that complicated hardware is required to realize the reorder buffer. First, in order to determine whether the result of a certain operation can be reflected in the register, the reorder buffer displays instructions in the instruction window that stores the decoded instruction and the instruction that precedes the operation in program order. It is necessary to perform a comparison process to confirm that there is no data. In order to increase the chances of being executed in the out-of-order, the size of the reorder buffer and the instruction window needs to be increased. However, as these sizes increase, the hardware required for this comparison becomes complicated. become. Also, when the number that can be reflected in the register is increased at the same time, the hardware for comparison also becomes complicated.

Further, in the reorder buffer method, a register renaming mechanism is indispensable in order to speculatively execute a plurality of instructions to be written in the same register so that the result of speculative instruction execution is not directly reflected in the register. Become. The hardware for this register renaming mechanism is also complicated.

As described above, the reorder buffer method is as follows.
This is a method applied to a processor such as an out-of-order superscalar processor which is assumed to have complicated hardware. Therefore, it cannot be used for a processor based on an idea such as VLIW which aims to improve the performance by increasing the operating frequency by simplifying the hardware. Also, it is difficult to apply to a processor in which low power consumption and low cost are important, such as an embedded processor.

On the other hand, in the checkpoint method,
To increase the chances that an instruction is executed speculatively, it is necessary to save the state at more checkpoints. In a general checkpoint method, it is necessary to save the state of all registers for each checkpoint, and to save and restore the state at high speed, it is necessary to prepare a plurality of register sets in the processor . The cost of the hardware for this is large,
It is difficult for a general-purpose processor to have three or more register sets.

In the method of reducing the state to be saved at the checkpoint, the state to be saved needs to be added to the code. Therefore, when applied to a superscalar processor, the instruction set architecture needs to be changed. It is difficult to maintain compatibility with the architecture. The application area of this method is limited to an in-order instruction issuing processor.

The present invention has been made in view of the above circumstances, and provides a central processing unit and a compiling method capable of storing less information and effectively performing speculative execution with a smaller amount of hardware or processing. The purpose is to provide.

[0028]

Means for Solving the Problems The present invention (first invention)
A central processing unit (e.g., a superscalar processor that issues in-order instructions) that includes a plurality of operation execution units and allocates the execution units when executing the instruction sequences of the program. An identification number for assigning an identification number (for example, a group value) for identifying which instruction in a program section the instruction belongs to when divided by a predetermined specific instruction for each instruction during its execution An assigning unit (for example, a group value generating unit) and a speculative determining unit (for example, a speculative determining unit) that determines whether or not execution of the instruction is speculative using the identification number assigned to each instruction. It is characterized by having.

According to a second aspect of the present invention, there is provided a central processing unit having a plurality of operation execution units for fetching and interpreting an instruction sequence of a program for each of a series of instructions assigned to each of the operation execution units in advance. Device (eg, out
-Of-order instruction issuance VLIW), instruction storage means for temporarily saving an instruction that has been fetched but cannot be executed (to enable subsequent instructions to be executed in advance) (for example, Pending queue), storage means for storing information on the usage status of each register, and determining whether or not the fetched instruction is executable based on the information stored in the storage means,
Means for temporarily storing the instruction in the instruction storage means when it is determined that the instruction cannot be executed; and instructions belonging to any of the program sections when the instruction sequence of the program is divided by a predetermined specific instruction. An identification number (for example, a group value) for identifying each of the instructions at the time of execution of the identification number (for example, a group value), and the identification number assigned to each of the instructions. And a speculativeness judging unit (for example, a speculativeness judging unit) for judging whether the execution of the instruction is speculative.

Preferably, the identification number assigning means holds information indicating whether each identification number is in use or not, and when an instruction to which an identification number is to be assigned is the specific instruction, the identification number assigning means stores the information. Means for selecting and assigning an identification number that is not in use by reference, and when an instruction to be assigned an identification number is an instruction other than the specific instruction, means for assigning the same identification number as the identification number assigned immediately before (For example, a bit vector method).

Preferably, the speculativeness judging means includes, for each of the identification numbers assigned by the identification number assigning means, information indicating whether or not a specific command assigned with the identification number is being executed. Based on the above, when it is indicated that a specific instruction having the same identification number as the identification number assigned to the instruction to be determined is being executed, execution of the instruction as the determination target is It may be determined that it is speculative.

Preferably, the identification number assigning means includes an identification number counter means for holding an identification number assigned to a command immediately before, and an identification number adding means for assigning an identification number to a command other than the specific instruction. Assigning the same identification number as the identification number held in the counter means, and when the instruction to be given the identification number is the specific instruction, the identification number held in the identification number counter means Means for adding the increased identification number after incrementing by one (for example, a hardware counter method).

Preferably, the identification number has the same initial state as that of the identification number counter means, and when the execution of the specific instruction to which the identification number is given is completed using the identification number counter means, the identification number to be held is changed. Further comprising execution instruction counter means for incrementing the execution instruction counter by one, wherein the speculative judgment means refers to the identification number counter means and the execution instruction counter means, and the identification number given to the instruction to be determined is the execution number. If the identification number corresponds to an identification number within a range from the identification number held by the instruction counter means to the identification number held by the identification number counter means, the execution of the instruction as the determination target is speculative. You may make it determine.

Preferably, the apparatus further includes means (for example, a register saving unit) for holding information for restoring a register updated by an instruction determined to be speculatively executed to a state before execution of the instruction. It may be.

Preferably, in the second invention, the instruction accumulating means, together with the fetched but unexecutable instruction, includes an identification number assigned to the instruction and whether the instruction corresponds to the specific instruction. Information indicating whether or not the information may be held may be held.

Preferably, in the second invention, when the instruction is issued from the instruction storage means, the instruction of the specific instruction may be issued in a program order.

Preferably, when it is determined that the speculative execution of the instruction determined to be speculatively executed has failed, a trap corresponding to the cause of the failure is trapped, and the speculation is performed by a trap routine. You may make it return to the state before the target execution.

[0038] Preferably, the specific instruction may be an instruction corresponding to a conditional branch instruction. Preferably, the specific instruction may be an instruction corresponding to a load instruction or a store instruction. further,
Preferably, the specific instruction may be an instruction corresponding to a Predicate set instruction.

Preferably, in the second invention, the specific instruction is a conditional branch instruction, a load instruction, a store instruction, or any of the other instructions determined to be unexecutable because output operands cannot be used. The instruction may correspond to any of the above.

Preferably, the speculativeness judging means judges whether or not the execution of only the SYNC instruction for restricting the speculative execution is speculative, and judges that the SYNC instruction is speculatively executed. In such a case, an instruction subsequent to the SYNC instruction may not be executed until the specific instruction input earlier in the program order than the SYNC instruction is completed.

According to the present invention (third invention), a central processing unit (for example, an in-order unit) for allocating a plurality of execution units when executing an instruction sequence of a program.
An instruction issuing super scalar processor) or a central processing unit (for example, an out-of-order instruction issuing VLIW processor) which fetches and interprets a sequence of instructions of a program for each of a series of instructions assigned to each of a plurality of operation execution units in advance. Wherein the output operand of an instruction arranged on one path branched from the conditional branch instruction is updated in the other path branched from the conditional branch instruction. The instruction placed on the one path and the instruction having an output operand that matches one of the input operands of the speculatively executed instruction in the case where the instruction is referred to by another instruction, SYNC for restricting speculative execution so that it is not speculatively executed in an arithmetic unit And allocating to generate decree. Note that, when the SYNC instruction is speculatively executed by the central processing unit, the SYNC instruction is executed until a specific instruction which is input prior to the SYNC instruction in program order and causes speculative execution is completed. This is an instruction for controlling not to execute an instruction subsequent to the instruction.

Next, the present invention (fourth invention) comprises a plurality of operation execution units, and a central processing unit for fetching and interpreting an instruction sequence of a program for each series of instructions assigned to each of the operation execution units in advance. An arithmetic unit (for example, in-
In an order instruction issuing VLIW processor), when an instruction sequence of the program is divided by a predetermined specific instruction, an identification number (for example, an identification number) for identifying to which of the program sections the instruction belongs. A group value), and information relating to the speculative property of the instruction, and a means for extracting the information at the time of interpreting the instruction; and
A speculativeness determining means for determining whether or not the execution of the instruction is speculative; and a speculative characteristic based on the identification number and the information on the speculativeness incorporated in the instruction determined to be speculatively executed. Speculative result determining means for determining whether or not speculative execution has succeeded, and when it is determined that speculative execution has failed for an instruction determined to have been speculatively executed, trapping is performed according to the cause of the failure. And a hanging means.

Preferably, the speculativeness judging means judges that the execution of the instruction is speculative when the information on the speculativeness incorporated in the instruction to be judged indicates that the instruction is speculative. You may make it.

Preferably, the speculative result judging means, when an instruction having the same identification number as the identification number incorporated in the instruction to be judged and corresponding to the information relating to the speculative property is executed, It may be determined that the speculative execution of the instruction has failed.

Preferably, when it is determined that the speculative execution of the instruction has failed, holding means (for example, a register saving unit) for temporarily holding save information for returning to a state before performing the speculative execution is provided. ) May be further provided.
In this case, preferably, the evacuation information may be held corresponding to an identification number given to the instruction determined to have been executed speculatively. Further, the return of the state based on the evacuation information may be selectively performed with reference to an identification number in the holding unit.

Next, the present invention (fifth invention) relates to a central processing unit (for example, an in-instruction unit) which fetches and interprets an instruction sequence of a program for each of a series of instructions assigned to each of a plurality of operation execution units in advance. A compiling method for generating a program to be executed by an order instruction issuing VLIW processor), wherein, when an instruction sequence of the program is divided by a predetermined specific instruction, which instruction belongs to a program section is determined. An identification number for identification (for example, a group value) and information on the speculative nature of the instruction are given for each instruction, and an instruction located after the specific instruction in the program order is identified as a cause of the speculative execution. And moving forward beyond the specific command.

According to the present invention, there is provided a central processing unit having a plurality of operation execution units and allocating a plurality of operation execution units when executing an instruction sequence of an execution program, or a plurality of instruction sequences of an execution program in advance. A compilation procedure for generating a program executable by a central processing unit that fetches and interprets a series of instructions assigned to each of the operation execution units, wherein the instructions are arranged on one path branched from a conditional branch instruction. And the instruction placed on one path when the output operand of the instruction is referenced by another instruction without being updated on the other path branched from the conditional branch instruction, and the speculatively executed instruction An instruction whose output operand matches one of the input operands of the instruction is executed speculatively in the central processing unit. No way, a gist of the computer readable recording medium recording the compiled program for executing the compiled instructions to the computer, including the steps of assigning to generate SYNC command to limit speculative execution.

The present invention also provides a compiling procedure for generating a program executable by a central processing unit which fetches and interprets an instruction sequence of an execution program for each of a series of instructions assigned to each of a plurality of operation execution units in advance. When an instruction sequence of the program is divided by a predetermined specific instruction, an identification number for identifying to which of the program sections the instruction belongs, and information on speculativeness of the instruction are stored in each instruction. A compiling procedure including a procedure of giving an instruction every time and moving an instruction located after the specific instruction in the program order beyond the specific instruction causing speculative execution is executed by the computer. And a computer-readable recording medium on which a compiling program is recorded.

It should be noted that the present invention relating to the apparatus is also valid as an invention relating to the method, and the present invention relating to the method is also valid as an invention relating to the apparatus.

The present invention relating to a compiling apparatus or method is provided for causing a computer to execute a procedure corresponding to the present invention (or for causing a computer to function as means corresponding to the present invention, or for causing a computer to execute the procedure corresponding to the present invention) The present invention is also realized as a computer-readable recording medium on which a program (for realizing a corresponding function) is recorded.

According to the present invention, in the instruction processing method for executing speculatively, before executing a specific instruction, for example, a conditional branch instruction or a load / store instruction, instructions following these instructions in program order are speculated. A unique identification number for each program section from (instruction of) the program section from the instruction corresponding to any of the specific instructions to the instruction immediately before the next instruction corresponding to any of the specific instructions Is added to add a specific instruction to the head and manage the instructions immediately before the next specific instruction as a group, so that it is easy to determine whether the instruction has been executed speculatively (comparison of the identification numbers). Only the speculative execution of instructions can be performed), and the information and hardware necessary to cancel the result of speculative execution by mistake can be obtained using the conventional speculative instruction execution method. (Eg, simpler hardware than a reorder buffer and saving less information than a general checkpoint speculative execution method, resulting in more efficient speculative execution). Is possible.).

As described above, according to the present invention, more effective speculative execution of instructions becomes possible by simple hardware and storage of a small amount of information.

This also has the effect that speculative execution becomes possible even in a processor requiring simple hardware. Further, since there is less information to be stored, speculative execution exceeding more branch instructions and load / store instructions can be performed, and the performance is improved as compared with speculative execution using a general checkpoint method. Further, the present invention has an effect that speculative execution by saving a small amount of information becomes possible even in an out-of-order instruction issuing processor having no reorder buffer, such as an out-of-order instruction issuing VLIW processor. is there.

[0054]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) In this embodiment, an in-
This is an embodiment in the case where instructions are speculatively executed by an order instruction issuing superscalar processor.

FIG. 1 is a block diagram showing a configuration example of a processor according to the present embodiment. As shown in FIG.
The processor according to the present embodiment includes a memory 1, an address generation unit 28, an instruction fetch unit 2, an instruction queue 3, an instruction decode unit 4, a group value generation unit 6, a decoded instruction queue 7, an operand state determination unit 5, and an instruction execution unit 8. , 9, a load / store unit 10, a branch instruction execution unit 11,
Processor state control unit 30, speculative judgment units 12 to 15,
It has a register saving unit 16 and a register 17.

The number and functions of the instruction execution units (8 to 11) of the present processor are merely examples, and the present invention is not limited thereto. Also, in the example of FIG. 1, an example is shown in which four register write buses (26 to 29) respectively corresponding to the instruction execution units (8 to 11) are provided.
When a branch instruction with register write is not used, the register write bus corresponding to the branch instruction execution unit 11 is omitted.

In this embodiment, in the instruction sequence to be executed by the processor, the instruction starting from the instruction corresponding to the conditional branch instruction or the load / store instruction, and the instruction immediately before the next instruction corresponding to the conditional branch instruction or the load / store instruction are used. The part ending with is called an “instruction group”. That is, the first instruction in the instruction group is an instruction corresponding to a conditional branch instruction or a load / store instruction, and an instruction corresponding to only one conditional branch instruction or a load / store instruction in the instruction group. Further, in the present embodiment, in order to identify which instruction group each instruction belongs to in the processor, each instruction is given a “group value” unique to the instruction group to which it belongs.

The outline of the main units of the processor shown in FIG. 1 is as follows. The group value generation unit 6 is a unit for generating a group value to be given to the decoded instruction. The operand state determination unit 5 is a unit for determining whether the operand used by the decoded instruction is usable. The processor state control unit 30 is a unit for controlling the instructions corresponding to the conditional branch instruction or the load / store instruction so that their completion order does not change. The speculativeness judging units 12 to 15 are units for judging whether an instruction to be executed is speculative based on a group value. The register saving unit 16 is a unit for storing an original value of a register before updating a corresponding register when an instruction is speculatively executed.

The processor of this embodiment is schematically
If the branch prediction of the conditional branch instruction is incorrect or a page fault occurs during the execution of the load / store instruction, a trap is set, the value stored in the register save unit 16 is restored to the register 17, and then the instruction is executed. The speculativeness of the instruction can be determined only by comparing the group values, and the instruction can be speculatively executed by simple hardware and saving a small amount of information.

Next, FIG. 2 shows an example of the flow of pipeline processing in the processor of the present embodiment.

The instruction fetch unit 2 includes an address generation unit 28
Are designated on the address bus 33, and a plurality of instructions starting from the instruction are fetched from the memory 1 via the instruction fetch bus 34 (step S1).
1). The fetched instructions are inserted into the instruction queue 3 via the instruction queue bus 32 in the order of fetch.

The instruction decoding unit 4 decodes a plurality of instructions from the head of the instruction queue 3 via the decode bus 35, and obtains the type and operand of each instruction (step S12). Further, after obtaining the group value of each instruction from the group value generation unit 6 (step S13), the decoded instruction is inserted into the decoded instruction queue 7.

For the decoded instruction, the operand state determination unit 5 determines in order from the head of the decoded instruction queue 7 whether or not the operand is usable (step S14). Then, the operand is usable and the instruction is executed. If there is a free space in the instruction execution unit, the instruction execution unit 8, the instruction execution unit 9, the load / store unit 1 together with the group value according to the type of the instruction.
0, the instruction is transferred to any of the branch instruction execution units 11 via the corresponding instruction buses 18 to 21 and the operand is fetched from the register 17 via the corresponding register read buses 22 to 25, and then the instruction is executed. (Step S15).

After the execution of the instruction, the corresponding speculative judgment section 12
It is determined whether or not the instruction execution is speculative according to (15) (step S17). If the instruction execution is speculative, the "identification information of the register to be changed", the "value before change of the register", and the " The instruction group value is registered in the register saving unit 16 in association with the instruction group value (step S18).

Then, the execution units (8 to 11) permitted to update the state by the processor state control unit 30 execute the corresponding register write buses 26 to 29 and memory bus 3
Then, the execution result is written back to the register 17 and the memory 1 via step 1 (step S19).

The reason why the execution of the instruction becomes speculative is as follows.
The following is the case. When executing an instruction at a predicted branch destination before completion of a conditional branch instruction. When executing subsequent instructions before completion of a load / store instruction. First, speculative execution of a conditional branch instruction will be described. .

When executing a conditional branch instruction, an instruction address to be fetched next is predicted by a branch prediction mechanism provided in the address generation unit 28 (eg, JA Fi).
sher and S.M. M. Freudenberg
r, "Predicting Conditional
Branch Directions fromPre
visible Runs of a Program ",
in Proceedings of the 5th
International Conference
on ASPLOS, 1991). The next instruction fetch is started without waiting for the completion of the conditional branch instruction. The branch instruction execution unit 11 compares the branch prediction result with the actual branch destination, and if they are different, performs a branch prediction mistrap after completion of all the instructions being executed.

The processor has means for examining the cause of the trap. Causes of the trap include a branch prediction error, a page fault, and the like. When it is determined by this means that the trap is caused by a branch prediction error (step S16), first, the instruction queue 3 and the decode instruction queue 7 are emptied to invalidate the fetch process and the decode process being executed (step S20). ). Next, the value of the register registered in the register saving unit 16 is returned to the original value (step S21), and the state of the group value generating unit 6 is reset. Then, after setting the address indicated by the address generation unit 28 to the correct branch destination, the trap processing is completed.

Next, speculative execution exceeding a load / store instruction will be described.

Generally, virtual addresses are used for reading from and writing to memory. A part of the virtual address area is stored in the memory 1, and the others are stored in an external storage device (not shown). If the value of the specified virtual address does not exist in the memory 1 when executing the load / store instruction, a page fault trap is performed.

If the means for examining the cause of the trap determines that the cause of the trap is a page fault (step S16), the fetch processing and the decoding processing are invalidated in the same manner as in the branch prediction mistrap. (Step S20), the register value is restored according to the contents of the register saving unit 16 (Step S21), and the group value generating unit 6 is reset. Also, page processing for loading the virtual address area onto the memory 1 is performed at the same time. Upon completion of the page fault trap, the address generation unit 28 is set to indicate the instruction address of the load / store instruction that has been subjected to the page fault trap.

Now, how the units operate when instructions are speculatively executed in the processor of the present embodiment, and the configuration or function of some units will be described in more detail. .

In the following description, the processing performed in each pipeline stage is defined as follows. • Fetch stage (F stage): Fetch an instruction from memory • Decode stage (D stage): Decode the fetched instruction • Execution stage (E stage): Perform an operation using an instruction execution unit, and execute the operation based on the result of the operation. A trap is generated if necessary.-Memory stage (M stage): Determines page faults, reads data from memory, and writes data to memory.-Write-back stage (W stage): Outputs operation results. In the following, “instruction i” represents the instruction of the instruction number i.

FIG. 3 shows an example of a program executed by the present processor. In FIG. 3, instructions 1 and 3 are load / store instructions, and instruction 5 is a conditional branch instruction.

Hereinafter, the case where the program shown in FIG. 3 is to be executed will be described along the flow of the cycle as an example. For the sake of simplicity, it is assumed that there are no instructions being processed in the pipeline at the start of the program in FIG.

First, in cycle 1, the instruction fetch unit 2 fetches instructions 1 to 4 in order at the F stage and inserts them into the instruction queue 3. Although the present invention is applicable to any number of processors having the same number of simultaneous fetches and enables speculative execution of instructions, the number of simultaneous fetches is set to 4 in this embodiment.

Next, in cycle 2, at the F stage, the instruction fetch unit 2 first selects the conditional branch instruction "beq
r4, r3, and instruction 7 (the address thereof) "are fetched.
At this time, the branch destination of the conditional branch instruction 5 is predicted (in this case, either instruction 6 or instruction 7).
In this example, assuming that the branch prediction destination is instruction 7, instructions 7, 8 and the next instruction (not shown) are fetched subsequently. The branch prediction destination (in this case, instruction 7) is conditional branch instruction 5
Is saved until the execution is completed.

On the other hand, in the D stage in cycle 2, the instruction decoding unit 4 decodes the instructions 1 to 4 in the instruction queue 3 and obtains the instruction type and the operand to be used. Also,
Each instruction obtains a group value from the group value generator 6 in order. Thereafter, they are inserted into the decode instruction queue 7 in the order of instructions. If there is no free space in the decode instruction queue 7, instruction decoding is stopped.

As described above, the group value generating unit 6
Starting with a load / store instruction or conditional branch instruction,
A common group value is assigned to each instruction in the instruction group ending with the instruction immediately before the next load / store instruction or conditional branch instruction. Instruction groups that are being executed simultaneously are assigned different group values.

Here, FIG. 4 shows an example of realizing the group value generating section 6 (the program example shown in FIG. 4 is different from that of FIG. 3).

As one implementation of the group value generation unit 6, an implementation using a bit vector indicating which group value is in use or not can be considered.

When assigning a group value to a load / store instruction or a conditional branch instruction, a predetermined selection is made from group values in which the corresponding bit (bit indicating whether or not it is in use) is 0. One is selected according to the procedure (e.g., the one with the largest value) and the selected group value is assigned. At this time, the bit corresponding to the group value is changed to 1 and the value of the buffer provided in the group value generation unit 6 is updated to this group value. On the other hand, when assigning a group value to another type of instruction, a value set in the buffer at that time is assigned.

When execution of all instructions having a certain group value is completed, the bit corresponding to the group value is set to 0. When all the bits of the above bit vector are 1,
The instruction decoding unit 4 stops decoding the instruction until an unused group value is generated.

The flag corresponding to the group value shown in FIG. 4, which indicates whether or not the program is being executed, is related to the speculativeness judging section 12 described later.

FIG. 5 shows another example of realizing the group value generator 6 (note that the example of the program shown in FIG. 5 is different from that of FIG. 3).

As another implementation of the group value generation unit 6,
Implementation using a hardware counter is also conceivable.

When adding a group value to a load / store instruction or a conditional branch instruction, the value of the group value counter is increased by one in advance. On the other hand, when adding a group value to another type of instruction, the value of the group value counter is not changed. Then, the value of the group counter is added to the instruction as a group value. When the value of the group counter indicates the maximum value, the counter value is set to 1
Instead of increasing the value, the value is set to 0, and 0 is set as a group value.

In the hardware counter method, the group value generator 6 has an execution instruction counter in order to guarantee that the group value of the instruction being executed does not overlap with the newly assigned group value. The execution instruction counter has the same value as the group value counter in the initial state, and increases by one when the execution of the load / store instruction or the conditional branch instruction is completed. 0 if the execution instruction counter is at the maximum value
And The instruction decoding unit 4 controls so that instructions subsequent to the instruction group whose value to be added is equal to the execution instruction counter are not transferred to the corresponding execution unit.

The initial state of the group value generator 6 is such that all bits are 0 in the bit vector system as shown in FIG.
In the hardware counter method as shown in FIG. 5, both the group value counter and the execution instruction counter are 0. When a branch prediction mistrap or a page fault trap occurs, the state of the group value generation unit 6 returns to the initial state after the completion of the trap processing.

Next, in cycle 3, the operand state determination unit 5 determines whether or not operands are available in order from the first instruction in the decode instruction queue 7, and if available, an instruction is issued to an execution unit that is not being used. To transfer. In this example, first, the instruction “lwr” of the instruction number 1
3, playlevel "is determined to be available, and the instruction 1 is sent to the load / store unit 10. Next, it is determined that the register r12 of the instruction" li r12, 2 "of instruction number 2 is available. , The instruction 2 is sent to the instruction execution unit 8. Next, the instruction "s" of the instruction number 3 is sent.
The instruction transfer ends here because the register r12 cannot be used for “wr12, quicklibs”. In this case, even if the register r12 is available, the instruction 1 uses the load / store unit 10. Therefore, the instruction 3 cannot be executed because of the transfer of the instruction (here, the instruction 1 and the instruction 2).
The execution is started on each execution unit at the stage.

As described above, the operand state determination unit 5 checks whether or not there is an instruction to be written in the designated register in the instruction being executed. If the instruction does not exist, the register can be used or the register can be used. Is a means for determining that the service is unavailable. This means can be realized by, for example, a register scoreboard method as in a conventional in-order superscalar processor. The register scoreboard method has a scoreboard that indicates whether or not each register can be used.When an instruction is sent to an execution unit, the scoreboard of the register written by that instruction is used, and the execution of the instruction is completed. At this point, the scoreboard of the register is made usable.

On the other hand, in the D stage in cycle 3, the instruction decoding unit 4 decodes the instruction 5, the instruction 7, the instruction 8, and the next instruction (not shown) and inserts them into the decoded instruction queue 7. In the F stage, the instruction fetch unit 2 fetches an instruction (not shown) after the instruction fetched in the previous cycle. Also in the subsequent cycles, the instruction fetch unit 2 fetches instructions as long as there is a vacancy in the instruction queue 3 at the F stage, and the instruction decode unit 4 decodes the instructions as long as there is a vacancy in the decoded instruction queue 7 at the D stage.

Subsequently, it is assumed that the operation of the instruction "li" of the instruction number 2 is completed in the cycle 5, and the instruction "lw" of the instruction number 1 is still being executed. The speculativeness judging unit 12 outputs the instruction 2
Is determined to be speculative. In this example, execution of the instruction 2 is determined to be speculative because it is not determined whether the instruction 1 causes a page fault trap.

The speculativeness judging section 12 includes the group value generating section 6
Is realized by the bit vector method, as shown in FIG.
It has a bit vector indicating whether an instruction corresponding to a store instruction or a conditional branch instruction is being executed or has been completed.
In this case, at the start of execution of a load / store instruction or conditional branch instruction having a certain group value, a bit corresponding to the group value is set to 1, and to 0 when the execution of the instruction is completed. The speculativeness determining unit 12 determines that the instruction is speculative when the bit corresponding to the group value of the instruction to be determined is 1, and determines that the instruction is non-speculative when the bit is 0.

On the other hand, when the group value generator 6 is realized by a hardware counter method, the speculativeness determiner 12 does not need to include a bit vector. In this case, it is determined from FIG. 6 whether or not it is speculative from the value x of the group value counter provided in the operand state determination unit 5, the value y of the execution instruction counter, and the group value z of the instruction to be determined. Can be.

Now, after the determination of the speculative property, the cycle 5
First, the processor state control unit 30 executes the instruction “l
It is determined whether or not the state of the processor may be updated according to ir12,2 ". In this example, since the register r12 updated by the instruction 2 is a general-purpose register, the update of the state is permitted. If the update is permitted, the instruction 2 is speculative here, and therefore, first, the register number “12” and the register r12 (before the update)
The value and the group value “1” of the instruction 2 are stored in the register save unit 1
6 is registered. Then, in the W stage of cycle 5, the value of the register r12 is updated to the operation result of the instruction 2.

As described above, the processor state control unit 30 guarantees that the execution completion order of the load / store instruction and the conditional branch instruction does not change. The processor state control unit 30 permits the state update based on the condition illustrated in FIG. 7 from the type of the instruction and the speculativeness of the instruction. For example, the instruction “lir12, 2” of the instruction number 2 corresponds to the other instruction in FIG. 7 and the update is permitted even if it is speculative.

In FIG. 7, other typical instructions are instructions for changing general-purpose registers, and typical instructions for changing control registers are instructions for changing multiplication / division registers. However, the conditions in FIG. 7 are merely examples, and may be appropriately set according to the specifications of the processor and the instruction set. Basically, in the case of non-speculative, it is "permitted" for all instruction types, and in the case of speculative, at least instructions corresponding to load / store instructions or conditional branch instructions are "disallowed". . In the case of an instruction other than a load / store instruction and a conditional branch instruction in a speculative case, for example, an "instruction to write in a special register not explicitly specified as an output destination" or an "instruction to change a certain register" Instructions that cause an action to occur at the time of execution when the register is changed ”are“ disabled ”and“ instructions to write to general purpose registers specified as output destinations ”or“ instructions to change a certain register. An instruction in which no action occurs at the time of execution even if the register is changed and an action occurs later as a result of determination by another instruction is "permitted". For example, if the instruction to change the condition register is speculative, it becomes "permitted" in one processor and "disabled" in another processor.
It is possible that

The register saving section 16 is a queue for holding information necessary for returning the processor to a state before the execution of the speculative instruction when the speculative instruction is an error.

Note that a plurality of sets of information about the same register may be registered in the register saving unit 16. In the example of FIG. 8 (the program example shown in FIG. 8 is different from that of FIG. 3), the instruction “add” of (2)
r2, r3, r4 "and the instruction" li r2,1
00 ”was executed speculatively, so that the register
In the register r2 are registered.

Registration and deletion of information in the register saving section 16 and restoration of a register value based on information are performed according to the following rules. When a speculative instruction (in FIG. 7, other instructions) updates the processor state, the identification information of the register to be changed by the instruction, the value before the change of the register, and the group value of the instruction are Registered ・ When a load / store instruction or conditional branch instruction having the same group value as the registered information is completed without causing a trap, the information is deleted. ・ Branch prediction mistrap or page When a fault trap occurs, the values of all the registered registers are returned to the registered values in order from the most recently registered one, and the information is deleted. In the example of FIG. 8, the instruction “1w” of (1) is When a page fault occurs, the register r2 is returned to 15832, and the instruction “beq” of (4) is replaced with the instruction (5) (not shown).
When a branch prediction error occurs, the register r2 is returned to 45.

Subsequently, in cycle 10, when the execution of the instruction “lw” of the instruction number 1 in FIG. 3 is completed without causing a trap, the instruction 1
The information having the same group value 1 as that of the register r12, that is, the information on the register r12 saved in the register saving unit 16 in the previous cycle 5 is deleted. At this point, since the load / store unit 10 becomes usable, the instruction “s
w "in order from the operand state determination unit 5,
Transferred to each execution unit. Instruction "s" of instruction number 3
w "to the load store unit 10, the instruction" addiu "of instruction number 4 to the instruction execution unit 8, and the instruction number 5
The instruction “beq” is transferred to the branch instruction execution unit 11, and the instruction “move” of the instruction number 7 is transferred to the instruction execution unit 9, and the instruction is executed in the E stage.

Next, it is assumed that the operations of the instructions 4 and 7 are completed in the cycle 11, and the instructions 3 and 5 are still being executed. The instructions 4 and 7 are determined to be speculative by the speculativeness determining units 12 and 13, respectively, and the processor state control unit 30 permits the state update. Thereafter, information on the register r13 changed by the instruction 4 and information on the register r6 changed by the instruction 7 are registered in the register saving unit 16,
The values of these registers are updated in the W stage.

Next, in cycle 12, the operation of the instruction “beq” of the instruction number 5 is completed, and the instruction “sw” of the instruction number 3 is completed.
Is still running. The instruction 5 is not completed because the state update is not permitted by the processor state control unit 30.
Wait for the completion of the instruction 3 while occupying the load / store unit 10.

Subsequently, in cycle 15, when execution of instruction 3 is completed without generating a page fault trap,
Information on the register r13 of the register saving unit 16 (information having the same group value 2 as the instruction 3) is deleted.

Then, in cycle 16, the instruction 5 is permitted to be updated in state by the processor state control unit 30.
Upon completion of the execution, information on the register r6 of the register saving unit 16 (information having the same group value 3 as the instruction 5) is deleted.

On the other hand, in the program flow of FIG. 3 described above, the instruction “beqr4, r3, instruction 7
(Address of) causes a branch prediction mistrap, and the instruction “swr12, quick
klibs "generates a page fault trap as follows.

If it is found that the predicted branch destination is different from the actual branch destination at the end of the operation of the instruction 5 in the cycle 12 (in this example, the predicted branch destination is the instruction 7 and the actual branch destination is Is instruction 6), a branch prediction mistrap is applied when the instruction is completed. When the branch prediction mistrap occurs, the contents of the instruction queue 3 and the decoded instruction queue 7 are all erased. In this example, the instruction 8 is one of the instructions to be deleted from the decode instruction queue 7. After that, the register registered in the register saving unit 16 is returned to the saved value. In this example, when the instruction 5 is completed, the instruction 3 is completed, and the information on the register r13 has been deleted from the register saving unit 16;
Only the value of is changed. After that, the address indicated by the address generation unit 28 is set as the instruction address of the instruction 6, and the trap processing ends.

In cycle 14, instruction 3 at M stage
If it is found that the virtual address to be stored does not correspond to the real memory area when executing, a page fault trap is set when the instruction is completed. The operation at the time of the trap is the same as the operation of the branch prediction mistrap. In this example, when the instruction 3 causes a page fault trap, the registers r13 and r6 are registered in the register saving unit 16, so that the values of these registers are changed. Thereafter, the address indicated by the address generation unit 28 is set as the instruction address of the instruction 3, and the trap processing is completed.

By the way, the condition that the determination of a page fault by a load / store instruction and the determination of a branch misprediction by a conditional branch instruction are performed before completion of another instruction having the same group value as these instructions is satisfied. Then, the speculativeness judging units 12 to 15 and the register saving unit 1
6 can be omitted. In this case, if the executed instruction is not canceled by the trap, it is not speculative. In a processor in which the number of instructions transferred to the execution unit is at most 1 as shown in FIG. 1, satisfying this condition by making the time for completing the trap determination equal to the time for completing the operation of each execution unit. Can be. On the other hand, as shown in FIG. 9, each execution unit 308 has a queue 309 between itself and the instruction decoding unit 307, and the decoded instruction is put in the queue when the execution unit is unavailable, and the execution unit is placed in the queue. Since the time from the transfer of the instruction to the completion of the execution is not uniquely determined in the configuration in which the instructions are sequentially executed from the head of the instruction, it is necessary to provide the speculativeness determination units 12 to 15 and the register saving unit 16.

(Second Embodiment) The speculative instruction execution mechanism according to the present invention is not limited to executing instructions out-of-order beyond load / store instructions and conditional branch instructions. In the following, the present invention is referred to as Predic
An embodiment in which the present invention is applied to a program code including an instruction with an a.

The instruction execution mechanism with Predicate is:
This is a mechanism that implements a conditional branch in a different form from a conditional branch instruction. In this mechanism, Predic added to each instruction
The value of a Boolean variable called "ate" controls whether the result of the operation is reflected in the register.

FIG. 10 shows an example of a program code which does not include the instruction with Predicate, and FIG.
4 shows an example of a program code including an instruction with a digit. The program code in FIG. 11 shows the same contents as the program code in FIG. 10 using Predicate.

The Pseq instruction (Pred) shown in (1) of FIG.
In the present example, if the condition is satisfied, and in this example, the value of the register r3 is equal to the value of the register r4, 1 is set to p1 as the Predicate value and 0 is set to p2 as the Predicate value. On the other hand, when the condition is not satisfied, in this example, when the value of the register r3 is not equal to the value of the register r4, p1 is set to 0, p2
Is set to 1. Also, as shown in (2) to (4) of FIG. 11, a Predic such as <p1> or <p2> is used.
For the instruction with ate, the variable in <> is Ps
Only when set to 1 by the eq instruction, the result of that instruction is reflected in the register. On the other hand, as for the instruction without Predicate as in (5), the result of the instruction is always reflected in the register.

Therefore, in the program code of FIG. 11, when the value of the register r3 is equal to the value of the register r4, 1 is set to p1 and 0 is set to p2 by the Pseq instruction. At this time, the instruction with <p1> is added. "Sll r
6, r10,2 "," lir5,1 "and Predic
Since only the result of the instruction “move r2, r5” without “ate” is reflected in the register, FIG.
The same result as in the case of branching to L2 at 0 is obtained. Similarly, when the value of the register r3 is not equal to the value of the register r4, p1 is set to 0 and p2 is set to 1. At this time, the instruction "li r5,0" with <p2> and the Pred
Instruction "move r2, r without icate"
Since only the result of 5 ″ is reflected in the register, the result is the same as the case where the process did not branch to L2 in FIG.

In the conventional instruction execution mechanism with Predicate, an instruction with Predicate is assigned to its Pr.
Not executed until edit is confirmed. Therefore,
Pre after the instruction to set Predicate
Instructions with dict cannot be executed speculatively. According to the present invention, speculative execution of such an instruction with Predicate becomes possible. Hereinafter, a speculative execution method of an instruction with Predicate to which the present invention is applied will be described.

Note that the configuration and operation of the processor according to the present embodiment are basically the same as those of the first embodiment except for the part relating to the instruction with Predicate. Therefore, the following description is different from the first embodiment. This will be mainly described.

In this embodiment, a Predicate set instruction as shown in FIG. 11A is handled in the same manner as the load / store instruction and the conditional branch instruction in the first embodiment. That is, in this embodiment, in the instruction sequence to be executed by the processor, the instruction sequence starts with an instruction corresponding to a conditional branch instruction, a load / store instruction, or a Predicate set instruction, and corresponds to a conditional branch instruction, a load / store instruction, or a Predicate set instruction. The part ending with the instruction immediately before the next instruction is referred to as an “instruction group”. Similarly, the processor state control unit 30
Conditional branch instruction or load / store instruction or Pred
Instructions corresponding to the icate set instruction are controlled so that their completion order is not changed. For example, in FIG. 7, the Predicate set instruction is the same as the load / store instruction and the conditional branch instruction.

In order to identify which instruction group each instruction belongs to in the processor, each instruction has a “group value” unique to the instruction group to which it belongs.
Is the same as in the first embodiment.

The operand state judging section 5 includes the Predic added to the instruction as shown in (2) to (4) of FIG.
Regarding ate, the state is not determined, and if another operand is available, it can be used. However, Predi
For instructions such as changing the Predicate, such as a cat set instruction, and instructions for performing an operation with the Predicate as an input, the Predica is used.
It is determined whether te is available. Also, even when the execution of the instruction with Predicate is completed, the operand state determination unit 5 does not make the register written by the instruction available until the Predicate of the instruction is determined. This is because when the operand state determination unit 5 is configured by the register scoreboard method, Predicate
This can be realized by keeping the scoreboard in use when speculative execution of the attached instruction is completed, and making the scoreboard available at the time of Predicate set trap described later.

The Predicate set trap is a trap that is set when a Predicate set instruction is completed in this method. If the trap determining unit determines that the trap is caused by the Predicate set, the pipeline is not deleted. Then, the information registered in the register evacuation unit 16 is checked in order from the most recently registered information, and the process at the time of the Predictate set trap is performed based on the information.

FIG. 12 shows an example of a processing procedure at the time of Predicate set trap. Note that tg in FIG. 12 is the group value of the instruction that caused the trap. In this process, the register speculatively updated by the instruction for setting the Predicate value to 0 is returned to the value before the update.

In FIG. 12, first, the register save unit 1
6 is obtained (step S3).
1). If n> 0 (step S32), the group value g of the information registered last in the register saving unit 16 is obtained (step S33). If g = tg (step S3
4), p of information registered last in the register saving unit 16
A redactate value p is obtained (step S35).

When p = 0 (step S36), if the corresponding register is not usable (step S37),
The register is returned to the original value based on the registered information (step S38), the register is made usable, and the information registered last in the register saving unit 16 is deleted (step S39).

In cases other than the above, that is, when p = 0 is not satisfied, or when p = 0 and the corresponding register is available, the register is used without returning to the original value. Then, the information registered last in the register saving unit 16 is deleted (step S39).

The above processing is repeatedly executed until the processing exits the loop because n> 0 in step S32 or g = tg in step S34.

As shown in FIG. 13, the register saving section 16 stores a Predictate number (information for identifying P1 and P2) in addition to a register number, an original value of the register, and a field for an instruction group value. have.

When an instruction with Predicate is speculatively executed, the register updated by the instruction, its original value, the group value of the instruction, and the number of the Predicate added to the instruction are stored in the register save unit 16.
Registered in.

For instructions to which Predicate is not added, Predica having a value of 1 is always used.
Similar processing is performed assuming that the te variable has been added. For example, p31 is a Predic whose value is always 1.
If it is assumed that the instruction is a predicate number, 31 is registered as a Predicate number during speculative execution of an instruction without Predicate.

The other units included in the processor of this embodiment are the same as those of the first embodiment.
A rule or processing method applied to a store instruction or a conditional branch instruction as it is also applied to a Predicate set instruction can be used as a processor unit of the present embodiment.

The operation of the present embodiment when the program code illustrated in FIG. 11 is executed speculatively will be described. For simplicity, it is assumed that there are no instructions being processed in the pipeline at the beginning of this code.

First, in cycle 1, instructions (1) to (4)
Is fetched at the F stage.

Next, in cycle 2, instructions (1) to (4)
Are decoded in the D stage, and at the same time, four instructions are fetched from the instruction (5) in the F stage. The decoded instructions (1) to (4) have the same group value. Hereinafter, operations related to fetch and decode are omitted.

Next, in cycle 3, the instruction (1), that is, the Predicate set instruction is sent to the instruction execution unit 8
Then, the instruction (2) is transferred to the instruction execution unit 9, and the execution of the instruction is started in the E stage.

Subsequently, in cycle 5, it is assumed that the execution of the instruction (2) is completed and the instruction (1) is still being executed. The instruction (2) is determined to be speculative by the speculativeness judging unit 12, and the register number “5”, the register r
The pre-update value, group value, and Predicate number “2” of 5 are registered. Then, at the W stage, the register r
The value of 5 is updated.

Subsequently, at the time of cycle 9, instructions (3),
It is assumed that the execution of (4) has been completed and the instruction (1) is still being executed. The instruction (3) is determined to be speculative by the speculativeness determining unit 12, and the register saving unit 16 stores the register number “6”, the value of the register r6 before updating, the group value, and Pr.
The edit number "1" is registered. Similarly, the instruction (4) is determined to be speculative by the speculativeness judging unit 12 and the register number “5”, the register r
5, the pre-update value, the group value, and the Predicate number “1” are registered. Then, at the W stage, the register r
5 and the value of the register r6 are updated. At this time, the information in FIG. 13 is registered in the register saving unit 16.

Next, in cycle 10, when the execution of the instruction (1), that is, the Predicate set instruction is completed,
A Predictate set trap occurs.

[0139] By the Predicate set instruction, p
When 1 is set to 1 and p2 is set to 0, first, the information of the registration order 3 in FIG. 13 is checked according to the procedure of FIG.
Since P1 = 1, the register r5 is enabled without changing the register r5 (without returning to the original value), and the information of the registration order 3 is deleted. Next, the information of the registration order 2 is examined, and since P1 = 1, the register r6 is not changed, and
The register r6 is made usable, and the information of the registration order 2 is deleted. Finally, the information of the registration order 1 is examined, and although P2 = 0, the register r5 is in a usable state, so that the information of the registration order 1 is deleted without doing anything.

On the other hand, when p1 is set to 0 and p2 is set to 1 by the Predicate set instruction, first, the information of the registration order 3 is checked. Since P1 = 0 and the register r5 is not usable, the register r5 The value is returned to 0, which is the value before the update, the register r5 is made usable, and the information of the registration order 3 is deleted. Next, the information of the registration order 2 is examined. Since P1 = 0 and the register r6 is not usable,
The value of the register r6 is restored, the register r6 is made usable, and the information of the registration order 2 is deleted. Finally, registration order 1
Is checked, and P2 = 1, and the register r5 is in a usable state.
Delete information for.

In a processor in which the number of instructions transferred to the execution unit is at most 1 as shown in FIG.
The number of cycles required from issuance to completion of the edit set instruction (this is uniquely determined) is Predicat
When the processing time is longer than the e-set trap processing time, the effect of speculative execution of a larger instruction with Predicate is obtained. If the number of cycles required from issuance to completion of a Predicate set instruction is not constant, as in the configuration in which the execution unit includes a queue in FIG.
It is also conceivable to perform speculative execution only when it is more efficient to speculatively execute an instruction with edit. To determine the execution efficiency, for example, a method of examining the number of instructions in the queue of the execution unit to which the Predicate set instruction is issued at the time of issuing the Predicate set instruction and performing speculative execution when there is a certain number or more of instructions is considered.

(Third Embodiment) In the first and second embodiments, the method of saving the original value of the register to be speculatively rewritten and restoring the value at the time of trapping has been described.

In the present embodiment, the compiler performs register allocation and code generation so that the register value does not need to be restored even when the register is erroneously changed by speculative execution. A method of performing speculative execution of an instruction without performing speculative judgment of each instruction and saving / restoring a register as in the second embodiment will be described.

The structure and operation of the processor according to the present embodiment are the same as those of the processor shown in FIG.
2, the point that the processing (registration and restoration of information, etc.) relating to the register saving unit 16 is omitted from the procedure of FIG. 2, and that the speculativeness determining units 12 to 15 determine the speculativeness only for a SYNC instruction described later. Other than the above, it is basically the same as the first embodiment. The instruction group, group value, operand state determination, processor state control, and the like are the same as in the first embodiment.

When an instruction executed speculatively changes a register by mistake, it is necessary to return the register to the original value because the instruction is executed using an incorrect register value after trapping. This is to prevent the processor from transitioning to an incorrect state.

Such a malfunction occurs in the following two cases.
Only when one of the types of instructions is speculatively executed and erroneously updates a register. FIG. 14 shows the state of the following (2). (1) An instruction whose output operand matches one of the input operands of an instruction (including itself) for which speculative execution was erroneous (2) A conditional branch instruction in which an instruction output operand branches to a path leading to the instruction An instruction whose value is used without being updated in the other path of FIG. 15. Here, an instruction corresponding to the above (1) and (2)
An example of a program code including an instruction corresponding to (1) is shown.

In FIG. 15, the instruction “move” of instruction number 4
r6, r3 ”corresponds to the instruction of (1). Before the completion of the instruction“ lw r4, in (r0) ”of the instruction number 2, the instruction“ addu r4, r4, r6 ”of the instruction number 3 is completed.
When the instruction “mover6, r3” of instruction number 4 is speculatively executed, the registers r4 and r6 are updated. When the instruction 2 causes a page fault trap, the register r4 is substituted when the instruction 2 is re-executed, but the register r6 remains at an erroneous value, so that when the instruction 3 is re-executed, a transition to an erroneous state occurs. .

On the other hand, the instruction “li” of the instruction number 6 in FIG.
r6, 20 "corresponds to the instruction of the above (2). It is predicted that the instruction" beq r2, r3, instruction 6 "will branch to the instruction 6 before completion, and the instruction 6 is speculatively executed. When the result is written to the register r6, when the instruction 1 causes the branch prediction mistrap, the value of the register r6 of the instruction “addu r4, r4, r6” of the instruction number 3 is changed when the execution is resumed from the instruction 2. Transitions to the wrong state.

On the other hand, if the code does not include an instruction that satisfies the above condition (1) or (2), the register that has been erroneously speculatively updated is not restored to the original value. Therefore, it is possible to guarantee that the processor does not transition to an erroneous state in the execution after the trap.

A register allocation method and a code generation method by a compiler which enable speculative determination of each instruction and speculative execution without register save / restore as in the first embodiment will be described below.

In this method, the instruction set includes a special instruction called a "sync instruction". In the processor configuration based on FIG. 1, the sync instruction is executed by the instruction execution units 8 and 9. When a sync instruction is sent to an execution unit, instruction transfer to all execution units is stopped until the sync instruction is completed.

The sync instruction operates in the execution unit as follows. If the sync instruction is executed non-speculatively, nothing is done. If the sync instruction is executed speculatively, load / store having the same group value as the group value assigned to the sync instruction. The sync instruction is not completed until the execution of the instruction or the conditional branch instruction is completed.

The compiler according to this embodiment has a basic configuration similar to that of a conventional compiler.
In the process of register allocation, a sync instruction is issued so as to guarantee that no malfunction occurs in execution after a trap in the present processor (that is, a sync instruction that satisfies the above condition (1) or (2)). Register allocation and code generation such that there are no instructions). In addition, regarding the register allocation method,
An arbitrary register allocation method can be applied to a part for obtaining a register live range (eg, Andrew W.A.).
ppel, "Modern Compiler Imp
elementation in C ", Cambridge
Ge University Press, 199
8).

The following describes the register allocation based on this method.

FIG. 16 shows an example of a procedure of register allocation and code generation for a basic block by the compiler according to the present embodiment.

A series of instructions starting from an instruction start portion or a branch destination of a conditional branch or an unconditional branch, and ending immediately before a conditional branch or an unconditional branch, and immediately before a branch destination of a conditional branch or an unconditional branch are described as follows. It is called a basic block.

First, it is assumed that a program code including a symbol register has been generated based on a source program or the like described in a high-level language.

By the way, in the initial state of this processing, all the registers (r1,...) Can be used. Register allocation starts from the basic block at the beginning of the program code.

First, the following processing is performed on all the symbol registers (# 1,...) Existing in the basic block in the order of instructions until the registers become insufficient. -Select and assign one available register.-Disable that register. Steps S41, S42, S43, S43 in FIG.
44, S45, S46, and S52.

If the symbol register being assigned exists in another basic block to which assignment has already been completed, the assigned register is assigned to the block to which assignment has been completed (steps S43, S50, S51). Also, for a symbol register whose assignment register is fixed, such as a stack pointer, the fixed register is assigned (step S43,
S50, S51). At this time, when the assigned register is not included in the usable register set (step S5).
0) contains s immediately before the instruction to be output to this symbol register.
A nc instruction is inserted, and all registers that are not alive at this time are made available (step S47).

If there are not enough registers (step S46), a sync instruction is inserted after the last register allocation instruction, and all registers that are not alive at this time can be used (step S46). S47).

If there is no newly available register, the inserted SYNC instruction is deleted and spill processing is performed (processing for changing a part of the instruction so as not to use the register).
(Steps S48 and S49), the flow returns to step S43 to resume register allocation.

When the register allocation is completed, if the basic block forms a loop, and if the register is the last basic block to be allocated in the loop,
Insert a SYNC instruction after the last instruction (step S
53).

When the allocation of all the basic registers to the symbol registers is completed by the above processing, one basic block satisfying the following condition is selected from the other basic blocks to which no register allocation has been performed, and further register allocation is performed. Perform All the basic blocks flowing into the basic block are either “register allocation is completed” or “constitute a part of a loop with the basic block”. In the example of FIG. 17, the basic block D is 3 Is a block into which two basic blocks A, B, and C flow, and the basic block A
Satisfies the condition that “register allocation is completed”, the basic block C satisfies the condition that “is part of a loop together with the basic block D”, but block B is unregistered and Since a part of the loop is not formed together with the basic block D and none of the conditions is satisfied, the basic block D cannot be selected. However, in FIG. 17, when the basic block B is selected and its register allocation is completed, the basic blocks A and B satisfy the former condition and the block C satisfies the latter condition. Is selected.

Here, at the head of a newly selected basic block to which no register is allocated, a set of usable registers is represented by the following equation.

[0166]

(Equation 1)

In the above formula, I₁... I_nThis new
Flow into the selected basic block and register allocation
A set of basic blocks for which allocation has been completed.₁
... B _mIs I₁... I_nSet of basic blocks flowing out of
It is.

[0168] For example, in the case of FIG. 18, when the basic block allocation target B3, a basic block does not form part of a loop with I ₁ ... I ₃ is and basic block flow into the basic block B3 B3, B ₁ ... B ₃ is I ₁
... is a set of basic block flow out from the I _n. Also,
basic blocks shown in i1, since at the time the register allocation of basic blocks B3 have not yet been made register allocation, not included in the I ₁ ... I _n.

In the above equation, free represents a register that can be used at the time of completion of register allocation of the basic block, and dead represents a set of registers that do not exist at the head of the basic block.

The above processing is repeated, and when the register allocation for all basic blocks is completed, the processing is terminated.

In the following, description will be given of the operation when register allocation and code generation are performed based on the present method for the program code described in the symbol register of FIG.

FIG. 20 shows the relationship between the basic blocks existing in the code of FIG.

In this example, the registers are r1 to r8. The register allocation starts from the basic block of the instruction 1, and the registers r1, r
5, r7, and r8 are usable and do not survive.

First, the register r1 is assigned to the symbol register # 1 of the instruction 1, and the register r1 is disabled. Similarly, r5 is allocated to $ 5 of instruction 2, and r7 is allocated to $ 7 of instruction 3, and the allocation of the first basic block is completed. The available register set at the end of the basic block allocation is r8.

Next, the register of the basic block of instructions 5 and 6
Data allocation is performed. Basic block of instructions 1-4
I₁, Basic block B of instructions 5 and 6₁, Instruction 7
Lock B _TwoFor free (I₁) = R8, dead
(B₁) = R4 to r8, dead (B_Two) = R3 to r6
And r8, so at the beginning of this basic block
The only register that can be allocated is r8. Accordingly
Then, the register r8 is allocated to $ 8. As a result, the assignment
No registers are available on exit.

Next, register allocation of the basic block of the instruction 7 is performed. As with the basic blocks of the instructions 5 and 6, the only register that can be allocated at the beginning of the basic block of the instruction 7 is r8. Therefore, register r
Assign 8 to $ 9. As a result, no registers are available at the end of the assignment.

Finally, the register of the basic block of the instruction 8 is allocated. Basic block I _{3 of} instructions 5 and 6, instruction 7
Free (I ₃ ) = free for the basic block I ₄ of
Since e (I ₄ ) = φ, there is no register available at the beginning of this basic block. Therefore, a sync instruction is inserted before the instruction “add $ 11, $ 1, r2” of the instruction number 8 (as a result, the sync instruction becomes the instruction number 8, “ad
d "becomes the instruction number 9), which makes all the registers usable. Therefore, r1 is assigned to $ 11.

Thus, the code after register assignment and code insertion in FIG. 19 are as shown in FIG.

Next, the operation when the code of FIG. 21 is executed by the processor of this embodiment will be described.

First, the instructions 1 and 2 correspond to the instruction execution units 8 and
9 and their results are written to registers r1 and r5.

Assuming that the branch prediction destination of the instruction 4 is the instruction 7, the instructions 3, 4 and 7 are respectively executed by the instruction execution unit 8, the branch instruction execution unit 11, and the instruction execution unit 9
Executed in

If instructions 3 and 7 complete before instruction 4 completes, instruction 8, a sync instruction, is transferred to the execution unit. Since the sync instruction is determined to be speculative by the speculativeness determination unit, the transfer of the instruction 9 to the execution unit is stopped until the conditional branch instruction 4 having the same group value as the sync instruction is completed.

Assuming that a branch prediction mistrap occurs upon completion of instruction 4, code execution is resumed from instruction 5 after the trap. Here, since the instruction 5 uses the register r1, if the instruction 9 speculatively updates r1 before the completion of the instruction 4, a malfunction occurs. Thus, the sync of instruction 8
The instruction guarantees that instruction 9 is not executed speculatively.

On the other hand, even if the branch prediction mistrap occurs by predicting that the instruction 4 branches to the instruction 5, if the instruction 9 speculatively updates r1, a malfunction occurs when the instruction 9 is re-executed. The sync instruction guarantees that instruction 9 will not be executed speculatively.

(Fourth Embodiment) The first to third embodiments are embodiments in which instructions are speculatively executed by an in-order instruction issuing superscalar processor.
This embodiment is an embodiment in which an in-order instruction issuing VLIW processor executes instructions speculatively.

The flow of the pipeline in the processor of this embodiment is basically the same as that of the first embodiment. However, in this embodiment, the group value is included in the code of the VLIW instruction. Is obtained from That is, in the present embodiment, the group value is generated by the compiler. The definition of the instruction group and the group value is the same as in the first embodiment.

FIG. 22 is a block diagram showing a configuration example of a processor according to the present embodiment.

As shown in FIG. 22, the processor of this embodiment comprises a memory 101, an address generation unit 103, an instruction fetch unit 102, an instruction decode unit 104, an operand state determination unit 105, and instruction execution units 108 to 11.
0, branch history storage unit 115, speculative judgment units 111 to 11
3. It has a register saving unit 114 and a register 116.

The main difference from the configuration example of FIG. 1 is that a group value generation unit is not provided and a branch history storage unit 115 is provided.

In the following, the "VLIW instruction" and the V
In order to distinguish from each "instruction" constituting the LIW instruction, each of the instructions constituting the latter one VLIW instruction may also be referred to as "atom".

In this embodiment, there is shown an example in which the number of instruction execution units is three, that is, one VLIW instruction is composed of three atoms. However, when the number of instruction execution units is two or four or more, , Ie one VLI
The present invention is also applicable when the W instruction is composed of two or more atoms.

Further, the flow of the pipeline in the processor of the present embodiment is basically the same as that of FIG. 2 of the first embodiment.

In the following, description will be made focusing on the points in which the present embodiment is different from the first embodiment.

First, the flow of the pipeline processing in the processor of this embodiment will be described.

The instruction fetch unit 102 specifies the VLIW instruction address indicated by the address generation unit 103 on the address bus 119, and fetches a VLIW instruction composed of three atoms from the memory 101 via the instruction fetch bus 117 (step S11). ).

The instruction decode unit 104
Decodes the LIW instruction via the decode bus 120,
For each atom, the type, the operand to be used, the group value, and information on whether or not the atom is speculative are obtained (step S12).

In the decoded VLIW instruction, it is determined by the operand state determining unit 105 whether the operand used by each atom is usable (step S14).
Thereafter, if all operands are available, each atom is transferred to the corresponding instruction execution unit 108-110 via the instruction bus 124-126, respectively. At this time, the group value and information on whether it is speculative or not are also transferred. Thereafter, the operand is fetched from the register 116 via the register read buses 127 to 129, and each atom is executed (step S15).

After the execution of each atom, the speculativeness judging sections 111 to 111
It is determined whether the execution of the atom is speculative by 113 (step S17). If it is speculative, the identification information of the register to be changed, the value before the change of the register, the group value of the atom, To the register saving unit 11
4 (step S18).

Thereafter, if the atom is a conditional branch instruction, whether or not the branch to the label associated with the conditional branch instruction is recorded in the branch history storage unit 115. For other types of atoms, register write buses 139-1
The execution result is written back to the register 116 and the memory 101 via the memory bus 41 and the memory bus 142 (step S1).
9).

Incidentally, the in-order instruction issuance VL
In the IW processor, in an integer operation pipeline and a floating point operation pipeline, an atom in a certain VLIW instruction is replaced with another VLIW instruction located earlier in the program order.
It does not complete before the execution of the atom in the instruction is completed. Therefore, VLI exceeding VLIW instruction including conditional branch instruction
Speculative execution of the W instruction cannot occur. For the same reason, speculative execution of a VLIW instruction exceeding a VLIW instruction including a load instruction and a store instruction cannot occur.

As described above, the in-order instruction issuance V
In the LIW processor, speculative execution due to completion of out-of-order execution cannot occur. On the other hand, in a code generated by a speculative code arranging method in which an atom at one branch destination of a conditional branch instruction (conditional branch atom) is arranged before the conditional branch instruction, the in-order instruction issuing VLIW processor uses the atom. Is executed speculatively.

Conventionally, in a code scheduling method in which an atom is speculatively arranged, if a compiler needs to return a changed register to a correct value when a speculatively arranged atom is erroneously executed, the compiler is required to do so. Generate a correction code.

The present invention makes it possible to return a register to a correct value without using a correction code when a speculatively executed atom is erroneously executed in a code in which the atom is speculatively arranged. . As a result, it is possible to prevent the code size from increasing due to the correction code.

Next, a method for the compiler to generate speculative instruction arrangement codes that operate on the processor of this embodiment will be described.

The compiler according to the present embodiment has a basic configuration similar to that of a conventional compiler. However, in the course of the processing, addition of a group value to an instruction (atom) and speculation of an instruction (atom) are performed. Placement, tbt, tbn
And inserting two types of branch trap instructions (branch trap atoms). In addition,
Regarding the instruction scheduling method, (1) a method of speculatively arranging at the symbol register stage, (2) a method of speculatively moving an atom arranged non-speculatively at the symbol register stage, and (3) non-speculatively A method of speculatively moving an atom allocated and assigned to a register is conceivable, but this method can be realized by any method. Hereinafter, a method based on (3) will be described.

First, a group value is assigned to all conditional branch instructions (conditional branch atoms) before instruction movement so that the number of conditional branch instructions having the same group value is reduced as much as possible. This means that, for example, to each conditional branch instruction, a group value increased by one from the smallest group value in code order is assigned, and if the group value exceeds the maximum value, it is again assigned in order from the smallest group value. Can be realized in a way.

Next, an atom to be moved is selected and moved. As for this method, any conventionally proposed method can be applied (eg, JA Fisher,
“Trace scheduling: Atechni
que fon global microcode
compaction ”, IEEE Transact
ions on Computers, 30 (7), 1
981). However, the destination of the atom must satisfy the following conditions. -Conditional branch instructions (atoms) included in the path from the atom destination to the atom's original position have different group values. The atom cannot be moved to a position that does not satisfy this condition. Therefore, the greater the distance between branch atoms having the same group value, the greater the possibility of speculative instruction movement. The above-described group value assignment scheme takes this into consideration. A flag indicating that the atom is speculative is attached to the moved atom, and a group value of a conditional branch instruction that the atom first crosses is assigned. Finally,
A branch trap instruction (branch trap atom) is placed at the head of the branch destination that does not include the atom among the branch destinations of the conditional branch instruction that the atom first crosses, and the group value of the conditional branch instruction is set to this branch. Assign to a trap instruction. This is shown in FIG.

The type of the branch trap instruction (atom) to be arranged is selected based on the following criteria. -If an atom is placed at the branch destination where the label is written in the conditional branch instruction, the tbn instruction (trap i
f branch not take) • If an atom is placed at the branch destination where no label is written in the conditional branch instruction, a tbt instruction (trap
If branch take) The selection of the code and the criterion for terminating the movement can be performed using a conventional method, similarly to the above-described selection and movement of the atom to be moved.

FIG. 24 shows an example of code in which non-speculative instruction arrangement and register allocation have been completed. Based on this method, the atom 1 of the VLIW instruction 4, that is, "lir21,
1024 "is moved to the position of atom 2 of VLIW instruction 1 beyond the conditional branch instruction" beq r3, r18, VLIW instruction 6 (address) "of atom 1 of VLIW instruction 3.

First, the atom 1 of the VLIW instruction 4 is converted to the VLI
Move to W instruction 1. At this time, if it is assumed that the group value “1” is added to the conditional branch instruction of the VLIW instruction 3, the group value “1” is added to the atom 2 of the VLIW instruction 1 after the movement (the group of the conditional branch instruction that is first exceeded) Value) is added. Further, a speculative flag indicating speculative is attached to atom 2 of the VLIW instruction 1. There are two types of speculative flags, st (speculative if)
(taken) indicates that the conditional branch instruction becomes speculative when it branches toward the label, and sn (specul)
"active if not taken" indicates that otherwise it is speculative. In the case of this example, st is added. Note that as a result of the instruction movement, VLIW in FIG.
Instruction 4 is deleted because it is no longer needed.

Next, a branch trap instruction is assigned. In the case of this example, the original position of the moved atom (VLIW instruction 4 in FIG. 24) is included in the path not labeled in the conditional branch instruction of VLIW instruction 3, so that the type of the branch trap instruction is The tbt instruction is chosen. Then, the head of the label written in the conditional branch instruction (FIG. 24)
The tbt instruction is placed in the VLIW instruction 6). In this case, a group value “1” is added to the tbt instruction.

The code finally obtained in this way is as shown in FIG. In addition, the value in [] represents a group value.

The addition of a group value and a speculative flag to an atom is realized, for example, by arranging, in a memory, one including an extended atom in addition to atoms 1 to 3 as one VLIW instruction as shown in FIG. it can. The instruction decoding unit 104 obtains a group value and a speculative flag of each atom from the extended atom at the time of decoding. The extended atom is, for example, one in which three sets of group values and speculative flags are arranged as shown in FIG. The group value is composed of an arbitrary number of bits, and the range of numbers represented by the number of bits is the range of the group value. The speculative flag is 2 bits and has the meaning shown in FIG. 28 (01 corresponds to st and 10 corresponds to sn).

Next, in the processor of this embodiment,
The following describes in more detail how each unit operates when the code in which the atoms are speculatively arranged is executed, and the configuration or function of some units.

Here, the operation when the code of FIG. 25 is executed will be described as an example. For simplicity, it is assumed that there are no instructions being processed in the pipeline at the beginning of the code. The definition of the pipeline stage is the same as in the first embodiment. The speculative flag is based on the example of FIG.

First, the instruction fetch unit 102 fetches the VLIW instruction 1 in the F stage of the cycle 1.

Next, in the D stage of cycle 2, the instruction decode unit 104 decodes the VLIW instruction 1, and in the F stage, the instruction fetch unit 102 fetches the VLIW instruction 2. As a result of the decoding, the group value “1” of the atom 2 of the VLIW instruction 1 and the speculative flag “01” are obtained.

Next, in cycle 3, the operand judging unit 1
05 is a register r used by each atom of the VLIW instruction 1
It is determined whether 2, r16 and r5 are available. Note that the operand determination unit 105 can be realized with the same configuration as in the first embodiment. Since all of these registers can be used, the atoms 1 to 3 of the VLIW instruction 1 together with the group value and the speculative flag are used in the instruction execution unit 108
１１０110 and executed in the E stage. on the other hand,
At the D stage, the instruction decode unit 104 decodes the VLIW instruction 2, and at the F stage, the instruction fetch unit 102
Fetch IW instruction 3.

When the execution of the VLIW instruction 1 is completed, the speculativeness determining units 111 to 113 determine whether each atom has been speculatively executed. If the speculativeness flag of the atom is “00”, the speculativeness judging units 111 to 113 are non-speculative.
If it is “01” or “10”, it is determined to be speculative. In the case of this example, the atom 1 of the VLIW instruction 1 “lbur r2,
0 (r16) ”is determined to be non-speculative from the speculative flag“ 00 ”, and the atom 2“ li. str
5,1024 "is determined to be speculative from the speculative flag" 01 ".

With respect to the atom 2 of the VLIW instruction 1 determined to be speculative, the register number “5”, the value of the register r5, its group value “1”, and the speculative flag “01” are registered in the register saving unit 114. I do. Thereafter, the values of the registers r2 and r5 are updated in the W stage.

Here, the register saving unit 114 is a buffer for storing information for returning the processor to a correct state when a speculative atom is incorrect. Registration and deletion of information in the register save unit 114 and restoration of a register value based on the information are performed according to the following rules. When a speculative atom updates the processor state, a register changed by the atom, a value before the change of the register, a group value of the atom, and a speculative flag are registered. A speculative execution mistrap is generated when the tbt instruction is executed when the value of the branch history storage unit 115 described later is “branch” or when the tbn instruction is executed when the value is “straight ahead”. At this time, the register registered by the atom having the same group value as the tbt instruction or the tbn instruction is restored using the information of the register saving unit 114. When the conditional branch instruction updates the branch history storage unit 115, the register saving unit 11 having the group value before the update
4 is deleted.

In the pipeline processing, the VLIW instruction 2 is executed after the completion of the VLIW instruction 1, and the VLIW instruction 3 including a conditional branch instruction (atom) is executed after the completion. When the conditional branch instruction is executed, the operation of the branch is stored in the branch history storage unit 115.

The following information is registered in the branch history storage unit 115. -Group value of conditional branch instruction-Information indicating "branch" when the conditional branch instruction branches in the label direction, otherwise indicating "straight ahead" VLIW instruction 4 is executed after VLIW instruction 3 is completed And
After the completion, the VLIW instruction 5 is executed. At that time, V
When the information stored in the branch history storage unit 115 of the LIW instruction 3 is “straight ahead”, no trap occurs in the tbt instruction, and the atom 2 of the VLIW instruction 1 is stored in the register save unit 114.
The information registered in is deleted as it is. On the other hand, if the information stored in the branch history storage unit 115 is “branch”, t
The bt instruction causes a speculative execution mistrap.

In the speculative execution mistrap, the following processing is performed depending on the type of the branch trap instruction. When a speculative execution mistrap occurs due to a tbt instruction, the speculative flag is “01” in the register information of the register saving unit 114 with the same group value as the tbt instruction.
When the speculative execution mistrap occurs with the tbn instruction, the register information of the register saving unit 114 has the same group value as the tbn instruction and the speculative flag is set to “10”. "
In this example, the register having the group value “1” and the information having the speculative flag “01” registered in the register saving unit 114, that is, the register r5 is the original register. Is returned to the value of

Thereafter, when the next conditional branch instruction is executed, the information having the group value “1” among the information of the register saving unit 114 is deleted.

(Fifth Embodiment) In the first to third embodiments, the case where the present invention is applied to an in-order instruction issuing superscalar processor will be described, and in the fourth embodiment, the present invention will be described as an in-order instruction. Instruction issue VLIW
Has been described, but in the present embodiment,
A case in which the present invention is applied to an out-of-order instruction issuing VLIW processor will be described.

The present invention enables dynamic speculative execution in an out-of-order instruction issuing VLIW (hereinafter, dynamic VLIW) processor.
Dynamic VLI that enables its dynamic speculative execution
Before describing the W processor, dynamic VL
The basic configuration of the IW processor will be described.

In the following, each instruction constituting one VLIW instruction may be called an atom, as in the fourth embodiment. FIG. 29 shows an example of one VLIW instruction. This is an example in which one VLIW instruction is composed of three atoms. The position where each atom constituting the VLIW instruction should enter is called a slot.

As a method of increasing the parallelism at the instruction level, there are a VLIW method in which resources are statically allocated and used at compile time and a superscalar method in which resources are dynamically allocated at execution time.
In the VLIW method, since a compiler detects instructions that can be executed simultaneously, a mechanism for detecting the instructions at the time of execution is not required, hardware at the time of execution is simplified, and a high frequency may be achieved. However, the method of detecting instructions that can be executed simultaneously by the compiler includes parameters that cannot be completely predicted by the compiler or that cannot be realistically predicted.

The dynamic VLIW method is located between the super scalar method and the VLIW method. Basically, the dynamic VLIW method partially executes the VLIW method to solve a problem that is difficult to predict at the time of compiler. However, it operates to some extent dynamically and can proceed with processing without stopping the entire processor. That is, this dynamic VL
The IW method seeks a new optimal point of hardware and software (compiler) and aims at optimizing performance.

In the basic configuration of a processor based on the dynamic VLIW method, a pending queue for temporarily saving an fetched but unexecutable atom so that a subsequent atom can be executed in advance is provided. It stores and manages information on the use status of each register, determines whether or not the fetched atom can be executed based on this information, executes the fetched atom if executable, and fetches if not executable The accumulated atoms are stored in the pending queue,
Judgment of the execution of the atom stored in the pending queue is performed. If the execution is possible, the atom is executed. It can be executed first.

The dynamic VLIW method is based on the VLI
The point of fetching an atom for each W instruction is the conventional in
-Order instruction issuance VLIW is the same as that of the VLIW instruction, but when a plurality of atoms of the simultaneously fetched VLIW instruction cannot be executed, the conventional in-order
In the r instruction issue VLIW, the fetch is always interrupted, but in the dynamic VLIW method, there is a possibility that the fetch need not be interrupted.

FIG. 30 shows such a dynamic VLI.
It is a conceptual diagram showing the basic structure of W processor.
In FIG. 30, two pipeline units (1006-
1, 1006-2). This dynamic VLIW processor is provided with a pending queue (P) for saving an atom fetched from an instruction sequence as an execution wait when the atom cannot be immediately executed.
Out-of-order is determined using queues 1002-1 and 1002-2 provided independently for each slot called "ending queue" and a scoreboard 1004 for managing information on the use status of each register for each register. This is an example that has been realized.

An atom that is not executed among the plurality of atoms of the fetched VLIW instruction is executed until it becomes executable.
Stored in the corresponding pending queue.

The pending queue is preferably constituted by a FIFO (first-in first-out buffer). When the pending queue is configured by FIFO, the execution is performed in order from the first atom stored in the pending queue, which is different from the conventional superscalar reorder buffer. In other words, in exchange for a performance constraint that an executable atom may not be executable even if it exists in the pending queue, the hardware can be greatly simplified and the speed can be increased.

Further, the pending queue is a VLIW
It is preferably provided for each slot into which the individual atoms making up the instruction are to enter. For example, the VLI illustrated in FIG.
When the format of the W instruction is used, since there are two slots, two pending queues are prepared.
Then, an atom that is not executed among the fetched VLIW instructions is put into a pending queue corresponding to the slot. The fact that a pending queue exists for each slot as described above and does not span slots also constitutes one of the limitations for simplifying hardware and increasing the speed.

In each cycle / slot, an atom giving an opportunity to execute may be an atom fetched from a normal instruction sequence or an atom from the pending queue when the pending queue is not empty.
Execution is prioritized in the order of (1) the fetched atom and (2) the atom in the pending queue.

The determination as to whether an atom given an opportunity to be executed (a fetched atom or an atom at the head of the pending queue) is executable is based on the contents of the scoreboard (use of registers related to the atom).
Basically, if the register used by the atom is not available to the atom, it is determined that the atom cannot be executed.

As described above, in the dynamic VLIW method, an out-of-order method is realized by temporarily saving atoms that cannot be executed immediately in the pending queue and executing them when they become executable. .

In the dynamic VLIW system, registers are assigned by a compiler without having a renaming configuration in the processor. Eliminating register renaming can simplify the hardware.
For this purpose, as a compiler that generates a VLIW instruction sequence, a compiler that assigns registers so that false dependency does not occur is used (a known compiler may be used).

Next, the outline of the dynamic VLIW will be described with reference to a simple example in order to show the effects of the dynamic VLIW.

FIG. 31 shows an example of an instruction sequence to be executed.
An example of an instruction sequence when two atoms are included in one VLIW instruction is shown.

As shown in FIG. 31, this instruction sequence is
ADD R8, R9, R10 and LD R5, (R3),
LDI R18,1000 and ADDI R13, R9,
4, ADD R21, R18, R9 and SUB R11,
R5, R8, LSR R22, R21, 5 and ORI
R24, R21, 0xFF, SUBI R25, R2
4, 5 and NOP, BRZ R11, R0, ROOP_E
XT and NOP are fetched one by one in this order.

In the following, the instruction sequence illustrated in FIG.
n-order instruction issue VLIW method and dynamic V
A description will be made in comparison with the case where the respective processes are executed by the LIW method.

FIG. 32 shows that this instruction sequence is a conventional in-or
FIG. 33 shows a case where the der instruction is executed by the VLIW system, and FIG. 33 shows a case where the instruction sequence is executed by the dynamic VLIW system.

In the examples of FIGS. 32 and 33, the first VLIW
LD (load instruction), which is the atom of the second slot of the instruction
Caused a miss in the primary cache and the corresponding data was 2
It is assumed that four cycles are required to load this because it exists in the next cache.

As shown in FIG. 32, when this instruction sequence is executed by the conventional in-order instruction issuance VLIW method, in cycle 1, ADD R of the first slot
8, R9, R10 and LD R5, (R
3) is executed, but since the LD in the second slot causes a cache miss, the four cycles of cycles 2 to 5 are stall due to the LD miss in both the first and second slots (while fetch is interrupted). Thereafter, the instructions are sequentially executed, and as a result, the processing is completed in 10 cycles.

Next, as shown in FIG. 33, when this instruction sequence is executed by the dynamic VLIW method, first, in cycle 1, ADD R8, R
9, R10 and LD R5, (R3) in the second slot are executed, and the LD causes a cache miss. From the next cycle, an atom using the destination register R5 of this LD cannot be executed until the LD is completed (the status of this register R5 is reflected on the scoreboard).

In cycle 2, since each atom of the VLIW instruction does not use R5, which is the destination register of LD, LDI R18,1000 and ADDI
R13, R9, and 4 are executed.

At cycle 3, ADD of the first slot
R21, R18, and R9 are executed because R5 is not used, but SUB R11, R5, and R8 in the second slot are
Since R5 is referred to as the first source register, it cannot be executed and is put into the pending queue (it can be seen that R5 cannot be used by referring to the scoreboard, so it cannot be executed). Also, from the next cycle, atoms (excluding this SUB) using the SUB destination register R11 cannot be executed until this SUB is completed (the status of this register R11 is also reflected on the scoreboard). Is done).

In cycle 4, since neither R5 nor R11 is used, LSR R22, R21, 5 and ORI R2
4, R21, 0xFF is executed.

In cycle 5, since neither R5 nor R11 is used, NOBI is executed with SUBI R25, R24, 5.

Here, the LD is completed, and from the next cycle, R5 becomes available (the status of this register R5 is also reflected on the scoreboard).

In cycle 6, first, B in the first slot
RZ R11, R0, and ROOP_EX cannot be executed because R11 is the destination. As will be described in detail later, when the register to be used as the destination cannot be used, the register is not put into the pending queue and waits for the executable state (the fetch is interrupted). Therefore, this cycle becomes an empty slot. Since the fetch is interrupted, the execution of the fetched instruction in the second slot is also suspended.

Here, in the second slot, since the interruption of the fetch has occurred, the execution opportunity is given to the atom in the pending queue. SUs in the pending queue
BR11, R5, and R8 are executable because the previous LD has been completed and R5 is available (it can be understood by referring to the scoreboard).
Therefore, SUB R11, R5, and R8 are taken out of the pending queue and executed.

Here, SUB is completed, and R11 becomes available from the next cycle (the status of this register R11 is also reflected on the scoreboard).

In cycle 7, BRZ R11, R0, ROOP_EXT waiting for execution in the first slot are
Executable and executed, and in the second slot, the NOP waiting for execution is executed.

As a result, the process is completed in seven cycles.

As described above, where the conventional in-order instruction issuance VLIW system takes 10 cycles,
It can be seen that in the dynamic VLIW method, the execution is completed in seven cycles and the speed can be increased by an out-of-order function that can be executed by another atom during a miss due to an LD atom.

The basic configuration of the dynamic VLIW processor capable of out-of-order has been described above.

Now, the dynamic VLIW processor according to the present embodiment, which enables out-of-order and enables dynamic speculative execution of a conditional branch instruction and a load / store instruction, will be described in detail below.

FIG. 34 shows an example of the configuration of a dynamic VLIW processor that can be dynamically speculatively executed according to the present embodiment.

As shown in FIG. 34, the processor of this embodiment comprises a memory 201, an address generation unit 203, an instruction fetch unit 202, a processor status register 204,
Instruction decoding unit 205, group value generation unit 206, pending queues 209 to 211, instruction execution permission unit 20
7, operand state determination unit 208, instruction execution unit 2
12 to 214, a speculative determination unit 215 to 217, a register saving unit 218, and a register 219.

The main difference from the configuration example of FIG. 1 lies in that a processor status register 204 and an instruction execution permitting unit 207 are provided.

In the present embodiment, there is shown an example in which there are three instruction execution units, that is, one VLIW instruction is composed of three instructions. However, in the case where there are two or four or more instruction execution units, , Ie one VLIW
The present invention is applicable to a case where an instruction is composed of two or more instructions.

In the following, description will be made focusing on the points in which this embodiment is different from the first embodiment.

First, the outline of the dynamic VLIW processor shown in FIG. 34 will be described.

Instruction fetching and decoding are performed in accordance with the conventional or fourth embodiment of the in-order instruction issuing VLI.
This is performed in the same manner as in the W processor. Decoded VL
For the IW instruction, the operand state determination unit 208 determines whether the operand used by each atom is usable.

If all operands are available,
Instruction execution is started in the same manner as in the conventional or the in-order instruction issuing VLIW processor of the fourth embodiment.

If there is an operand that cannot be used, the atom that uses the operand is a conditional branch instruction, a load instruction or a store instruction, or if the output operand of the instruction cannot be used, the operation is stalled. Execution is started when becomes available.

On the other hand, when another type of instruction uses an unusable operand, the decode information of these instructions is stored in the corresponding pending queue 2 without stalling.
09 to 211.

Then, only executable instructions are sent to the instruction execution units 212 to 214 and executed.

If the atoms in the pending queues 209 to 211 cannot be executed in the slot corresponding to the subsequently decoded VLIW instruction and the operand state determination unit 208 determines that they can be used, the pending queue 209 To 211 are sent to the instruction execution units 212 to 214 and executed.

The operation from the execution of the atom to the completion thereof is the same as that of the in-order instruction issuance V according to the conventional or fourth embodiment.
It is similar to the LIW processor.

[0275] The operand state determination unit 208
It can be realized using the scoreboard method shown in the first embodiment as follows. -When an atom enters the pending queue, it is assumed that the input register and output register used by the atom are being used. When the execution of the load atom is started, the output register is used. -When an atom that uses a register as an input is removed from all pending queues, the register is made available. • The output register is available when the load to write to that register is completed in addition to the above conditions.

Next, a case where speculative execution is performed by the dynamic VLIW processor shown in FIG. 34 will be described in detail.

FIG. 35 shows an example of the flow of pipeline processing in the processor of this embodiment.

Instruction fetch (step S61), instruction decode (step S62), and group value acquisition (step S63) are sequentially performed.

[0279] Of the atoms in the decoded VLIW instruction, those whose execution is not permitted by the instruction execution permitting unit 207 are set in the pending queue 20 regardless of the type of instruction.
9 to 211 (steps S64 and S72).
At this time, a group value is added to the atom by the group value generation unit 206, and this group value is also put in the pending queues 209 to 211.

Of the atoms in the decoded VLIW instruction, those whose execution is permitted by the instruction execution permitting unit 207 are transferred to the instruction execution units 212 to 214 and executed (steps S64 and S65). Again, in this case,
The group value is added to the atom by the group value generation unit 206.

On the other hand, pending queues 209 to 211
At the corresponding slot in the subsequently decoded VLIW instruction cannot be executed.
If the execution is permitted by the instruction execution permission unit 207 (steps S73 and S74), the instruction is transferred from the pending queue to the instruction execution units 212 to 214 and executed (step S65).

After the execution of the atom, the speculativeness judgment sections 215-2
It is determined whether or not the instruction execution is speculative by step 17 (step S67). If it is speculative, the identification information of the register to be changed, the value of the register before the change, and the group value of the atom are registered in the register. The information is registered in the evacuation unit 218 (step S68). Thereafter, the state of the processor is updated (step S69).

If it is found that the branch destination predicted at the time of fetch is different from the actual branch destination during execution of the conditional branch instruction, a branch prediction mistrap is applied (step S6).
6) The fetch processing and decoding processing are canceled, and the V after the VLIW instruction including the atom that caused the trap
Delete all atoms belonging to the LIW instruction (step S
70). Instruction fetch is stopped until the trap processing is completed. When all the atoms being executed have been completed, all the registers registered in the register saving unit 218 are returned to the registered original values (step S71). Further, the group value generation unit 206 is returned to the initial state. Then, the address generation unit 20
The address indicated by No. 3 is set as a correct branch destination, and the trap processing is completed.

If a page fault occurs during execution of a load instruction or a store instruction, a page fault trap is performed (step S66). In the page fault trap, similarly to the branch prediction mistrap, fetch processing, decoding processing cancellation, pending queue
The erasure of 211 (step S70) and the restoration of the register value are performed (step S71), during which the instruction fetch stops. At the same time, paging processing is performed. When these processings are completed, the group value generation unit 206 is returned to the initial state, and the address indicated by the address generation unit 203 is set to the address of the VLIW instruction including the load instruction and the store instruction, and the trap processing is performed. Complete.

FIG. 36 shows a configuration example of the pending queue.

In the pending queues 209 to 211,
Instruction decode information, instruction group value,
One-bit information called an -order flag is registered. When the following instruction (called a commit instruction) is put in the pending queue, the in-order flag is set to 1
And 0 for other instructions. -Conditional branch instruction, load instruction, store instruction-Instruction whose output operand cannot be used by the operand state determination unit 208. The processor state register 204 has 2 bits.
It has the meaning of FIG. When the value is “01”, the conditional queue instruction, the load instruction, and the store instruction are assigned to the pending queues 209 to 211 even if the operand to be used is available.
Can be put in. When the value is “10”, the instruction fetch unit 202 does not fetch an instruction.

The group value generation unit 206 can be realized by a bit vector system or a hardware counter system as in the first embodiment. However,
In the present embodiment, the pending queues 209 to 2
The group from the commit instruction entering 11 to the next commit instruction entering the pending queues 209 to 211 is one instruction group. The order between atoms in the same VLIW instruction is from atom 1 to atom 3.

In this embodiment, the order of execution between commit instructions must be preserved. for that reason,
When the group value generation unit 206 is implemented by the bit vector method, another mechanism is required to grasp the order. This mechanism can be realized by the following FIFO. An instruction closer to the head of the FIFO is determined to be a previous instruction. When the group value assigned to the instruction is changed, put the group value at the end of the FIFO. In-ord having the group value at the beginning of the FIFO
When an instruction whose er flag is 1 is issued from the pending queue, the group value is output from the FIFO. On the other hand, the hardware counter implementation includes an execution instruction counter (see FIG. 5) to ensure that the group values do not overlap. ing. In this realization, the order between the instruction A and the instruction B is as follows: if the group value of the instruction A is x, the group value of the instruction B is y, and the value of the execution instruction counter is z
8 is determined.

The instruction execution permitting unit 207 permits the transfer of the instruction to the corresponding execution unit. If some of the operands used by an instruction cannot be used, execution of the instruction is not permitted. If all operands are available, the execution of the instruction is permitted if the value of the processor status register 204 is "00". Processor status register 2
When the value of 04 is "01", execution permission and non-permission are determined as shown in FIG. 39 according to the instruction issue location (instruction decoding unit or pending queue) and the type of instruction.

The speculative judgment sections 215 to 217 can be realized in the same manner as in the first embodiment.

Although the register saving unit 218 can be realized in the same manner as in the first embodiment, the conditions for deleting registered information are changed as follows. When an instruction with an in-order flag of 1 is completed without causing a trap, information having the same group value as that of the instruction is deleted.

Hereinafter, the dynamic VL of this embodiment will be described.
The operation when the code of FIG. 40 is executed in the IW processor will be described. For the sake of simplicity, it is assumed that no instruction is being processed in the pipeline at the start of the code, and the value of the processor status register 204 is "00". The definition of the pipeline stage is the same as in the first embodiment.

First, VLIW in the F stage of cycle 1
Instruction 1 is fetched, and VL is
Decoding of the IW instruction 1 and fetching of the VLIW instruction 2 are performed in the F stage. Decoded VLIW instruction 1
Are added with a group value "0". Here, it is assumed that the group value generation unit 206 is realized by a hardware counter method.

Subsequently, in cycle 3, the operand used by each atom of the VLIW instruction 1 is
08, it is determined that all of them can be used. Since the value of the processor status register 204 is "00", the execution is permitted by the instruction execution permitting unit 207, and each atom is transferred to each of the instruction execution units 212 to 214. Executed in On the other hand, in the D stage, the VLIW instruction 2 is decoded, and in the F stage, the VLIW instruction 3 is fetched, and a group value “0” is added to each instruction of the VLIW instruction 2.

Next, at the start of cycle 4, the execution of the atom 1 "addi r12, r0, 3" of the VLIW instruction 1 is completed, and the execution of the atom 2 "lwr3, level (r
"0)" is being executed, but no page fault has occurred. Since the speculativeness determining unit 215 determines that the atom 1 is not speculative, the atom 1 does not register information in the register saving unit 218, and does not register information in the W stage. Update the register r12.
On the other hand, each atom of the VLIW instruction 2 is permitted to execute and
Performed on stage. The VLIW instruction 3 is decoded at the D stage, a group value “0” is added to each atom, and the VLIW instruction 4 is fetched at the F stage. Hereinafter, the fetch and decode processes will be omitted. It is also assumed that the execution of the atom 2 of the VLIW instruction 1 is not completed until after the execution of the VLIW instruction 12.

After the execution of VLIW instruction 2 and VLIW instruction 3 is completed, the state of the register is updated without saving the register because it is not speculative. Here, even after the decoding of the VLIW instruction 4, the atom 2 of the VLIW instruction 1 “lwr3, level”
Since (r0) "is being executed, the operand 1 of the VLIW instruction 4" slti r4, r3, 20 "is determined by the operand state determination unit 208 to be unable to use the operand r3, and its decode information is stored in the pending queue 2
09 together with the group value “0” and the in-or
The der flag is set to “0”.

Similarly, after decoding of VLIW instruction 5, V
Since atom 2 of LIW instruction 1 is being executed, VLIW
The atom 1 of the instruction 5 “beq r4, r0, (address of the VLIW instruction 8)” is put in the pending queue 209 together with the group value “1” because the register r4 cannot be used, and the in-order flag is set to 1. You. Then, the processor status register 204 is set to “0”.
Here, assume that atom 1 of VLIW instruction 5 is predicted not to branch to VLIW instruction 8 at the time of fetch.

Next, atom 1 “add” of VLIW instruction 6
Since the operands of iu r12, r0, 2 ″ are available, they are transferred to the instruction execution unit 212 and executed. After execution, the speculativeness determination unit 215 determines that the speculativeness has occurred. And the group value “1” are registered in the register saving unit 218. Then, the register r12 is updated.

Next, atom 2 “sw” of VLIW instruction 7
Although the operand of “r12, libs (r0)” can be used, since the processor status register 204 is “01”, the store instruction is not executed and is put in the pending queue 210 together with the group value “2”. −
The order flag is set to "1".

Next, atom 1 “slt” of VLIW instruction 8
i r12, r3, 2 "is a commit instruction because the output operand r12 cannot be used. Therefore, it enters the pending queue 209 together with the group value" 3 ".
The in-order flag is set to “1”.

Next, atom 1 “beq” of VLIW instruction 9
r12, r0, (address of VLIW instruction 12) "
Also enters the pending queue 209 together with the group value “4” because the operand r12 cannot be used, and
The −order flag is set to “1”. Here, VLIW
Assume that atom 1 of instruction 9 is predicted to branch to atom 12 at the time of fetch.

Next, atom 1 “ad” of VLIW instruction 12
diu r29, r29, 12 ″ is the operand r29
Are available and transferred to the instruction execution unit 212 for execution. On the other hand, Atom 2 “move r2,
Since the operand r12 cannot be used, the operand r12 is put in the pending queue 210. Since the execution of the atom 1 is speculative, the register r29, its original value, and the group value “4” are registered in the register saving unit 218. Thereafter, the register r29 is updated.

At this time, the pending queue 209-
The state of 211 is shown in FIG. Each item is a group value, the number of the VLIW instruction to which the atom belongs, i
Indicates an n-order flag. FIG. 42 shows the state of the register save unit 218 at this time.

Thereafter, atom 2 “lw” of VLIW instruction 1
When the execution of “r3, level (r0)” is completed, the register r3 becomes usable, and the group value becomes “0”.
Atom 1 “sltir r4, r of VLIW instruction 4”
3, 20 "is transferred from the pending queue 209 to the instruction execution unit 212 and executed.

After the execution of the atom 1 of the VLIW instruction 4 is completed, the register r4 becomes available. Therefore, the instruction 1 “beq r4,” of the VLIW instruction 5 whose group value is “1”
r0, VLIW instruction 8 (address of) ”is transferred from the pending queue 209 to the instruction execution unit 212 and executed. At this time, the execution instruction counter becomes“ 1 ”.

Assuming that the branch prediction of the conditional branch instruction is correct, the execution of the conditional branch instruction is completed without generating a trap. At this time, the information about the group value “1” saved in the register saving unit 218 is deleted. In FIG. 42, the information on the register r12 corresponds thereto.

Subsequently, the VLI whose group value is “2”
Atom 2 “sw r12, libs (r
0) ”is executed from the pending queue 210, and the execution instruction counter becomes“ 2 ”.

Assuming that this store instruction is completed without causing a page fault, the atom 1 “sltir12, r3, atom1” of the VLIW instruction 8 whose group value is “3” is next.
2 is executed and the execution instruction counter becomes “3.” The register saving unit 218 stores the group values “2” and “3”.
Since no register information is registered, no information is deleted upon completion of these instructions.

On the other hand, when the above store instruction causes a page fault, first, the fetch processing and the decode processing of the instruction are canceled, and the pending queues 209 to 209 are canceled.
211 is erased. In this example, the atom 1 “beq r12, r0, (address of) the VLIW instruction 12” of the VLIW instruction 9 is deleted from the pending queue. Then, after the processor status register 204 is set to “10”, the register evacuation unit 21
8 is returned to the original value, and at the same time, paging processing is performed. In this example, the register r29 is returned to the original value. Finally, the group value generation unit 206 is returned to the initial state, and the processor status register 204 is set to “0”.
The trap processing is completed by setting the address indicated by the address generation unit 203 to 0 "as the address of the VLIW instruction including the store instruction.

If the store instruction does not cause a page fault, the VLIW instruction 8 atom 1 "sltir12,
When the execution of “r3, 2” is completed, the atom 1 “beq r12, r0, (address of) the VLIW instruction 12” of the VLIW instruction 9 is transferred from the pending queue 209 to the instruction execution unit 212. At this time, the execution instruction counter is It becomes “4” and the processor status register 204 becomes “0”.
0 ".

When the execution of this conditional branch instruction is completed without generating a branch prediction mistrap, the register information (in this example, information about the register r29) of the register save unit 218 relating to the group value “4” is deleted. You.

The processing in the case where the above conditional branch instruction generates a branch prediction mistrap is described above, except that there is no paging processing and that the address indicated by the address generation unit 203 is set to the address of the VLIW instruction 10. This is the same as the case of the page fault trap of the store instruction.

Note that the in-order of the first embodiment is used.
Like the instruction issuing superscalar processor, the dynamic VLIW processor of the present embodiment has a Pre
The embodiment in which the instruction with dictate is executed speculatively can also be realized by the same method as the second embodiment. Further, a method that does not require speculative judgment of each instruction and save / restore of registers by using a SYNC instruction as in the third embodiment can be applied to this embodiment as it is.

The compiler in each of the embodiments can be realized as software. Further, the compiler in each of the embodiments is a computer-readable program that records a program for causing a computer to execute predetermined means (or for causing a computer to function as predetermined means, or for causing a computer to realize predetermined functions). It can also be implemented as a possible recording medium.

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications within the technical scope.

[0316]

According to the present invention, a unique identification number is added to each instruction of a program section between predetermined specific instructions for each program section, and speculative execution is performed based on the identification number. Since processing is performed, storage of less information and effective speculative execution with a smaller amount of hardware are enabled.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a processor according to first and second embodiments of the present invention.

FIG. 2 is a flowchart illustrating an example of pipeline processing according to the first, second, and fourth embodiments of the present invention;

FIG. 3 shows an example of a program.

FIG. 4 is a diagram for explaining a case where a group value generation unit is realized by a bit vector;

FIG. 5 is a diagram for explaining a case where a group value generation unit is realized by a hardware counter;

FIG. 6 is a diagram illustrating an example of a criterion for determining whether execution of an instruction is speculative or non-speculative;

FIG. 7 is a diagram showing an example of a criterion for determining whether or not to permit updating of a state of a processor;

FIG. 8 is a diagram for explaining a case where a plurality of pieces of information relating to the same register are registered in a register saving unit;

FIG. 9 is a diagram illustrating a case where an execution unit includes a queue.

FIG. 10 is a diagram illustrating an example of a program that does not include an instruction with Predicate.

FIG. 11 is a diagram showing an example of a program including an instruction with Predicate;

FIG. 12 shows a Predi according to a second embodiment of the present invention.
9 is a flowchart showing an example of a processing procedure for register return at the time of a “cate” set trap.

FIG. 13 is a diagram illustrating an example of a format of information stored in a register saving unit;

FIG. 14 is a diagram for describing a case where a malfunction occurs due to re-execution of a trap.

FIG. 15 shows an example of a program.

FIG. 16 is a flowchart illustrating an example of a processing procedure of register allocation and code generation without using a register saving unit according to the third embodiment of the present invention.

FIG. 17 is a diagram for describing a method of selecting a basic block to be subjected to register allocation.

FIG. 18 is a diagram illustrating a register set usable at the beginning of a basic block.

FIG. 19 is a diagram showing an example of a program described by a symbol register.

FIG. 20 is a view for explaining the relationship between basic blocks existing in the program of FIG. 19;

FIG. 21 is a diagram showing an example of a result obtained by performing register allocation and code insertion on the program of FIG. 19;

FIG. 22 is a diagram illustrating a configuration example of a processor according to a fourth embodiment of the present invention.

FIG. 23 is a view for explaining the arrangement of branch trap instructions;

FIG. 24 is a diagram showing an example of a program in which non-speculative instruction arrangement and register allocation are performed.

FIG. 25 is a diagram showing an example of a result obtained by processing the program in FIG. 24;

FIG. 26 is a diagram showing an example of a block arrangement of a VLIW instruction having an extended atom.

FIG. 27 is a diagram showing an example of the format of an extended atom

FIG. 28 is a diagram showing an example of a 2-bit speculative flag;

FIG. 29 is a diagram illustrating an example of a VLIW instruction;

FIG. 30 is a diagram for explaining a dynamic VLIW method;

FIG. 31 is a diagram showing an example of an instruction sequence of a VLIW instruction;

FIG. 32 is a view for explaining a case where the instruction sequence of FIG. 31 is executed by a conventional VLIW method;

FIG. 33 is a view for explaining a case where the instruction sequence of FIG. 31 is executed by a dynamic VLIW method;

FIG. 34 is a diagram illustrating a configuration example of a processor according to a fifth embodiment of the present invention.

FIG. 35 is a flowchart showing an example of pipeline processing in the embodiment.

FIG. 36 is a diagram illustrating a configuration example of a pending queue.

FIG. 37 shows an example of a 2-bit processor status register.

FIG. 38 is a diagram showing an example of a criterion for determining the order between instructions;

FIG. 39 is a diagram illustrating an example of a criterion for determining whether to permit execution;

FIG. 40 shows an example of a program.

FIG. 41 is a diagram showing an example of a pending queue state;

FIG. 42 is a diagram illustrating an example of a state of a register saving unit;

FIG. 43 shows an example of a program.

[Explanation of symbols]

1, 101, 201 memory 2, 102, 202 instruction fetch unit 3 instruction queue 4, 104, 205 instruction decode unit 5, 105, 208 operand state determination unit 6, 206 group value generation unit 7 decode Instruction queue 8-9, 108-110, 212-214 Instruction execution unit 10 Load / store unit 11 Branch instruction execution unit 12-15, 111-113, 215-217 ... Speculative judgment unit 16, 114, 218 ... Register save units 17,116,219 ... Registers 18-21,124-126 ... Instruction buses 22-25,127-129 ... Register read buses 26-29,139-141 ... Register write buses 28,103,203 ... Addresses Generation unit 30 Processor state control unit 31, 142 Memory bus 32 Instruction Queue buses 33, 119 Address buses 34, 117 Instruction fetch buses 35, 120 Decode bus 115 Branch history storage unit 204 Processor status register 207 Instruction execution permitting units 209 to 211, 1002-1, 1002-2 Pending Queue 1004 ... Scoreboard 1006-1, 1006-2 ... Pipeline unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B013 AA12 DD04 5B033 AA07 BE05 CA09 5B045 GG11 5B081 CC23 CC32

Claims (20)

[Claims] 1. A central processing unit having a plurality of operation execution units and allocating the operation execution units when executing an instruction sequence of a program, wherein the instruction sequence of the program is divided by a predetermined specific instruction. When an instruction is issued, an identification number for identifying an instruction belonging to any of the program sections is assigned to each instruction during its execution, using the identification number assigned to each instruction. And a speculativeness determining means for determining whether execution of the instruction is speculative. 2. A central processing unit having a plurality of operation execution units and fetching and interpreting an instruction sequence of a program for each of a series of instructions assigned to each of the operation execution units in advance. Instruction storage means for temporarily saving, storage means for storing information on the use status of each register, and whether or not an instruction fetched based on the information stored in the storage means is executable. Means for temporarily saving the instruction in the instruction storage means when it is determined that the instruction cannot be executed; and, when the instruction sequence of the program is divided by a predetermined specific instruction, An identification number assigning means for assigning an identification number for identifying an instruction to each instruction when executing the instruction, and an identification number assigned to each instruction. Serial execution of instructions with identification numbers central processing unit, characterized in that a speculative determining means for determining whether speculative or. 3. The identification number assigning means holds information indicating whether or not each identification number is in use, and refers to the information when an instruction to which an identification number is to be assigned is the specific instruction. Means for selecting and assigning an identification number that is not in use, and when an instruction to be assigned an identification number is an instruction other than the specific instruction, means for assigning the same identification number as the identification number given immediately before; The central processing unit according to claim 1 or 2, further comprising: 4. The speculativeness judging means, for each identification number given by the identification number giving means, is based on information indicating whether or not a specific instruction given the identification number is being executed. When it is indicated that a specific instruction having the same identification number as the identification number assigned to the instruction to be determined is being executed, the execution of the instruction to be determined is speculative. 4. The central processing unit according to claim 3, wherein the central processing unit determines that the target is appropriate. 5. An identification number assigning means comprising: identification number counter means for holding an identification number assigned to an instruction immediately before; and if the instruction to be assigned an identification number is an instruction other than the specific instruction, The same identification number as the identification number held in the counter means is assigned, and when the instruction to be given the identification number is the specific instruction, the identification number held in the identification number counter means is set to 1 A means for assigning the increased identification number after the number has been increased. 3. The central processing unit according to claim 1, wherein 6. An identification number which has the same initial state as that of said identification number counter means, and when the execution of said specific instruction given said identification number is completed using said identification number counter means, the identification number to be held is set to 1 The speculativeness judging means refers to the identification number counter means and the execution instruction counter means, and the identification number given to the instruction to be determined is the execution instruction. If the identification number corresponds to an identification number within the range from the identification number held by the counter means to the identification number held by the identification number counter means, it is determined that the execution of the instruction subject to the determination is speculative. The central processing unit according to claim 5, wherein 7. The apparatus according to claim 1, further comprising means for retaining information for restoring a register updated by an instruction determined to be speculatively executed to a state before execution of the instruction. Or the central processing unit according to 2. 8. The instruction storage means holds together with the fetched instruction that cannot be executed, an identification number assigned to the instruction and information indicating whether the instruction corresponds to the specific instruction. The central processing unit according to claim 2, wherein: 9. When it is determined that the speculative execution has failed for an instruction determined to have been speculatively executed, a trap corresponding to the cause of the failure is set, and the trapping routine executes the speculative execution. 9. The central processing unit according to claim 1, wherein the central processing unit is returned to a previous state. 10. The speculativeness judging means judges whether or not execution of only a SYNC instruction for restricting speculative execution is speculative, and judges that the SYNC instruction has been speculatively executed. 3. The method according to claim 1, wherein in the case, an instruction subsequent to the SYNC instruction is not executed until the specific instruction input earlier in the program order than the SYNC instruction is completed. Central processing unit. 11. A central processing unit for allocating a plurality of execution units when executing a program instruction sequence, or a program instruction sequence for each of a series of instructions previously assigned to each of the plurality of operation execution units. A compiling method for generating a program to be executed by a central processing unit for fetching and interpreting, wherein an output operand of a certain instruction arranged on one path branched from a conditional branch instruction is the other operand branched from the conditional branch instruction. Has an instruction placed on one of the paths and an output operand that matches one of the input operands of the speculatively executed instruction in such a case that the instruction is referred to by another instruction without being updated in that path SYNC instruction for restricting speculative execution such that such an instruction is not speculatively executed in the central processing unit. A compilation method characterized by generating and assigning instructions. 12. A central processing unit having a plurality of operation execution units and fetching and interpreting an instruction sequence of a program for each of a series of instructions assigned to each of the operation execution units in advance. When demarcated by a specified specific instruction, an identification number for identifying to which one of the program sections the instruction belongs, and information on the speculative property of the instruction are used when interpreting the instruction. Means for extracting, based on the information on the speculative property incorporated in the instruction that has been executed, speculativeness determining means for determining whether or not the execution of the instruction is speculative, and that the instruction has been speculatively executed. Based on the information on the identification number and the speculative property incorporated in the determined instruction,
A speculative result determining means for determining whether or not the speculative execution has succeeded, and when it is determined that the speculative execution has failed for the instruction determined to have been speculatively executed, according to a cause of the failure, A central processing unit comprising: means for trapping. 13. The speculativeness judging means judges that the execution of the instruction is speculative when the information on the speculativeness incorporated in the instruction to be judged indicates that the instruction is speculative. The central processing unit according to claim 12, wherein: 14. The speculative result judging means, when an instruction having the same identification number as the identification number incorporated in the instruction to be judged and corresponding to the information relating to the speculative property is executed, executes the instruction. 13. The central processing unit according to claim 12, wherein it is determined that the speculative execution of has failed. 15. A storage device for temporarily storing evacuation information for returning to a state before performing speculative execution when it is determined that speculative execution of an instruction has failed. The central processing unit according to claim 12, wherein 16. The central processing unit according to claim 15, wherein said evacuation information is held in correspondence with an identification number assigned to an instruction determined to have been executed speculatively. 17. The central processing unit according to claim 16, wherein the return of the state based on the save information is selectively performed by referring to an identification number in the holding means. 18. A compiling method for generating a program to be executed by a central processing unit which fetches and interprets an instruction sequence of a program for each of a series of instructions assigned to each of a plurality of operation execution units in advance. When the instruction sequence is divided by a predetermined specific instruction, an identification number for identifying which instruction belongs to the program section, and information regarding the speculative property of the instruction are added to each instruction. An instruction located after the specific instruction in program order,
A compiling method comprising: moving forward beyond the specific instruction causing speculative execution. 19. A central processing unit for allocating a plurality of operation execution units when executing an instruction sequence of an execution program, or a series of instructions in which an instruction sequence of an execution program is previously assigned to each of the plurality of operation execution units. A compile procedure for generating a program executable by a central processing unit that fetches and interprets each instruction, wherein an output operand of an instruction arranged on one path branched from a conditional branch instruction branches from the conditional branch instruction An instruction placed on one path and an output operand that matches one of the input operands of the speculatively executed instruction in such a case that the instruction is referred to by another instruction without being updated in the other path. SY for restricting speculative execution so that instructions having the same are not speculatively executed in the central processing unit. A computer-readable recording medium recording a compilation program for causing a computer to execute a compilation procedure including a procedure of generating and assigning an NC instruction. 20. A compiling procedure for generating a program executable by a central processing unit that fetches and interprets an instruction sequence of an execution program for each of a series of instructions assigned to each of a plurality of operation execution units in advance. When an instruction sequence of a program is divided by a predetermined specific instruction, an identification number for identifying which instruction belongs to a program section and information on speculativeness of the instruction are assigned to each instruction. Along with an instruction located after the specific instruction in the program order,
A computer-readable recording medium storing a compile program for causing a computer to execute a compile procedure including a procedure of moving forward beyond the specific instruction causing speculative execution.