JP2000284960A - Bit field processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a processing engine, though not dedicated, such as a digital signal processor for example. SOLUTION: This processor is provided with an executing device 802 for a processing engine including a first head partial circuit 804 for obtaining an intermediate signal 818 from an input signal. The executing device 802 includes another circuit 806 which receives the intermediate signal 818, and generates a final signal by operating this intermediate signal. The other circuit 806 is normally constituted so as to be integrated with the first circuit so that one or more signal processing functions can be executed, and generally each circuit is included in each function. The intermediate signal is constituted so as to be used by each different circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a processing engine configurable to manipulate bit fields, and more particularly, but not exclusively, to a digital signal processor.

[0002]

BACKGROUND OF THE INVENTION Many different types of processing engines are known, of which the microprocessor is one example.
For example, digital signal processors (DSPs) are used extensively, especially for certain applications. DSPs are typically configured to optimize the performance of the applications concerned, and use more sophisticated execution units and instruction sets to accomplish this.

[0003]

A particular application of a DSP is in telecommunications equipment. Modern telecommunication devices require high-level processing of data transmitted through the system, for example, error checking or correction techniques such as channel coding and decoding, interleaving and deinterleaving or cyclic redundancy checking. Such processing manipulates the bit fields in the data that are expanded or extracted from data packets transmitted through the telecommunications device to improve or enhance the robustness or integrity of the transmission channel. To give the divided and reconstructed data in a suitable way. Another application is pure signal processing, where it is often necessary to normalize a numerical table representing the sampled signal in order to maintain a good level of accuracy throughout the signal processing task. Such normalization occurs during floating point arithmetic. Normally, a normalized number such as a mantissa has its sign bit in the most significant bit (msb) position and the complement of the sign bit in the next lower position (S, not (S), X, Y, ..., Z format). The unnormalized mantissa has one or more sign bits from its most significant digit to its least significant digit (S, S, ..., not (S),
X, Y, ..., Z formats). Normalization is based on "S, not
Find the bit position of the (S) "column (commonly referred to as exponent calculation) and typically involve shifting the" S, not (S) "column to the most significant bit. Often, the mantissa value msb is not the same as the data word msb containing the mantissa. For example, in a 40-bit data word, the mantissa msb, or normalized sign bit, is bit 31. The remaining bits serve as overflow bits during floating point operations. Thus, even with a normalized mantissa, there can be a sequence of sign bits from the data word msb to the mantissa msb.

[0004] It is known to implement bit processing techniques in software or hardware. Software implementations generally have slow performance and large code size. Hardware implementations are generally inflexible, with different processor devices physically located, for example, one for fixed-point modules and another for floating-point modules. In addition, the bit field extraction or expansion function
The bit to be extracted is the data source,
It is implemented in a limited way that requires it to be in a contiguous area of memory. This is because known bit field extraction or expansion functions utilize shifters in combination with mask logic. Furthermore, the shifter is limited to performing only bit field extraction or expansion functions, and cannot be used in parallel with other tasks.

The purpose of the present invention is, for example, not exclusively,
It is an object of the present invention to provide a bit field processor directed at improving the performance of a processing engine such as a digital signal processor.

[0006]

SUMMARY OF THE INVENTION Particular and preferred features of the invention are set forth in the accompanying independent and dependent claims. Combinations of functions from the dependent claims are a proper combination of the features of the independent claims and are not expressly recited in the claims.

According to a first aspect of the present invention, there is provided an execution apparatus for a processing machine including a first circuit adapted to obtain an intermediate signal input. It may also be another circuit for receiving and manipulating the intermediate signal and / or receiving and manipulating a signal related to the input signal according to the intermediate signal to provide another signal derived from the input signal and / or the related signal. Also have.

In a first embodiment according to the invention, another circuit is operable with the first circuit to form a composite bit counter and to process the intermediate signal to provide a bit count of the input signal. Including circuits.

According to a second embodiment of the invention, another circuit comprises:
A circuit operable with the first circuit to form a composite bit extraction circuit and includes a circuit utilizing the intermediate signal to provide a bit string extracted from the related signal according to the input signal.

According to a third embodiment of the invention, another circuit comprises:
And a circuit operable with said circuit to form a composite bit expansion circuit. Using the intermediate signal, a bit string developed from the related signal according to the input signal is provided.

According to a fourth embodiment of the invention, another circuit comprises:
A tail sub-circuit operable with the first circuit to form a composite index counting circuit and to provide a shift value using the intermediate signal to normalize an input signal.

The above embodiments according to the present invention may be provided together in any combination of two or more embodiments. The advantage of such a combination is that a common architecture is provided for the bit processing functions typically required for signal processing applications. In particular, the bit count circuit, the bit field extraction and bit field expansion circuit, and the exponent count circuit are first or head portions that generate signals usable by separate intrinsic circuits for performing separate signal processing functions. They may be combined into a common architecture sharing circuits. Such an architecture effectively reduces the surface area required by signal processing functions on an integrated circuit, thus reducing the cost of the integrated circuit or providing an opportunity to mount another circuit and function on the integrated circuit. .

In addition, the common architecture supports bit field extraction and decompression of non-adjacent bits, for example, bits from non-adjacent locations in the accumulator register. Further, the common architecture provides for single cycle operation within the processor timing train.

Another circuit typically performs a separate circuit to perform each signal processing operation on the related signal according to the intermediate signal and / or perform each operation on the intermediate signal to obtain each signal processor result from the input signal. Included. Each of the separate circuits may be directed to one or more preferred embodiments, such as a bit expansion or extraction, bit count or exponent count circuit.

Preferably, the first circuit is adapted to obtain an intermediate signal so as to be optimally configured for use by another circuit. Further, the first circuit is adapted to manipulate a portion of the input signal, said portion preferably being dimensioned to provide an optimally configured intermediate signal. The optimal configuration is directed toward reducing the number of processing elements or gates required to implement the first and other circuits, thereby reducing the surface area required by the common architecture.

A separate portion of the first circuit and another circuit provides each composite signal processing circuit for each signal operation, wherein each composite signal processing circuit is formed non-simultaneously with the other of the composite signal processing circuits. . Thus, the common architecture is configured to operate in parallel, thereby providing enhanced operating speed or simultaneous composite signal processing circuitry.

Typically, the first circuit operates to determine the number of occurrences of the data attribute for each portion of the input signal, where the input signal generally comprises a binary sequence (bits). Suitably, each part includes a group of bits. The data attribute of the input signal containing the binary sequence is one of "set" or "not set".

Since the signal processing function generally requires knowledge of the number of bits in the input signal or portions of the input signal to perform the function, it is advantageous to provide a first circuit that performs a "bit" count. It is. Thus, the bit count circuit provides a suitable head portion or first circuit of a common architecture for signal processing functions.

Generally, the first stage of the first circuit includes a digital counter each associated with a respective portion of the input signal and provides an output indicative of the number of occurrences of the data attribute of the relevant portion.

Each part typically includes a group of four bits, and the digital counter includes four inputs. In the preferred embodiment, the digital counter is "4 to 2 (four into tw
o) Includes a counter.

A suitable first stage configuration is a reduction tree for obtaining a bit count of the input signal.
And the second stage of the first circuit is suitably configured as the second stage of a reduced tree for obtaining the bit count of the input signal. In a preferred embodiment,
The second stage provides an intermediate signal.

Generally, the second stage outputs a signal representing the bit count of two adjacent portions of the input signal.

According to a first embodiment of the present invention, the tail subcircuit can be configured as a reduced tree that receives the intermediate signal from the second stage and provides a bit count of the input signal. The reduced tree has a well-known configuration such as “Wallac
e-like) "is advantageously a reduced tree. Preferably, the intermediate signal contains a classically coded bit count for each adjacent part.

According to a second embodiment of the present invention, another circuit divides the related signal and the input signal into corresponding groups and shifts bits located in the related signal group to positions determined by the corresponding input signal group. Includes shifting device. Another circuit further includes a device for receiving a signal corresponding to the signal from the divider including the shifted bits and manipulating the signal according to a control signal derived from the intermediate signal. The device receiving the signal operates a larger group of signals than the splitting device, and shifts the bits located in the signal to positions determined by the control signal. Thus, subsequent stages of another circuit operate on groups of bits corresponding to larger portions or groups of the input signal.

[0025] Preferably, the further circuit includes a further device for reception, which operates on signals from the receiving device in a larger group and converts the bits located in the signal from the receiving device. A shift is made to a position determined by another control signal obtained from the intermediate signal.

The dividing device is an encoder, a receiving device,
And a separate receiving device including a multiplexor. The input signal includes a bit mask identifying the bits to be extracted from the relevant signal.

In a third embodiment of the invention, another circuit includes an apparatus for distributing bits from the relevant signal to bit positions in at least two groups of bits determined by a control signal derived from the intermediate signal. Another circuit also includes a device for distributing bits of the distribution bits to bit positions in a smaller group of bits determined by another control signal derived from the intermediate signal. Finally, another circuit distributes the bits of the signal corresponding to the distribution bits from the apparatus for distributing to bit positions in a smaller group determined by the input signal or the control signal obtained from the mask. including.

The device for distributing bits from the relevant signal and the device for distributing the bits of the distribution bits are suitably included in a multiplexer, and another device for distribution includes an encoder.

In a fourth embodiment according to the invention, another circuit receives each part of the input signal and provides a shift value for normalization of the input signal which is controllable by the signal obtained from each part of the intermediate signal. A tail subcircuit including each processing unit is included.

An embodiment according to the present invention helps reduce the surface area required to provide a circuit that performs signal processing functions. Thus, other functions may be included in a processor, digital signal processor, or integrated circuit that embodies the invention. This makes embodiments of the invention particularly suitable for portable devices such as wireless communication devices that require maximum functionality with a minimum surface area.

A particularly useful use of an embodiment according to the present invention is
A display for inputting data into the communication device, a user interface including a keypad or keyboard, a transceiver and an antenna operatively coupled to the transceiver, and an execution device or processor as described above, or a processor, a digital signal processor or the implementation A wireless communication device including an integrated circuit including the device.

[0032]

DETAILED DESCRIPTION OF THE INVENTION The present invention finds particular application, for example, in digital signal processors (DSPs) implemented in application specific integrated circuits (ASICs), but finds application in other types of processing engines. .

The basic architecture of an example of a processor according to the present invention will now be described.

FIG. 1 is a block diagram of a microprocessor 10 having an embodiment of the present invention. Microprocessor 10 is a digital signal processor ("DSP"). For clarity, FIG. 1 illustrates only those portions of the microprocessor 10 that are appropriate for understanding embodiments of the present invention.
Details of the general structure of a DSP are known and can be readily found elsewhere. For example, US Pat. No. 5,072,418 issued to Frederick Boutard et al. Describes a DSP in detail and is incorporated herein by reference. U.S. Pat. No. 5,329,471 issued to Gray Swoboda et al. Describes in detail how to test and emulate a DSP and is incorporated herein by reference. The details of portions of microprocessor 10 that are relevant to embodiments of the present invention are described in sufficient detail below to make the present invention available to those of ordinary skill in the microprocessor arts.

Some exemplary systems that benefit from features of the present invention are described in US Pat. No. 5,072,418, which is incorporated herein by reference, and in particular, US Pat. No. 5,072,418.
See FIGS. 2-18 at 418. The system described in U.S. Pat. No. 5,072,418 can be further improved using a microprocessor including features of the present invention for improved performance or reduced cost. The systems include, but are not limited to, industrial process control, automotive systems, motor control, robot control systems, satellite telecommunications systems, echo suppression systems, modems, video imaging systems, voice recognition systems, encrypted vocoder modem systems. And so on.

A description of the various architectural features and a complete instruction set for the microprocessor of FIG. 1 is provided in co-pending US application Ser. No. 09 / 410,977 (TI-28433), which is hereby incorporated by reference. Included in the book.

FIG. 1 is a schematic overview of a processor 10 forming an exemplary embodiment of the present invention. Processor 10 includes a processing engine 100 and a processor backplane 20. In this embodiment, the processor is an application special integrated circuit (A
1 is a digital signal processor 10 mounted on an SIC.

As shown in FIG. 1, the processing engine 100
Forms a central processing unit (CPU) having a processing core 102 and a memory interface or management device 104 that interfaces the processing core 102 with a memory device external to the processing core 102.

The processor backplane 20 includes a backplane bus 22 to which the processor engine memory management unit 104 is connected. The instruction cache memory, peripheral devices 26 and external interface 28 are also connected to the backplane bus 22.

In other embodiments, it will be appreciated that the invention can be implemented using different configurations and / or different technologies. For example, processing engine 100 can separate processor backplane 20 therefrom to form processor 10. The processing engine 100 may be, for example, a DSP mounted separately from the backplane 20, which supports the backplane bus 22, peripheral and external interfaces. The processing engine 100 can be, for example, a macro processor instead of a DSP.
It can be implemented by a technology other than the C technology. A processing engine or a processor that includes a processing engine can be implemented on one or more integrated circuits.

FIG. 2 illustrates the basic structure of an embodiment of the processing core 102. As shown, the processing core 102 has four elements: an instruction buffer device (I device) 106 and 3.
Execution devices. The execution unit executes the instructions decoded from the instruction buffer unit (I unit) 106, controls and monitors the program flow, a program flow unit (P unit) 108, an address / data flow unit (A unit) 110 and data. A computing device (D device) 112.

FIG. 3 shows the P device 108, A of the processing core 102.
The device 110 and the D device 112 are shown in detail, and a bus structure for connecting various elements of the processing core 102 is shown. P device 1
08 includes, for example, a loop control circuit, a GoTo / Branch control circuit, and various registers for controlling and monitoring the program flow such as a repetition counter register, an interrupt mask, a flag or a vector register. The P device 108 includes general-purpose data write buses (EB, FB) 130, 132,
It is coupled to data read buses (CB, DB) 134, 136 and an address constant bus (KAB) 142. In addition, P device 108 communicates with A device 110 and D device 1 via various buses labeled CSR, ACB, and RGD.
12 are coupled to sub-devices.

As shown in FIG. 3, in this embodiment, the A device 1
Reference numeral 10 denotes a register file 30, a data address generator (DAGEN) 32 and an arithmetic logic unit (ALU).
34. The A device register file 30 includes various registers, including a 16-bit pointer register (AR0-AR7) and a data register (DR0-DR3) which is also used for address generation together with data flow.
There is. In addition, the register file contains a 16-bit circular buffer register and a 7-bit data page register. General-purpose bus (EB, FB, CB, DB) 1
Along with 30, 132, 134 and 136, a data constant bus 140 and an address constant bus 142 are coupled to the A device register file 30. A device register file 3
0 is a unidirectional bus 144 and 1 operating in opposite directions, respectively.
46 is coupled to the A-device DAGEN device 32. D
AGEN unit 32 includes, for example, a 16-bit X / Y register and a coefficient and stack pointer register that control and monitor address generation in the processing engine.

The A unit 110 performs addition, subtraction, and AN
Also includes ALU 34 that includes shifter functions along with functions normally associated with ALUs such as D, OR and XOR logical operators. The ALU 34 is also a general-purpose bus (EB, DB) 130, 13
6 and an instruction constant data bus (KDB) 140. The A unit ALU is coupled by a PDA bus to the P unit 108 to receive register constants from the P unit 108 register file. ALU 34 is also coupled to A-device register file 30 by buses RGA and RGB to receive address and data register constants, and transfers address and data registers of register file 30 by bus RGD.

As shown, the D unit 112 comprises a D unit register file 36, a D unit ALU 38, a D unit shifter 40 and two multiply and accumulate units (MAC).
1, MAC2) 42 and 44. The D device register file 36, the D device ALU 38, and the D device shifter 40 are buses (EB, FB, CB, DB, and KDB) 130, 1
32, 134, 136 and 140, the MAC devices 42 and 44 have buses (CB, DB, KDB) 134, 1
36, 140 and a data read bus (BB) 144. The D device register file 36 has 40 bits.
It includes an accumulator (AC0-AC3) and a 16-bit transfer register. D-device 112 can use the 16-bit pointer and data registers of A-device 110 as source or destination registers in addition to the 40-bit accumulator. The D device register file 36 stores the accumulator write bus (ACW0, AW0).
CW1) D unit ALU38 and M through 146, 148
D device shifter 40 from AC1 & 2/42, 44 and through accumulator write bus (ACW1) 148
Receive data from Data is passed from the D-device register file accumulator through the accumulator read buses (ACR0, ACR1) 150, 152 to the D-device ALU 38, D-device shifter 40 and MAC1 & 2/4.
2, 44. The D-device ALU 38 and D-device shifter 40 are also coupled to the sub-devices of A-device 108 via various buses labeled EFC, DRB, DR2, and ACB.

Referring now to FIG. 4, an instruction buffer unit 106 including a 32-word instruction buffer queue (IBQ) 502 is illustrated. The IBQ 502 includes a 32 × 16-bit register 504 logically divided into 8-bit bytes 506. The instruction is a 32-bit program
Arrives at the IBQ 502 via the bus (PB) 122.
The instruction is a local write program counter (LWPC) 5
Fetched to the location indicated by 32 in a 32-bit cycle. The LWPC 532 is included in a register arranged in the P device 108. The P unit 108 also includes a local read program counter (LRPC) 536 register, a write program counter (WPC) 530, and a read program counter (RPC) 534 register. LRPC 536 is the IBQ 502 of the next instruction or multiple instructions to be loaded into instruction decoders 512 and 514.
Indicate the middle position. That is, LRPC 534 indicates to decoders 512 and 514 the position in IBQ 502 of the instruction currently dispatched. WPC points to the address in program memory at the start of the next 4 bytes following the instruction code in the pipeline. For each fetch to IBQ, the next four bytes from program memory are fetched regardless of instruction boundaries. RPC534
Indicates the address in program memory of the instruction currently dispatched to the decoder 512/514.

The instructions are formed of 48-bit words and are routed through multiplexers 520 and 521 to a 48-bit bus 516.
Through to the instruction decoders 512, 514.
The instructions may be formed from words containing more than 48 bits,
It will be apparent to one skilled in the art that the present invention is not limited to the specific embodiments described above.

The bus 516 can load up to two instructions, one per decoder, at any one instruction cycle. The combination of instructions may be in any combination of formats that fit on a 48-bit bus, 8, 16, 24, 32, 40 and 48 bits. If only one instruction is loaded in one cycle, decoders 1 and 512
Is loaded in preference to Each instruction is executed and transferred to each functional unit to access the data on which the instruction or operation is to be performed. Instructions are aligned on byte boundaries before being passed to the instruction decoder. Matching is performed based on the format obtained from the previous instruction at the time of decoding. The multiplexing associated with instruction alignment by byte boundaries is performed in multiplexers 520 and 521.

The processor core 102 executes instructions through a seven stage pipeline, each stage of which is described below with reference to FIG.

The first stage of the pipeline is the PRE-FETCH (P0) stage 202, which is the memory interface or address bus (PAB) 118 of the memory management unit 104.
Asserting the above address causes the next program memory location to be addressed.

In the next stage, FETCH (P1) stage 204, the program memory is read and I-device 106 is filled from memory management device 104 via PB device 122.

During the PRE-FETCH and FETCH stages, the pipeline is interruptible and breaks the continuous program flow; for example, the PRE-FETCH and FETCH stages are pipelined in that they point to other instructions in program memory for branch instructions. Separated from the rest of the column.

The next instruction in the instruction buffer then goes to the third
Stage, DECODE (P2) 206, dispatches to decoders 512/514, where the instruction is executed by an execution device, such as P device 108, A device 110 or D device 11
Decoded to 2 and dispatched. Decoding stage 20
6 includes decoding of at least a part of the instruction including a first part indicating the type of the instruction, a second part indicating the format of the instruction, and a third part indicating the addressing mode of the instruction.

The next stage is the ADDRESS (P3) stage 208, where the address of the data to be used for the instruction is calculated or, if the instruction requires a program branch or jump, a new program address. Is calculated. Each calculation occurs in the A device 110 or the P device 108, respectively.

In the ACCESS (P4) stage 210, the address of the read operand is output, and the memory / address where the address was generated by the DAGEN X operator in the Xmem indirect addressing mode.
X memory with indirectly addressed operands (Xmem)
READ from.

The next stage in the pipeline is the READ (P5) stage 21
At 2, the memory operand of the address generated by the DAGEN Y operator in the Ymem indirect addressing mode or the DAGEN C operator in the coefficient address mode is read. The address of the memory location where the result of the instruction is to be written is output.

Finally, if the instruction is A-device 110 or D-device 1
There is an execution EXEC (P6) stage 214 that is executed in either of the two. The result is then stored in a data register or accumulator, or written to memory for a Read / Modify / Write or Store instruction. Further, a shift operation is performed on the data in the accumulator during the EXEC stage.

The basic operation principle of the pipeline processor will be described below with reference to FIG. As can be seen from FIG. 6, the first instruction 302, the pipeline stages for successive occurs on time T ₁ -T _7. Each time period is a processor
This is the clock cycle of the machine clock. Since the previous instruction is moved to the next pipeline stage now, the second instruction 304 may periodically T ₂ enters the pipeline. For instructions 3 and 306, PRE-FETCH stage 20
2 generates the time period T _3. As can be seen from FIG.
In the stage pipeline, a total of seven instructions are processed simultaneously.
FIG. 6 shows the time period T for all seven instructions 302-314.
₇ indicates that everything is processed. Such a structure adds a form of parallelism to instruction processing.

As shown in FIG. 7, the embodiment of the present invention
External memory device (not shown) via bit address bus 114 and bidirectional 16-bit data bus 116
And a memory management device 104 coupled to the Further, the memory management device 104 has a 24-bit address bus 11
It is coupled to a program storage memory (not shown) via an 8- and 32-bit bidirectional data bus 120. The memory manager 104 also communicates with the machine processor core 1 via a 32-bit program read bus (PB) 122.
02 is also coupled to the I-device 106. P device 108, A
Device 110 and D device 112 are coupled to memory management device 104 via a data read and data write bus and a corresponding address bus. P unit 108 is further coupled to program address bus 128.

In particular, the P unit 108 has a 24-bit program address bus 128, two 16-bit data write buses (EB, FB) 130, 132, and two 16-bit data read buses (CB, DB). ) 134,
136 is coupled to the memory management device 104. The A device 110 has two 24-bit data write address buses (EAB, FAB) 160, 162, two 16-bit data write buses (EB, FB) 130, 132,
Three data read address buses (BAB, CAB, D
AB) 164, 166, 168 and two 16-bit
It is coupled to the memory management device 104 via data read buses (CB, DB) 134, 136. D unit 112 has two 16-bit data write buses (EB, FB) 1
30, 132, and three data read buses (BB, C
B, DB) 144, 134, 136.

FIG. 7 shows, for example, in order to transfer a branch instruction.
The transfer of an instruction from the I device 106 to the P device 108 is represented by 124. Further, FIG. 7 shows I-device 1 at 126 and 128, respectively.
06 indicates the transfer of data to the A device 110 and the D device 112.

FIG. 8 shows a more detailed block diagram of the D device shifter 40 described above with reference to FIG. The core of the D-device shifter 40 is a bit-processing device 802, which includes various functional devices that provide data processing and means for computing and / or monitoring bit fields. In a specific embodiment according to the present invention, bit processing unit 802 determines the exponent value of the floating point operation and counts occurrences of a particular data attribute, such as a "set" or "unset" number of data fields. Indexing / counting device 804. Bit processing unit 802 also includes a bit field processor 806 that processes the data fields to perform bit expansion and bit extraction operations.

The bit processing device 802 also includes a shifter 80
8, also includes a rounding and saturation unit 810 and a sign extension unit 812.

A shifter 808, a rounding and saturating device 810,
Since the sign extension device 812 is not relevant to the present invention, no further reference is made except for an aside.

The D device shifter 40 is coupled to various buses as described above with reference to FIG. Of these buses, the D-device bit accumulator read bus ACR0
/ 150 and ACR1 / 152 are index / counters 80
4 In the particular embodiment shown in FIG. 8, the exponent / counter 804 and ACR1 / 152 are coupled to a bit field processor 806 to provide a "source" data word. Optionally, read bus ACR
0/150 alone or with ACR1 / 152 may be coupled to bit field processor 806.

The output 818 of the exponent counting device 804 is connected to the tri-state buffer 814 and the 16-bit bus 81.
6 to the data register DRX of the A device register file 30. Output 820 is also coupled to shifter 808, where it is selected as a control signal for shifter 808.

As described above, the bit field processor unit 806 has a data read bus ACR1 / 15.
2 has an input coupled to it. Device 806 has another input coupled to the 16-bit constant data bus 140 (K bus) to provide a "mask" word to bit field processor 802. The output 822 of the bit field processor 802 is a tri-state buffer 824
And 40-bit accumulator write bus ACW1 / 1
D-device 40-bit register file 36 via 48
Is transferred to the register.

The bit processing unit 802 has a status register 85
It is partially controlled by the state and control signals received from a portion of Oa. The result of the operation performed by bit processor 802 is partially stored in part of state register 850b. For example, the least significant bit (LSB) of the bit count value generated by the count instruction is stored in test / control bit TCx of status register 850b. This allows the program to execute conditional instructions based on the parity of the bit count.

According to a particular embodiment of the invention, the exponent / counter 804 and the bit field processor 80
6 share a common circuit with a common utility. Therefore, the area of silicon occupied by these devices can be reduced. A schematic diagram of a specific embodiment utilizing a shared circuit is illustrated in FIG.

The exponent / counter 804 includes a bit counter 902 and an exponent circuit 904. The bit field processor 806 includes a bit expansion circuit 906 and a bit extraction circuit 908. A 40-bit data word from bus 910 can be source 1 for both bit counter 902 and exponent circuit 904, and a 16-bit mask 9
12 can also be an input to bit counter 902. Bit field count 914 is the bit counter 9
Exponent part 904, bit expansion 906 and extraction 908 from 02
It is output to the device and used for these functions. Bit expansion 906 and bit extraction 908 are shared data bus 916
Has a 16 bit source 2 input from Bit counter 902 includes a number of stages, the first of which directly manipulates source 1 or the mask, with subsequent stages affecting the results of the previous stage. The result of one or more stages is an exponent 904, bit expansion 9
06 and extraction 908 devices.

In order to better understand the present invention, the operating principle of each of the devices 902, 904, 906 and 908 will be described below.

The bit counter 902 may be a source data word, such as a 40 bit source 1 data word, having a particular data attribute such as "set" or "non-set", or the number of bits in a 16-bit mask. Count. The result of the count is returned to the A-device register file 30 via the bus 816 labeled EFC in FIG.

The bit field extraction and expansion functions will now be described with reference to FIGS. 10A and 10B. bit·
For field extraction, the bits in mask 912
Extract bits from source 2/916 using pattern. In the embodiment illustrated in FIG. 10A, the “set” bit at the bit position in the mask 912 causes the source 2/9
The correspondingly located bit in 16 is "packed" into the next available bit position in destination register 1002. Thus, the first "set" bit 1004a of the mask 912 causes the "non-set" bit 1
006a is located at the first available bit position 1008a of destination register 1002. Group 1004 of “set” bits in mask 912 is source 2
/ 916 bit corresponding to bit position 1008 of destination register 1002
Is extracted. In addition, the “set” bit 1010 at bit position 14 of mask 912 is the position 1 of source 2/916
4 bit 1012 is extracted and the next available bit position 1014 of the destination register 1002 is extracted.
To "pack" this. In this way, certain individual or groups of bits can be extracted from a data word. The extract function is particularly useful, for example, for extracting flags from a status register. In addition, the extraction function can be used for deinterleaving and error correction decoding of data frames, especially for mobile communication applications.

The expansion function is considered to be the reverse of the extraction function, and vice versa, and will be described below with reference to FIG. 10B. In this embodiment, the “set” bit of mask 912 is the destination register 1002 corresponding to the bit position of mask 912 for data word source 2/916.
"Pack" the next available bit in the bit position of lsb → msb. Thus, the "set" bit 1016a of the mask 912 takes the first bit 1018a of the source 2/916 and places it at the location 1020a of the destination register 1002. Similarly, group 1016 of masks 912 is grouped from source 2/916 to group 101
8 in the destination register 102
0 in the group 1020. "Set" bit 1022
Is the next available bit 1024 of source 2/916
To the destination register 1002
At the corresponding bit position 1026. Thus, bits are taken from a data word and placed at target bit positions to form an object. Such a function is useful when interleaving data frames in a mobile communication system.

In the above description, the default bit value is 0 or “not set”. However, as will be apparent to those skilled in the art, the default value is 1 or "set".
Is also possible. In addition, the “active” bit value is 0
It is also possible that it is not 1. The embodiment of the present invention is 16
Mask, source and destination
It is not limited to a register or a word, and may include other appropriate bit lengths.

The index device 904 performs what is known as "index calculation", and its operation is described below with reference to FIGS. 11A and 11B. This is an important part of normalizing the mantissa of a floating-point number after an operation is performed, for example, in floating-point arithmetic.

Referring to FIG. 11A, the mantissa of a floating point number is shown labeled 1102. The mantissa 1102 is not normalized, and in certain embodiments of the present invention, S, S,... S, notS, as shown in FIG.
Indicated by the presence of one or more sign bits “S” 1104 in the form of X, Y,... Z from the most significant bit to the least significant bit, where the not sign (notS) 1106 is Indicates transition to a mantissa value. In certain embodiments, normalization is known as an exponential calculation, "S"
Scan the mantissa to find the bit position of the "notS" column 1108, shift this column to the most significant bit of the mantissa,
Updating the exponent value to the corresponding shift value. This means that the most significant bits of the normalized mantissa 1110 are “S”, “no”
This results in the format illustrated in FIG. Although the normalized mantissa is shown as having a sign bit at the bit position corresponding to the msb of the data word containing the mantissa, this is not always necessary. The data word may include more bits than required for the mantissa value, and the mantissa msb, or sign bit, may be in a location other than the data word msb. In the preferred embodiment, the exponent unit 904 performs the exponent calculation element of the normalization, passes the shift value to the shifter 808 to shift the mantissa, and passes it to the 16-bit A unit data register DRx located in the A unit register file 30. , Where it is stored as an exponent value. The corresponding shifted mantissa is stored in a 40-bit D-device accumulator ACx.

Returning to FIG. 12, a more detailed description of the common circuit including the bit counter 902 and the counting circuit according to a preferred embodiment of the present invention is provided. FIG. 12 is divided into two parts of FIG. 12A and FIG. 12B and divided and connected on a line AA ′ for easy observation.

As shown in FIG. 12, the circuit of the preferred embodiment is divided into four stages 1202, 1206 and 1208, with stage 1208 being the tail circuit of that portion of bit counter 902 which provides the result of the bit counter.

Source 1 data word 910 is a 40-bit or 16-bit word. However, in the example shown in FIG. 12, a 40-bit word is input to the bit counter 902. The source data word is the first stage 120 of the common circuit.
2 is input to the counter set 1210 (a-j).
Each counter 1210 (a-j) is a "4 into 2 with carry out" counter having a two bit output and a four bit input for the carry bit. The source data words are divided into groups of 4 bits, each group being input to a respective counter 1210. Counters 1210 are logically grouped into pairs, with adjacent groups of bits being input to adjacent pairs of counters.

The counters and bit groups are paired as shown in Table 1 below.

[Table 1]

Certain outputs of the counter 1210 are input to a second stage 1206 of the common circuit, some forming outputs N1 of other devices of the bit field processor 802. The second stage 1206 consists of “3 into 2”
It includes five counters 1212 (ae) which are counters. Each counter 1212 (ae) receives the same input from the two associated counters in the first stage 1202, and
Give output representing the field. The operation of counters 1210a and 1210b related to counter 1212a is
A set of related counters of 202 and stage 1206, ie, 12
1210c and 1210d, 1212c related to 12b
The operations of 1210e and 1210f related to the above and 1210g and 1210h related to the 1212d and 1210i and 1210j related to the 1212e will be described below as examples.

The carry outputs (1214, 1216) of the counters 1210a and 1210b are output together with the most significant bit (msb) 1218 of the counter 1210a.
is input to a. The carry output of counter 1210b also forms an output N1 with the result (1222, 1224) of counter 1210b.

The other counters 1210 in the first stage 1202 are likewise coupled to the respective counters 1212 in the second stage 1206. Further, a counter 1210d including a carry output
Form the second stage output N0.

The result of the counter 1212a (1228, 1
230) is input to a 4-bit adder 1226a, which is the 4-bit adder 1 of the second stage 1206 of the common circuit.
226. The output msb 1228 is input to bit position 2 and the lsb 1230 is input to bit position 1 to provide msb 12 from the counter 1210b of the first stage 1202.
It is added to 22 outputs. Lsb12 of counter 1210a
20 is the bit position 0 of the adder 1226a and the counter 12
It is added to lsb 1224 of 10b. First and second stage 1
202, its associated counters 1210 and 121 at 1206
The corresponding inputs from 2 are adders 1226b, 1226c,
Performed at 1226d and 1226e.

The operation of stage 1202 in accordance with the preferred embodiment is described below with reference to Table 2, which shows that the Sum and C0 outputs are set when the input includes one or three "set" bits. As described above, one of the counters 1210 (a-j) including the Sum (S) output and the two carry outputs C and C0.
FIG. Each counter 1210 (a-j) scans a 4-bit field and encodes the result as shown in Table 2.

[Table 2]

Stage 1202 operates as the first stage of a "wallace-like" reduction tree to obtain a bit count of an 8-bit field. Each output N0 and N1 of stage 1202 above is in accordance with Table 2 and is a 4-bit field 3: 0 and 1
Represents the number of 1: 8 set bits (1).

Stage 1206 is used to obtain a bit count for an 8-bit field. In this regard, counters 1212 (a-e) add 8 to the sum performed by adders 1226 (a-e) in stage 1206, based on the output of counter 1210 paired by each 8-bit field. Includes the final stage of the "Wallace-like" reduction tree used to reduce each bit field.

The 4-bit output from each adder 1226 is transferred to the last bit counter stage 1208, where
The output (NNO) of 26b is also the exponent part 904 and the expansion 90
6 and provided for use by other devices such as the extraction 908 device. The output NN0 of stage 1206 is a "classically" coded binary field that represents the number of set bits (1) of the 8-bit field formed from bits 7: 0 of the source data word. In the preferred embodiment, stage 1208 is a "wallace-like" reduced tree and stage 120
Take the intermediate 8-bit field bit count from 6 as input and get the final bit count on all input words from the source.

In the preferred embodiment, the counting stage 1208
Are four “with 4 to 2 carry output” counters 1232
(Ad), the four least significant adders 1212a, 1212b, 1212c and 1212 of the second stage 1206
Receive input from d. Adder 1 to counter 1232
The distribution of outputs from 212 (ad) is expanded in Table 3.

[Table 3]

In the preferred embodiment, bit count stage 1
208 is another group of counters, in this example "3 into 2 (3 into 2)
2) "includes the counters 1234 (ae). Counter 1
234 is coupled to the counter 1232 and the adder 1226e of the second stage 1206 of the common circuit according to Table 4 below, where each of C, S and Co is the sum (Sum) shown in FIG.
It corresponds to the first carry output and the second carry output CO.

[Table 4]

The unused input is set to 0 and the counter 1
"Carry out" C for 232b, 1232c and 1232d
It should be noted that O is input to the "carry input" of counters 1232a, 1232b and 1232c, respectively.

The last stage of the bit count stage 1208 is 5
It includes a bit adder 1236, which provides the five most significant bits of the bit count result. The bit count result lsb is the lsb output from the counter 1234e. 12
The msb of 34e is added to the lsb of 1234d at bit position 1 and the msb of 1234d is the lsb of 1234c at bit position 2.
And the msb of 1234c is 123 at bit position 3.
4b is added to the lsb of 1b, and the msb of 1234b is
Is added to the lsb of 1234a, and the msb of 1234a is added to 0 at bit position 5.

Bits are set in bit groups 15:12 and 11: 8 and a bit counter 90 is set for a 40-bit data word in which all other bit positions are set to zero.
Operation example 2 will be described below.

The counters 1210a and 1210b count the number of occurrences of the "set" bit or "1" of each bit, which in this example are the counters 1210a and 1210b.
1220 and 1224 are output of 1
22 and a "carry out" 1214 and 1216 produce a zero. Set bits 1220 and 1224 are added together at bit position 0 in 4-bit adder 1226a, resulting in bit 1 of the output being set. The set bit is input to a bit of the counter 1232c, all other inputs are 0, and sets the output lsb. This is input to bit position 1 of adder 1236 which has 0 or "not set" on all other inputs. Therefore, the output of adder 1236 is 000010, which is a decimal number two.

Those skilled in the art can easily understand the operation of the counter 902 for other data words input thereto.

The bit extraction will be described below. The method of performing bit extraction according to the preferred embodiment falls under the general category of recursive sorting. In general, two consecutive bits
Fields (indicated by indexes i and i + 1,
Where i is an integer including 0) is taken from the source data word. Each field is ^2p in size, where p is a positive integer including 0. Returning now to the mask, the number of "set" bits, or "1", in bit field i of the mask is determined. This number may have a ^2p + 1 value (ie, a number in the range of 0 and ^2p ). Source i +
The bits of the first field are shifted to the i-th field of the source, shifting the bits already there according to the number of set bits found in the i-th field of the mask. For example, if n (the number of bits set to "1" in the mask field i) = 0, all bits in the (i + 1) th field are moved to the (i) th field, and a new i + 1
The bit field is filled with zeros.

This process starts from p = 0. For p = 0, the field size is 1 bit, i-th and i + 1
The ith consecutive bit field and the ith bit field mask are the source [s (i + 1), s (i)] and the mask [m
(i)]. If m (i) = 0, s (i + 1) is copied to position i, resulting in the following bit field [0, i + 1]. The generated bit field has 2 ^{p + 1} positions, and the newly shifted in bits are forced to zero.
If m (i) = 1, the generated bit field is [i + 1, i]
And remains unchanged for the source bit field. The above can be performed in parallel on an 8-bit field pair, for example on a 16-bit source.

Size 2^pFor a bit field of
After completing the above process, the next step is size 2^{p + 1}No
To process the set field. Therefore, p is
The process can be restarted, incrementing to p = 1. here
Indicates that the bit field contains two bit positions and the source
Field [s (i + 1)_msb, s (i + 1)_lsb], [S (i)_msb, s (i)_{ls b}]
And the mask field [m (i)_msb, m (i)_lsb]. 2
The bit field of bits is [0,0], [0,1] or [1,1]
It is a pair format. Therefore, the upper bits in the extraction process are
Bit to the right of the
It can be understood that it is removed. Where m (i) = 00
In contrast, the generated bit fields are [0,0, s (i + 1)], m (i)
= 01, the generated bit field is [0, s (i + 1), s
(i)_msb], M (i) = 11, [s (i + 1), s (i)]

The possible generated bit fields for each mask value are shown in Tables 5-7.

[Table 5]

[Table 6]

[Table 7]

The value of p is now incremented (p = 2) and the extraction process is restarted on the right-justified previously processed bit field according to mask m (i), as can be seen from Tables 5-7. You. The above algorithm is applied at p = 4 for a 16-bit source word. Source words containing more or less bits are processed using appropriate large or small values of p.

In the preferred embodiment described hereinafter with reference to FIG. 13, the encoder sorts the bit field in a single step for up to two p's.

The above algorithm is then followed by p = 2 to 4
Use up to. It will be apparent to those skilled in the art that p has a larger value if the source and mask include more than 16 bits.

A preferred embodiment of the extraction device 908 will be described below with reference to FIG. 13 is the bit counter 902 used by the extractor 908.
3 is a block diagram of a common circuit of FIG. Circuits specific to the extraction circuit 908 are shown on the left 1304.

In the preferred embodiment, source 2/916 is divided into four groups of four bits, each group having a
6, 1308, 1310 and 1312. Similarly, the mask 912 also includes encoders 1306, 1308, and 1
It is divided into groups of 4 bits input to 310 and 1312. The encoder relates to the bit field as follows: i relates to 1312, i + 1 relates to 1310, i + 2 relates to 1308, and i + 3 relates to 1306.

Encoders 1306, 1308, 1310
And 1312 each have a 4-bit output, of which 13
06 and 1308 are input to a first level “8 × 5 to 1” multiplexer 1314, and 1310 and 1312 are input to another first level “8 × 5 to 1” multiplexer 1316. Multiplexer 1314 is a bit counter 9
02, controlled by the output N1 from the first stage 1202,
Multiplexer 1316 is also controlled by output N0 from first stage 1202 of bit counter 902. N1 and N0 each include 3 bits and each multiplexer 1314
And 1316 decode N1 and N0 to obtain the counter 121
Obtaining the count values coded by Ob and 1210d selects and directs the multiplexer input to one of the 5 bit positions within each of the multiplexers 1314 and 1316.

The 8-bit outputs 1318 and 1320 of the multiplexers 1314 and 1316 are connected to the bit processor 9.
02 is input to a second level “16 × 9 to 1” multiplexer 1322 that can be controlled by the output NN0 of the second stage of the common circuit. Output 1324 of multiplexer 1322 provides the extracted result and is input to destination register 1326.

Referring to FIG. 14, which illustrates a truth table for a single encoder 1306 as an example of the operation of each encoder, an encoder 130 according to a preferred embodiment of the present invention is shown.
6, 1308, 1310, 1312 are given below in more detail. It should be noted that in the preferred embodiment, all encoders operate similarly. Input A receives bits from source 2/916, and input M receives bits from mask 912. S is an encoder output. As can be clearly seen from the truth table of FIG. 14, for the "set" bits in the group of bits (M0-M3) of the mask 912, the bit group (A0-A) of the source 2/916
3) The bit value from the corresponding position in the output (S0-
The next available bit position after S3) is communicated (ie, no bit value has been received from the A input).

The operation of encoder 1306 may also be expressed by the following equation:

(Equation 1)

Where the symbol "SX" represents the number of bit positions occupied by bit values from source 2/916,
That is, S3 indicates that bit 3 of the output is occupied by the bit value from source 2, while S0 is
Indicates that the input producing the least significant bit of the output is so occupied.

The multiplexers 1314 and 131 shown in FIG.
A more detailed description of the operation of 6 and 1322 is given below with reference to FIG. The first level multiprocessor, for example 1316, in this example is a pair of encoders 1310, 1
It has an 8-bit (A0-A7) input from 312 to it. Unused inputs are set to zero. Multiplexer 1
Since 316 is an “8 × 5 → 1” multiplexer, this is an 8-port 1502, each having 5 inputs (0-4).
including. The multiplexer port is controlled by three bits N0 output from the first stage 1202 of the common circuit of the bit counter 902. Encoders 1310, 13
The twelve pairs of outputs (A0-A7) are distributed to multiplexer ports 1502 as shown in FIG. The multiplexer port in the preferred embodiment is active low select, but may be active high select depending on the logic level used in other implementations.

In response to N0, a particular input is communicated to multiplexer output 1320.

First stage 1202 of bit counter 902
A similar scheme under control of the N1 output from
06, 1308 are used for the paired elements (A8-A15). In addition, a similar scheme is used for multiplexer 1322, but since this is a “16 × 9 → 1” multiplexer, for each of the 16 ports, four values are provided to provide one of nine inputs to select one of the nine inputs. Control bits are required.

The operation of the “16 × 9 → 1” multiplexer 1320 with the help of Table 8 is described below. The inputs to each port of multiplexer 1320 are labeled E0 → E8. The input of the multiplexer 1320 is A ₁₅ → A ₀
And the “Mux.” Number corresponds to the bit weight of the multiplexer output, see 1324 in FIG. “0” is associated with an unused input being forced to zero.

[Table 8]

To further understand the operation of the preferred embodiment of the bit extractor 908, the input and output values of the various elements are described for the following source data words: 1000111010001111, the mask is: 1111100000000001

For the above source and mask data words, the output from the encoder is as shown in Table 9.

[Table 9]

The outputs from the common circuit are N1 = 001 (binary) = 1 (decimal) and N0 = 001 (binary) = 1
(Decimal number).

The input to the multiplexer 1316 is 2,00.
000001 and 10000001 to the multiplexer 1314. Multiplexer 1316 is controlled by N0 = 1, provides output 1320 = 0000001,
314 is controlled by N1 = 1 and output 1318 = 0010
Give 1001. This output provides a 16-bit input to a multiplexer 1322 of the form 0011000100000001.
The multiplexer 1322 is NN0 = 00000001 (binary number)
= 1 (decimal number), output = 000000000010
Give 0011.

This output generally follows that expected from the bit extraction function described above.

A more detailed description of the bit / field expansion circuit will be given below with reference to FIG. As schematically illustrated in FIG. 16, the bit field expansion circuit includes a common circuit 1302 of the bit counter 902. The circuit specific to the deployment device 906 is labeled FIG.
6 to the left. As described above, the bit field expansion function is considered to be the reverse of the bit field extraction function. Therefore, the bit field extraction circuit 1304
First and second level multiplexers 1314, 13
16 and 1322 can be replaced by demultiplexers 1608, 1606 and 1604 for the first and second levels, respectively. The control signals of each demultiplexer are N1, N0 and NN0 outputs from the common circuit 1302,
It corresponds to the input control signal of the bit / field extraction circuit 1304. Accordingly, the propagation of bits from the source 1610 through the first and second level selectors is reversed relative to the propagation of bits between the first and second level selectors of the bit field extraction circuit 1304. .

Bit field encoder 161
2, 1614, 1616 and 1618 are encoders 1306, 1308 of the bit / field extraction circuit 1304,
1310 and 1312 operate differently. One example of the operation of each of these encoders is a single encoder 1
Referring to FIG. 17, which illustrates a truth table 612, encoders 1612, 161 according to a preferred embodiment of the present invention
4, 1616 and 1618 are described below. Input A receives bits from one of demultiplexers 1606 or 1608, and input M receives bits from mask 1622. S is an encoder output. As can be seen from the truth table of FIG. 17, the bit group (M
0-M3), the first available bit value from the bit group (A0-A3) from the demultiplexer 1608 is the output group of bits (S
0-S3) to the corresponding position, and so on for subsequent "set" bits and bit values. Output S is the destination bit such that the output of encoder 1612 is the most significant bit of the destination of the register.
The data is input to the register 1620 and the encoders 1614, 1
616 and 1618 are the destination register 16
Gives the next successive set of 20 most significant bits. Unused positions are "padded" with zeros.

The operation of encoder 1612 is also represented by the following equation:

(Equation 2)

Here, the symbol SX "is an encoder input (A)
Represents the bit position in the encoder output occupied by the bit value from the corresponding position of.

Second and first level multiplexer 16
Source 2/161 through 04, 1606 and 1608
The progression of the bits from zero can be followed by reversing the data flow with reference to the multiplexer shown in FIG. The operation of the second and first level multiplexers will be readily apparent to those having ordinary skill in the art with respect to the interoperability between the bit field extractor 1304 and bit field expander 1602 multiplexers.

Referring to FIG. 18, exponent count circuit 904
A detailed description of is given below. In the preferred embodiment of the invention, the exponent counting circuit 904 includes a bit counter 902
, And a tail portion 1802 that performs the final portion of the index calculation. FIG. 18 is divided into two pages for easy reference.

The output of stage 1206 to tail portion 1802 corresponds to a sequence of "set" bits starting at msb of the data word in source 1910. The output of stage 1206 provides a tail 1802 and an encoder select signal for selector 1814. The data word is divided into 8-bit groups,
Starting from the msb, it is coded and selected such that for each group where all bits are "set", the 8-bit offset represented by the outputs SoX and NNX is coded. For an 8-bit group where all bits are not "set", the location of the bit transition relative to the msb of the group is coded and represented by SoX and NNX for the group where the transition occurs. The selector 1814 is operated according to the algorithm and the SoX and NNX inputs and outputs a result corresponding to the bit shift required to normalize the mantissa. The algorithm can be configured to provide a bit shift for any specified normalized code position.

A more detailed description of the exponent counting circuit continues below. The tail portion of the exponent calculation 1802 comprises an encoder 1804 and four other encoders 1806, 1808, 1810 and 1812 having similar operations to each other.
And an encoder level having Encoder 18
04 is the output of the "4 to 2" counter 1210i and the source
Receive the eight most significant bits of the data word. Encoder 180
4 outputs a 6-bit result to bit position 1 of selector 1814. Encoders 1806, 1808, 1810 and 1812 each have a "4 to 2" counter 1210a, 121
Receive the output of 0c, 1210e and 1210g. Further, 1806 receives bits 15: 8 of the source data word, 1808 is bits 7: 0, 1810 is bits 3
1:24, 1812 receive bits 23:16. Each of encoders 1806, 18108, 1810 and 1812 has a bit position 9, 7, 5 and 3
Output a 6-bit result.

FIG. 19 shows a truth table of the lower half of the encoder as an example, and the encoder 180 is referred to by referring to the following equation.
The operation of No. 4 will be described below. Input A of encoder 1804 receives 8 bits from source 1/910, and input N receives 3 bits from the output of counter 1210i. So
Is the encoder output.

(Equation 3) Here, the symbol “SoX” indicates a bit position in the output of the encoder 1804.

As shown in FIG. 20, the encoders 1806, 1808,
A detailed description of the operation of 1810 and 1812 is provided below. Input A receives 8 bits, 15: 8 from source 910, and input N receives 3 bits from the output of "4 to 2" counter 1210a. So is the 6-bit encoder output. The encoder operates according to a truth table, the lower side of which is shown in FIG. 18 as an example, and the following equation:

(Equation 4) Here, the symbol “SX” identifies the bit position in the encoder output.

The selectors 1814 are also shown in FIG.
Inputs 8, 6,, labeled 0, NN1, NN2, NN3, and NN4, and corresponding to the same reference in FIG.
4, 2, 0 to 4-bit adders 1226a, 1226b,
Receive input from 1226c, 1226d and 1226e. The function of the bit exponent selector 1814 is represented by the following logical expression 15.

(Equation 5)

The 6-bit output S gives the exponent value of the data word in source 1 of FIG.

An example of an index calculation is provided below to aid in understanding and further explain the index calculation according to the preferred embodiment of the present invention. In this example, the source is source 1 shown in FIG. 9 and is a 40-bit data word having its code position at bit position 31 as indicated in Table 10. The code positions are labeled in the positive or negative direction with respect to the code bit position, bit position 31.

[Table 10]

In the example shown in Table 10, one thick line indicates the boundary of the normalized mantissa and the location of its sign bit position. As an example, the solid box indicates the position of the sign bit of the denormalized mantissa of bit 27. In this example, in order to normalize the mantissa, the sign bit must be shifted four bits to the left (in the msb direction). If the sign bit is in bit position 35 as indicated by the dashed box, it must be shifted 4 bit positions in the lsb direction.

Referring now to FIGS. 18 and 21 (selector 1814 in FIG. 18), the 4 → 2 counter, adder, encoder and selector correspond to the data words of source 1 shown in Table 10 above. It has an output as shown in FIG.

[Table 11]

From the above description, it will be apparent to those skilled in the art that various modifications can be made within the scope of the invention. For example,
The extract and expand function may be implemented by having a multiplexer tree for each bit position to be extracted. However, this requires more hardware and is slower than the particular embodiment described above.

For example, the processor 1 incorporated in an integrated circuit
One application of a processing engine, such as 0, is in a telecommunications device, for example, a mobile wireless telecommunications device. FIG. 22 illustrates an example of such a telecommunications device. In the particular example illustrated in FIG. 22, the telecommunications device is a keypad or mobile telephone 11 having an integrated user interface such as a keyboard 12 and a display 14. The display can be implemented using any suitable technology, for example a liquid crystal display or a TFT display. The processor 10 is connected to the keypad 12 via a keyboard adapter (not shown), where appropriate, and to the display 14 via a display adapter (not shown), where appropriate. A communication interface or transceiver 16 is connected to a wireless telecommunications interface including, for example, radio frequency (RF) circuits. The radio frequency circuit is included in or separated from the integrated circuit 40 that includes the processor 10. The RF circuit 16 is the antenna 1
8 is connected.

The scope of the present disclosure, whether or not it relates to the claimed invention, or alleviates any or all issues raised by this invention,
It includes a novel feature or combination of features or a generalization thereof disclosed explicitly or implicitly.

As used herein, the terms "apply,""connect," and "connection" refer to an electrical connection, including when another element is in an electrical connection. .

Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to those skilled in the art upon reference to the description. It is therefore contemplated that the appended claims will cover any such modifications of the embodiments that fall within the true scope and spirit of the invention. The following items are further disclosed with respect to the above description. (1) In a digital system having a processor, the processor receives a first circuit adapted to obtain an intermediate signal from an input signal, receives the intermediate signal, and relates the intermediate signal to the input signal according to the intermediate signal. Another circuit for manipulating a signal to generate the input signal and a further circuit for providing a final signal derived from the related signal. 2. The digital system of claim 1, wherein said first circuit is operable to determine a number of occurrences of a data attribute for each portion of said input signal. 3. The digital system of claim 2, wherein a first stage of said first circuit is associated with each portion of said input signal and provides an output indicative of said number of occurrences of said data attribute in said portion.・ Digital including counter
system. 4. The digital system of claim 3, wherein said first stage is operable as a first stage of a reduced tree to obtain a bit count of said input signal.
system. 5. The digital system of claim 4, wherein said first circuit is operable as a second stage of a reduced tree.
A digital system further comprising a second stage for obtaining a bit count of the input signal and providing the intermediate signal. 6. The digital system of claim 5, wherein the another circuit is operable with the first circuit to form a composite bit counter, process the intermediate signal and count bits of the input signal. Digital system including a tail subcircuit that provides 7. The digital system of claim 6, wherein said tail subcircuit is configurable as a reduced tree adapted to receive said intermediate signal from said second stage, said intermediate signal being associated with each of said adjacent portions. Digital counts representing each bit count of
system. 8. The digital system according to claim 1, wherein said another circuit is operable with said first circuit to form a composite bit extraction circuit, and utilizes said intermediate signal to produce said related signal according to said input signal. A digital system including a circuit for providing a bit string extracted from a digital signal. (9) In the digital system according to (8), the another circuit divides the related signal and the input signal into a corresponding group, and positions the related signal and the input signal in the related signal group to a position determined by the corresponding input signal group. Digital system that includes a device for shifting the number of bits to be shifted. (10) In the digital system according to the item (9),
The digital system further includes a device for receiving a signal corresponding to the signal from the splitting device including the shifted bits and manipulating the signal according to a control signal derived from the intermediate signal.

(11) In a digital system as set forth in claim 10, wherein said receiving device operates said signal in large groups and shifts bits located in said signal to positions determined by said control signal. system. (12) In the digital system according to (1),
A digital system operable with the first circuit to form a composite bit expansion circuit, the another circuit utilizing the intermediate signal to provide a bit string expanded from the relation signal according to the input signal. (13) In the digital system according to (12), the another circuit distributes bits from the relation signal to bit positions in at least two bit groups determined by a control signal obtained from the intermediate signal. A digital system that includes devices. 14. The digital system of claim 13, wherein said another circuit distributes the bits of said distribution bits to bit positions in a small group of bits determined by another control signal derived from said intermediate signal. Digital systems including. (15) In the digital system according to (1),
The other circuit is operable with the first circuit and forms a composite exponent counting circuit, and includes a tail portion circuit that provides a shift value for normalizing the input signal using the intermediate signal. system. 16. The digital system according to claim 15, wherein said tail portion circuit includes a processing device for receiving each portion of said input signal, said tail portion circuit being controllable by a signal obtained from each portion of said intermediate signal, and being provided with said shift value. Digital system that gives (17) In the digital system according to item 2,
A circuit operable with the first circuit to form a composite bit extraction circuit, the circuit providing a bit string extracted from the relation signal according to the input signal using the intermediate signal; A complex bit expansion circuit operable with the first circuit, forming a composite bit expansion circuit, and providing a bit string expanded from the relation signal according to the input signal using the intermediate signal; And a circuit for providing a shift value for normalizing the input signal using the intermediate signal.

(18) The digital system according to item (1) is a cellular telephone, comprising: an integrated keyboard connected to the processor via a keyboard adapter; a display connected to the processor via a display adapter; A digital system that includes a radio frequency (RF) circuit connected thereto and an antenna connected to the RF circuit. (19) The first method for obtaining the intermediate signal 818 from the input signal
An execution device 802 for a processing engine including a head partial circuit 804. The execution device also includes another circuit 806 that receives the intermediate signal and manipulates it to generate the final signal.
Other circuits are typically configured to perform one or more signal processing functions in combination with the first circuit, and typically include separate circuits for each function. The intermediate signal is configured to be usable by each of the separate circuits.

[Brief description of the drawings]

Specific embodiments according to the present invention will now be described, by way of example only, with reference to the accompanying drawings, wherein like reference numerals are used to refer to like parts unless otherwise indicated.

FIG. 1 is a schematic block diagram of a processor according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating the four main components of the core processor of FIG. 1;

FIG. 3 shows a P device, an A device, and D of the core processor of FIG. 2;
FIG. 2 is a schematic block diagram illustrating the apparatus.

FIG. 4 is a schematic diagram illustrating the operation of the I device of the core processor of FIG. 2;

FIG. 5 is a schematic diagram of a pipeline stage of the core processor of FIG. 2;

FIG. 6 is a schematic diagram of a stage of a thread in the pipeline of the processor of FIG. 1;

FIG. 7 is a schematic explanatory diagram of a processor core for describing an operation of a pipeline of the processor of FIG. 1;

8 is a more detailed block diagram of the D device shifter shown in FIG.

FIG. 9 is a block diagram of a bit processing circuit according to an embodiment of the present invention.

FIG. 10A is a schematic diagram of a Bit_Field extraction function.

FIG. 10B is a schematic diagram of a Bit_Field expansion function.

FIG. 11A is a schematic diagram of a denormalized mantissa.

FIG. 11B is a schematic diagram of a normalized mantissa.

FIG. 12A is a block diagram of a common bit processing circuit and a count circuit according to an embodiment of the present invention.

FIG. 12B is a block diagram of a common bit processing circuit and a count circuit according to an embodiment of the present invention.

FIG. 13 shows a common bit processing circuit according to an embodiment of the present invention;
FIG. 3 is a block diagram of a Bit_Field extraction circuit.

14 is a simplified diagram of the encoder of FIG. 13 and its truth table.

FIG. 15 is a schematic diagram of the operation of the first and second level selectors of FIG. 13;

FIG. 16 shows a common bit processing circuit according to an embodiment of the present invention;
FIG. 3 is a block diagram of a Bit_Field expansion circuit.

17 is a simplified diagram of the encoder of FIG. 16 and its truth table.

FIG. 18A is a block diagram of a common bit processing circuit and an exponent count circuit according to an embodiment of the present invention.

FIG. 18B is a block diagram of a common bit processing circuit and an exponent counting circuit according to an embodiment of the present invention.

19 is a simplified diagram of the first encoder of FIG. 18 and its truth table.

FIG. 20 is a simplified diagram of the second encoder of FIG. 18 and its truth table.

FIG. 21 is a block diagram of the selector of FIG. 18;

FIG. 22 is a schematic diagram of a wireless device suitable for including an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 microprocessor 100 processing engine 102 processing core 108 P device 110 A device 112 D device 40 D device shifter 802 bit processing device 804 exponent / count device 806 bit field processor 808 shifter 902 bit counter 904 exponent circuit 906 bit expansion circuit 908 bit extraction circuit 912 mask 1002 destination register

Continued on the front page (72) Inventor Emmanuel Ego Antibes, France, Beauches-Mand-Saint-Jean, 36, Le Mars de Micocoulies Ai 1 (72) Inventor Marc Koubert, France Saint-Laurente-du-Vet, Abnu-de-Plas Talks Fleuris, 1697

Claims (1)

[Claims] 1. A digital system having a processor, the processor receiving a first circuit adapted to obtain an intermediate signal from an input signal; receiving the intermediate signal; and receiving the input signal in accordance with the intermediate signal. A further circuit for manipulating signals associated with the input signal and the additional circuit for providing a final signal derived from the related signal.