JP2000284762A - Liquid crystal display device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a multi-gradation display which requires only a low power consumption, a short arithmetic calculation time, and a small circuit scale, and is, moreover, of high picture quality, by obtaining a correction amount of a voltage to be needed when a gradation display data is an intermediate value by an analog arithmetic circuit using a voltage-current characteristic of a MOS transistor. SOLUTION: A voltage, which brings a MOS transistor NREF1 into a saturated area operation and is equivalent to an input absolute value 1, is applied to a working point control terminal REF. Then, the MOS transistor NREF1 is put into a saturated area decided by a drain current flowing into the MOS transistor NREF1 by the short across the gate and the drain. And, a correction amount of a voltage required when a gradation display data is an intermediate value is determined by an arithmetic calculating circuit using a voltage-current characteristic of the MOS transistor PREF1. Therefore, an analog calculation is completed at the latest when the whole circuit is charged and a current source is stabilized, and the device requires only low power consumption, a short arithmetic calculation time, and a small scale circuit, and it is possible to realize a high quality multi-gradation display.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a liquid crystal device used as a display device of an electronic device, and further to an electronic device such as an OA device or a measuring device equipped with the liquid crystal device.

[0002]

2. Description of the Related Art In recent years, in a liquid crystal device using a simple matrix panel, a gradation method or a pulse width in which the ratio of ON data to OFF data is changed for each frame and displayed by a frame modulation method (hereinafter referred to as FRC). A gray scale method called modulation (hereinafter referred to as PWM) for displaying by changing the ratio of ON data to OFF data within a selection period is used. Pulse height modulation (hereinafter referred to as PHM) for changing the pulse height of the display data electrode as gradation display
Was also considered.

[0003]

However, the above-mentioned conventional liquid crystal device has a drawback that the image quality is degraded by the FRC flicker called flicker.
Further, PWM has a drawback that shadows called crosstalk occur and image quality deteriorates. Therefore FRC is also PWM
However, at a practical level, about 4 to 16 tones are the limits in terms of circuit scale and image quality. On the other hand, the PHM is a well-known fact that the number of gradations is not limited and can be displayed in a stepless manner and the image quality is the best. However, a tone correction operation is required, and performing a square and square root digital operation on a pixel-by-pixel basis is impractical due to the disadvantages of a large circuit scale, a large operation time, and a large power consumption. Accordingly, it is an object of the present invention to provide a realistic liquid crystal device capable of performing multi-gradation display with a simple matrix panel using PHM without causing flicker or crosstalk. Another object of the present invention is to provide an electronic device capable of displaying a natural image in which image quality degradation has been eliminated.

[0004]

According to a first aspect of the present invention, a simple matrix panel uses a one-line selection driving method, and a pulse height of a signal electrode is set to give an effective value corresponding to gradation display data to a pixel. It is characterized in that a gradation correction operation required when the gradation display data is an intermediate value (a state that is neither ON nor OFF) is obtained by an analog operation circuit utilizing the voltage-current characteristic of a MOS transistor. .

According to a second aspect of the present invention, the method of driving the liquid crystal display device according to the first aspect is a method of simultaneously selecting and driving a plurality of liquid crystal display devices.

A third aspect of the present invention is characterized in that a vector operation for driving a simple matrix panel by a plurality of simultaneous selection driving methods is performed by a vector operation of an analog charge amount held in a capacitor.

According to a fourth aspect of the present invention, a vector operation used in the driving method of the liquid crystal display device according to the second aspect is performed by a vector operation of an analog charge amount held in a capacitor.

According to a fifth aspect of the present invention, the vector operation of the analog charge amount held in the capacitors according to the third and fourth aspects is performed by using the potential difference of each capacitor as display data while maintaining the potential difference of each capacitor. It is characterized by the following.

According to a sixth aspect of the present invention, a vector operation of the amount of analog electric charge held in the capacitor according to the third and fourth aspects is performed by using the electric charge of each capacitor as display data and a total sum potential of the vector operation of the electric charge of each capacitor. Is the calculation result.

[0010]

According to the first and second aspects of the present invention, a gradation display corresponding to the pulse height is obtained by obtaining and driving a gradation correction amount by an analog arithmetic circuit utilizing a voltage-current characteristic of a MOS transistor. It can be carried out.

According to the third to sixth aspects of the present invention, the vector operation of the analog charge amount held in the capacitor is performed, so that the vector operation required by the multiple simultaneous selection driving method can be performed with the analog amount.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 is a diagram showing a front part of a first embodiment of the liquid crystal device according to the first aspect of the present invention. M
The voltage-current characteristic in the saturation region of the OS transistor is expressed by the following well-known equation.

[0014]

(Equation 1)

Here, ID is a drain current, β is a gain coefficient of a MOS transistor, VGS is a gate-source voltage, and Vth is a threshold voltage. In the present invention, the relationship between the square of the voltage and the current is used for the analog operation of the gradation correction operation of the simple matrix panel which displays the effective value response by the cumulative response effect. The following description is based on the enhancement type having a threshold voltage of 0 or more, but a depletion type having a threshold voltage of 0 or less is also applicable. Either of the Nch and the Pch of the MOS transistor may be used as long as the polarity is switched.

First, the signal flow will be described. When the display data input I1 is defined as ON being -1 and OFF being set to 1, the gradation level is processed into an absolute value and taken out from the output X1. Next, the function of each part of the circuit will be described. MO
The function of the S transistor NREF0 is to take out the threshold voltage as the potential GRAY0. This potential means 0 which is a value of an intermediate density between -1 and +1 as display data. The comparator COMPA outputs “H” of the vdd potential to the output terminal POL if the display data I1 is positive, and outputs “L” of the vss potential if the display data I1 is negative. An analog switch SWLV is connected to the X1 terminal such that either I1 or the inverted and amplified output is selected by POL and an absolute value is output.

FIG. 2 shows a main part of a first embodiment of the liquid crystal device according to the first aspect of the present invention. The three MOS transistors NREF1, NX1, and NADJ are made to have the same characteristics. MOS transistor PRE
F1 and PX1 are made to have the same characteristics. To the operating point control terminal REF, the MOS transistor NREF1 operates in the saturation region, and a voltage corresponding to the absolute value 1 of the I1 input is applied. Then, the MOS transistor PREF1 whose drain and gate are connected enters a state of a saturation region determined by a drain current flowing through NREF1 due to a short circuit between the gate and the drain. The MOS transistor PX1 has the same characteristics as PREF1 and forms a current mirror circuit. Therefore, the drain current IPX1 is equal to the drain current INREF flowing through NREF1.
Same as 1. On the other hand, the falling INX1 is determined according to the absolute value X1 of the display data input. IPX1-INX
1 is INADJ and the MOS transistor NA
Down the DJ. At that time, the voltage between the drain and source of NADJ is taken out as output ADJ.

According to the configuration described above, the document Ruckmong
athan, TN, "Addressing Technique for RMS Responding
LCDs-A Review, "Proceedings of Japan Display '92,
pp. 77-80, Oct. 1992 and Conner, ARand Schffer, TJ,
"Pulse Height Modulation (PHM) Gray Shading Method for Passive Matrix LCDs," Proc
The gradation correction calculation of gradation display shown in eedings of Japan Display '92, pp. 69-72, Oct. 1992 can be realized with a very simple circuit configuration. The principle of the gradation correction calculation for gradation display has been described in the above two documents and will not be described here.

The operation will be further described in detail.

With the MOS transistor NREF0 shown in FIG. 1, the current flowing through the MOS transistor PX1 is equal to the current flowing through the MOS transistor NREF1, and its value is expressed as follows in a saturation region current characteristic.

[0021]

(Equation 2)

The operation of the MOS transistor NX1 in the saturation region is expressed by the following equation.

[0023]

(Equation 3)

Due to this characteristic, the MOS transistor NX1
Is converted to a current INX1 which is multiplied by a coefficient and squared. When INX1 is insufficient for the intermediate display data other than +1 and −1, that is, for the current amount IPX1, the current expressed by the following equation flows through the MOS transistor NADJ.

[0025]

(Equation 4)

By substituting equations 2 and 3 into equation 4, the following equation is obtained.

[0027]

(Equation 5)

Thus, the gradation correction amount ADJ is calculated.
Since the calculation is performed with GRAY0 being offset by the transistor Vth, both the input X1 and the output ADJ are input / output based on the GRAY0 potential. The analog operation is completed until the entire circuit in which the current source is stabilized is charged. In an actual circuit, it is completed in several tens of ns. Therefore, compared to the large power consumption, long operation time, and large-scale circuit when performing the operation using digital data, much smaller power consumption, short operation time, and a small-scale circuit are required.

[Embodiment 2] FIG. 3 is a view showing a main part of a second embodiment of the liquid crystal device according to the second aspect of the present invention.

The number of simultaneous selections can be arbitrarily selected as 2, 3, 4, 5... Here, the number of simultaneous selections will be described as four.
First, the configuration will be described. MOS transistors NREF1,
Six of NX1 to NX4 and NADJ are made to have the same characteristics. In addition, MOS transistors PREF1, P
Five of X1 to X4 are made to have the same characteristics. The operating point control terminal REF has a MOS transistor N
REF1 operates in the saturation region, and the absolute value of the I1 input is 1
Apply a considerable voltage. Then, the MOS transistor PREF1 whose drain and gate are connected becomes NREF1
Into a saturated region determined by the drain current flowing through the device.
The MOS transistors PX1 to PX4 have the same characteristics as PREF1 and thus constitute a current mirror circuit. Therefore, each of the drain currents IPX1 to IPX4 is the same as the drain current INREF1 flowing through NREF1. On the other hand, the falling INX1 is determined according to the absolute value X1 of the display data input. At the same time, INX2-4 are also determined according to the absolute values X2-4 of the respective display data inputs. (IPX1 + IPX2 + IPX3 + IPX4
-INX1-INX2-INX3-INX4) flows through the MOS transistor NADJ as INADJ. At that time, the voltage between the drain and source of NADJ is taken out as output ADJ.

The former part is basically the same as that of the first embodiment. However, the number of display data inputs increases to four inputs (I1 to I4). The current flowing through the MOS transistor PX1 by the MOS transistor NREF0 shown in FIG. 1 is equal to the current flowing through the MOS transistor NREF1, and its value is expressed by the current characteristic in the saturation region as follows.

[0032]

(Equation 6)

The operation of the MOS transistors NX1 to NX4 in the saturation region is expressed by the following equation.

[0034]

(Equation 7)

[0035]

(Equation 8)

[0036]

(Equation 9)

[0037]

(Equation 10)

Due to this characteristic, the MOS transistor NX1
Gate voltages X1 to X4 are squared currents INX1
４4. When the intermediate display data other than +1 and −1, that is, INX1 to INX4 are insufficient for the current amounts IPX1 to IPX4, the current expressed by the following equation flows through the MOS transistor NADJ.

[0039]

[Equation 11]

By substituting the equations (3) and (7-9) into the equation (10), the following equation is obtained.

[0041]

(Equation 12)

Thus, the gradation correction amount ADJ is calculated.

Regardless of the number of simultaneous selections, the analog operation is completed up to the charging of the entire circuit in which the current source is stabilized. Therefore, the power consumption when calculating with digital data is large.
Compared to long operation time and large-scale circuits, much lower power consumption, short operation time and small-scale circuits are required.

[Embodiment 3] FIG. 4 is a view showing a main part of a third embodiment of the liquid crystal device according to the present invention.

The number of simultaneous selections can be arbitrarily selected from 2, 3, 4, 5....
The actual circuit changes the state of FIG.
The state is switched by the analog switch. 1
As an example, FIG. 7 shows a part of a connection example of the analog switch SWLV. In order to explain the function, the analog switch is omitted in FIGS. 4 and 5 because it is complicated, and only the connection in each state is shown. FIG. 4 shows a state in which the capacitors C1 to C4 store the absolute value charges Q1 to Q4 corresponding to the display data (+1 to -1). C1 to C4 and CADJ are created with the same capacity (c [F]). Several p in actual IC
F to several hundred fF is realistic, but the capacitance value may be determined in a slightly wider range depending on the specifications of the liquid crystal device to be applied and the characteristics of elements such as ICs. The polarity of the display data is reflected in the multiplication vector. Each CADJ stores a gradation correction calculation result as a charge QADJ. The connection state is changed to the connection state shown in FIG. FIG. 5 shows an embodiment of the liquid crystal device according to the fifth aspect of the present invention. The calculation is performed while maintaining each potential. This will be described in more detail with reference to FIG. Although input terminals of X1 to X4 and ADJ shown in FIG. 4 are omitted, they are actually separated by analog switches. Vector (Q1, Q
2, Q3, Q4, QADJ) with a multiplication vector (+
1, -1, + 1, + 1, + 1). The desired result is (Q1-Q2 + Q3 + Q4 + QA
DJ). This vector operation will be described. The connection state is determined by the analog switch according to the multiplication vector. In the embodiment of FIG. 5, C1, C which are products of +1
3, C4, CADJ are stacked in the positive direction, and C2, which is the product of -1, is stacked in the negative direction. When the operation is completed, the voltage (Q1-Q2 + Q3 + Q4 + Q)
ADJ) / c is output.

More specifically, in FIG. 7, the polarity control signal CONT determines the positive or negative direction. The voltage sum that is the vector operation result is taken out as an output OUT with respect to the reference potential VC. An analog vector operation indispensable for the gradation display simultaneous selection drive can be performed in one clock. Digital computation requires much lower power consumption, shorter computation time, and smaller circuits than large power consumption, long computation time, and large-scale circuits. In addition, high-quality multi-tone display was realized.

[Embodiment 4] In the calculation according to the third aspect which does not require the gradation correction calculation, it can be realized by omitting CADJ in FIGS.

[Embodiment 5] FIG. 6 is a view showing a main part of a fifth embodiment of the liquid crystal device according to the present invention. According to a fifth aspect of the present invention, the operation while maintaining the electric charge is performed in contrast to the operation while maintaining the potential of the capacitor. The actual circuit is switched from the state of FIG. 4 to the state of FIG. 6 by an analog switch in response to a clock signal. In order to explain the function, the analog switches are complicated and omitted, and only the connection in each state is shown. FIG. 4 shows display data (+1) on capacitors C1 to C4.
1 shows a state in which absolute value charges Q1 to Q4 corresponding to -1) are stored. C1 to C4 and CADJ have the same capacity (c
[F]). The polarity of the display data is reflected in the multiplication vector. The CADJ stores a gradation correction calculation result as a charge QADJ. The connection state is changed to the connection state shown in FIG. Although the input terminals of X1 to X4 and ADJ are omitted, they are actually disconnected by analog switches. Vector (Q
1, Q2, Q3, Q4, QADJ) are subjected to the vector operation of the multiplication vector (+1, -1, +1, +1, +1). The connection state is determined by the analog switch according to the multiplication vector. C1, C which is the product of +1
3, C4 and CADJ are commonly connected between VC and OUT in the forward direction, and C2 which is the product of -1 is VC-OUT in the reverse direction.
Are connected in common. The sum of the charges is stored in a capacitor having a capacitance five times that of C1 or the like. The voltage resulting from the vector operation is extracted as an output OUT with respect to the reference potential VC. The voltage of the operation result (Q1-Q2 +
Q3 + Q4 + QADJ) / (5c) is output. One analog vector operation indispensable for simultaneous selection of gradation display
You can do it with a clock. Compared to large power consumption, long operation time, and large-scale circuits, much smaller power consumption, short operation time, and small-scale circuits are required. In addition, high-quality multi-tone display was realized.

[0049]

According to the first aspect of the present invention, the pulse height of the signal electrode is varied in order to give the pixel an effective value corresponding to the gradation display data by using the one-line selection driving method in the simple matrix panel. The amount of voltage correction required when the grayscale display data is an intermediate value (a state that is neither ON nor OFF) uses the voltage-current characteristics of the MOS transistor. Therefore, the analog operation is completed up to the charging of the entire circuit in which the current source is stabilized. Compared to large power consumption, long operation time, and large-scale circuits when operating on digital data
It requires much lower power consumption, shorter operation time, and smaller circuits. In addition, high-quality multi-tone display was realized.

According to the second aspect of the present invention, the pulse height of the signal electrode is varied in order to give an effective value corresponding to the gradation display data to the pixel by using a plurality of simultaneous selection driving method in the simple matrix panel. The voltage-current characteristic of the MOS transistor is used for the gradation correction amount of the voltage required when the gradation display data is an intermediate value (a state that is neither ON nor OFF). Therefore, the analog operation is completed up to the charging of the entire circuit in which the current source is stabilized. Compared to a large power consumption, a long operation time, and a large-scale circuit when performing an operation using digital data, much smaller power consumption, a short operation time, and a small-scale circuit are required.
In addition, a high-quality multi-gradation display can be realized even in the multiple simultaneous selection driving method.

According to the third aspect of the present invention, the method utilizes the fact that the vector operation when the simple matrix panel is driven by the plural simultaneous selection driving method is performed by the vector operation of the analog charge amount held in the capacitor. Therefore, compared to a large-scale circuit with a large power consumption and a long calculation time when a calculation is performed using digital data, much smaller power consumption, a short calculation time, and a small-scale circuit are required. In addition, high-quality multi-tone display was realized.

According to the fourth aspect of the present invention, the vector operation is performed by the vector operation of the analog charge amount held in the capacitor. Therefore, compared to large power consumption, long operation time, and large-scale circuits when performing calculations using digital data,
It requires much lower power consumption, shorter operation time, and smaller circuits. In addition, high-quality multi-tone display was realized.

According to the fifth aspect of the present invention, the vector operation of the amount of analog charge held in the capacitor is performed by performing the vector operation while maintaining the potential difference of each capacitor using the potential difference of each capacitor as display data. Therefore, when calculating with digital data, large power consumption, long calculation time,
Compared to large-scale circuits, much lower power consumption, shorter operation time, and smaller circuits are required. In addition, high-quality multi-tone display was realized.

According to the sixth aspect of the present invention, the vector operation of the amount of analog charge held in the capacitor is performed by using the charge of each capacitor as display data and using the total potential of the vector operation of the charge of each capacitor as the calculation result. used. Therefore, compared to large power consumption, long operation time, and a large-scale circuit in the case of operation using digital data, much smaller power consumption, short operation time, and a small-scale circuit are required. In addition, high-quality multi-tone display was realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first part of a gradation correction operation according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of a one-line selection gradation correction operation according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a main part of a multiple line selection gradation correction operation according to one embodiment of the present invention.

FIG. 4 is a circuit diagram showing a state before a vector operation according to an embodiment of the present invention;

FIG. 5 is a circuit diagram showing a state after calculation of a potential difference holding vector calculation according to one embodiment of the present invention.

FIG. 6 is a circuit diagram showing a state after calculation of a charge holding vector calculation according to one embodiment of the present invention.

FIG. 7 is a circuit diagram showing a minimum unit of the vector operation circuit according to one embodiment of the present invention.

[Explanation of symbols]

 vdd. Positive power supply vss. Negative power supply PLOAD. MOS transistor NREF0. MOS transistor GRAY0. Threshold voltage I1. Display data OP1. Operational amplifier COMPA. Comparator SWLV. Analog switch X1 to X4. Absolute value display data POL. Polarity signal REF. Unit voltage PREF1. MOS transistor NREF1. MOS transistor INREF1. Drain current PX1-4. MOS transistors NX1-4. MOS transistor INX1. Drain current NADJ. MOS transistor INADJ. Drain current ADJ. Gradation correction voltages C1 to C4. Display data capacitors Q1 to Q4. Charge CADJ. Correction voltage capacitor QADJ. Correction charge VC. Center voltage OUT. Vector operation output CALC. Vector operation clock INP. Input gate signal CONT. Polarity control signal

Continuation of the front page F term (reference) 2H093 NA07 NA43 NA53 NC13 NC21 ND06 ND39 ND49 ND60 5C006 AA16 AC23 AF42 AF46 BB12 BC03 BC12 BF14 BF24 BF25 BF28 BF34 BF37 FA23 FA36 FA41 FA47 FA56 5C080 AA29 BB05 DD26 DD10

Claims (6)

[Claims] A simple matrix panel uses a one-line selection driving method, and varies a pulse height of a signal electrode to give an effective value corresponding to gradation display data to a pixel. A liquid crystal display device characterized in that a gradation correction operation required in the case of neither ON nor OFF is obtained by an analog operation circuit utilizing a voltage-current characteristic of a MOS transistor. 2. A liquid crystal display device according to claim 1, wherein the method of driving the liquid crystal display device is a method of simultaneously selecting and driving a plurality of liquid crystal display devices. 3. A liquid crystal display device wherein a vector operation when driving a plurality of simple matrix panels by a simultaneous selection driving method is performed by a vector operation of an analog charge amount held in a capacitor. 4. A liquid crystal display device according to claim 2, wherein the vector operation used in the driving method of the liquid crystal display device according to claim 2 is performed by a vector operation of an analog charge amount held in a capacitor. 5. A vector operation of an analog charge amount held in a capacitor according to claim 3 or 4, wherein a vector operation is performed while maintaining a potential difference of each capacitor by using a potential difference of each capacitor as display data. Liquid crystal display. 6. A vector operation of the amount of analog electric charge held in the capacitor according to claim 3 or 4, wherein the electric charge of each capacitor is used as display data, and a total potential of the vector operation of electric charge of each capacitor is used as an operation result. A liquid crystal display device characterized by the above-mentioned.