JP2000276403A - Cache memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the cache hit rate by preventing cache data of one right of memory ownership from being invalidated by another right of memory ownership. SOLUTION: Addresses of a user management area 3 in a main memory 1 are defined as one memory ownership area by an address definition register 6, and an OS is managed by a virtual address definition register 7. Consequently, when an application program is executed to access a memory, address comparison is performed in an address tag area 10 which manages only its area, and a cache block area 11 for user management area is accessed in the case of hit. When the OS executes its own program by a system call from the application program to access the memory, address comparison is performed only in an address tag area 12 for OS management, and a cache block area 13 for OS management is accessed in the case of hit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly, to preventing cache data of one memory ownership from being invalidated by another memory ownership.
The present invention relates to a main memory system for improving a cache hit rate.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional cache memory system including a main memory 22, a tag memory 25, and a cache memory 26. As shown in FIG. 4, when the application program is executed on the OS, the decoding circuit 28 divides and decodes the block number into the OS management area 23 and the user management area 24 in the main memory 22. The cache memory 26 is not decoded for the ownership of the memory, that is, for each of the OS management area 23 and the user management area 24.

[0003]

Therefore, when an application program in, for example, the user's management area 24 is executed and occupies the cache memory 26 in a certain area or time, a system call is made from the application program to the OS at the same time. The OS program is executed. At this time, the application program and the OS program compete in the cache memory 26, and the OS program copied to the cache memory 26 later overwrites and invalidates the application program copied in the cache memory 26 first. That is, there is a problem that the cache data is updated between the OS and the application program, thereby invalidating the cache data. The same applies to a plurality of OSs and a plurality of application programs.

A large tag memory area and a large cache memory area can be provided. However, when a task is executed, if an area for executing an instruction becomes large, an OS, an application program, or a device such as a device is consequently lost. The media having the memory ownership mutually access the cache memory 26 and invalidate each other's data. It also contributes to an increase in the cost of the system.

In Japanese Patent Laid-Open Publication No. Hei 8-263377 ("cache memory management system"), a main memory space is divided into an OS management area, a user management area, and the like, and a cache block area is provided in each area. However, these areas cannot be further divided to operate a plurality of OS management areas, a plurality of user application programs, and the like.

Therefore, for example, when a plurality of user application programs are executed, a data conflict also occurs in the cache block corresponding to the user management area, and one data invalidates the other data. I will. As a result, there is an obstacle that the performance of the system cannot be improved.

Accordingly, an object of the present invention is to prevent cache data of a certain memory ownership from being invalidated by another memory ownership and to improve a cache hit rate.

[0008]

According to the present invention, there is provided a main memory, an address tag area,
A cache memory system including a cache block area, a decoding circuit for accessing the cache block area, and an address definition register and a virtual address register for defining an address to be accessed, wherein the address definition register is provided for each ownership and / or device. An address is assigned to the address tag area and the cache block area. When a tag of an address to be accessed is hit in the address tag area, the cache block area specified by the tag is accessed, and when no hit is made, the main memory is accessed. I do.

That is, in the present invention, the user divides the main memory area for each purpose of use, and automatically divides the tag memory area and the cache block area managed in the tag memory area accordingly. . Furthermore,
For each area of main memory ownership, the tag memory area and the cache memory area are subdivided without limitation.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a cache memory system according to the present invention. As shown in FIG. 1, the cache memory system of the present invention includes a main memory 1, an address tag area 4, a cache block area 5, an address definition register 6, a virtual address definition register 7,
A boot ROM 8 and a decoding circuit 9 are included.

In the cache memory system of the present invention, the boot ROM 8 sets the address definition register 6 at the time of system initialization. The address definition register 6 can be set at any time. This set value is also reflected in the virtual address definition register 7 and is also referred to at the time of OS management.

The main memory 1, the address tag area 4 and the cache block area 5 have an address definition register 6
And the decoding circuit 9 accesses the target area. Data consistency is maintained between the cache block 11 and the user management area 3.

The same applies to other areas of the main memory such as the OS management area 2.

As described above, the address tag area 4 and the cache block area 5 exist for each memory ownership.
That is, the memory is owned by an area delimited by the address definition register 6. Therefore, by preventing cache invalidation due to access from another ownership, the overall system speed can be increased without lowering the cache hit rate.

Further, the decode circuit 9 divides the main memory 1 into the OS management area 2 and the user management area 3 by setting the address definition register 6, and also refers to the respective areas, and manages the address tag area 4 and the cache block. The area 5 is also divided for each ownership.

The scanning of the designated address is executed only in the corresponding address tag area 10. The scanning address area includes an area managed by the OS, an area scanned by a device driver, and the like. Absent.

If the address tag area 10 contains a tag of the address to be accessed, the data specified by the tag is stored in the cache block area 11 managed by the address tag area 10; The user accesses this address.

If the tag of the address to be accessed is not included, it is a cache miss and the user management area 3 in the main memory 1 is accessed. Data unification is performed between the user management area 3 and the cache block area 11. Will be

The access to the memory area 2 managed by the OS, the memory area managed by the device driver, and the like is the same, and is determined by each tag area. If there is a hit, each cache area is accessed.

According to this setting, the decoding circuit 9 decodes the main memory 1, the address tag area 4, and the cache block area 5, respectively.

Referring to the address definition register 6, the virtual address definition register 7 is set, thereby managing the OS.

The decoding circuit 9 causes the main memory 1
Are decoded for each ownership, of which 2 is an OS management area and 3 is a user management area.

The address tag area which manages each address such as the OS management area 2 and the user management area 3 is 4 and each cache block area is 5.

FIG. 2 is a block diagram of a specific example of the decoder circuit 9. The logical sum A of the decode signal of the address tag section and the decode signal of the address index section lower than the address tag section is used as a chip select (CS4) signal for accessing each block of the address tag area 4.
The logical sum of the latch output of the address hit (HIT) signal and the logical sum A is used as the chip select (CS5) of the cache block area 5.

Here, for example, it is assumed that the user executes an application program and accesses the user management area 3 in the main memory 1.

The address of the user management area 3 is defined as one memory ownership area by the address definition register 6 at the time of system initialization. The OS is managed by the virtual address definition register 7.

Therefore, when the application program is executed to access the memory, the address is compared in the address tag area 10 for managing only that area, and if a cache hit occurs, the cache block area 11 for the user management area is accessed.

When the OS executes its own program by a system call from the application program and accesses the memory, the address is similarly compared only in the OS management address tag area 12, and if a cache hit occurs, the OS management cache block is used. Access the area 13.

Therefore, the cache block areas of each other are not invalidated.

FIG. 3 is a block diagram of a cache memory system according to another embodiment of the present invention. This system includes an OS management area 15, a user management area 16, and an address tag area 1 for each area in the main memory 14.
7. Cache block area 18, address definition register 19, virtual address definition register 2 for each area
0, a boot ROM 21, and a decoding circuit 22.

In the user management area 16, the area accessed by the device A on the system is 16A, the device B is
Is 16B. A register that defines an area accessed by device A is an address definition register 19A, and a register that defines an area accessed by device B is an address definition register 19B.

The values of the address definition registers 19, 19A and 19B are initialized by the boot ROM 21, and the main memory 14 is also decoded by the decoding circuit 22 from the values.
The area is divided into a management area 15, a user management area 16, and an area 16A of the area accessed by the device A and an area 16B of the area accessed by the device B among the 16 areas, and each is independently decoded.

The address tag area 17 is accordingly
The address tag 17A manages an area 16A accessed by the device A, and the address tag 17B manages an area 16B accessed by the device B. The cache block area 18 is also accessed by the cache block 18A accessed by the device A and the device B. The data is divided and decoded by the cache block 18B and the like.

In this way, when the device A accesses the memory in the user management area 16, the determination as to whether or not a cache hit has occurred is made by the address tag area 17A according to the address definition register 19A.
If there is a hit, the cache block area 18A is accessed. If there is a mishit here, 16A in the device A area of the main memory 14 is accessed, and data consistency is performed between 16A and 18A. The same applies to the area accessed by device B.

Therefore, cache data is not invalidated between the use areas of the device A and the device B.

The memory area commonly accessed by both the device A and the device B, such as a database, is assumed to be 16AB, and the address management of the area is performed by the address tag 17AB,
Assuming that the cache block is 18 AB, the access to the database is performed by first determining the address by using the address tag 1.
This is performed at 7AB, and if a hit is made, the cache block 18AB is accessed.

If there is a miss hit, the memory area 16AB
And the data consistency is maintained in the cache block 18AB and the memory area 16AB. Thereby, the device A and the device B can always access the latest database.

The devices A and B may be the application programs A and B.

As described above, even within a certain area of the memory ownership, the memory area, the address tag area, and the cache block area are divided to eliminate data conflicts and to access the cache by another ownership. Invalidation can be prevented, and the probability of a miss hit can be reduced.

[0041]

According to the present invention described above, since there is a tag memory area and a cache memory for address management for each ownership of the main memory, the address area managed by each tag memory is different for each memory ownership. Limited,
In the cache memory, cache invalidation such as data overwriting due to access from another ownership can be prevented.

Further, according to the present invention, the address definition registers defining each area can be nested for each area, so that the address definition registers can be used when a plurality of OSs are running or a plurality of application programs are executed. Invalidation of data in the cache block can be eliminated. Therefore, even when a plurality of OSs are operated and a plurality of application programs are executed, the performance of the system can be maintained or improved without lowering the cache hit rate.

[Brief description of the drawings]

FIG. 1 is a block diagram of a cache memory of the present invention.

FIG. 2 is a block diagram illustrating an example of a decoding circuit.

FIG. 3 is a block diagram of another cache memory according to the present invention;

FIG. 4 is a block diagram of a conventional cache memory.

[Explanation of symbols]

 1,14 Main memory 2,15 OS management area 3,16 User management area 4,17 Address tag area 5,18 Cache block area 6,19 Address definition register 7,20 Virtual address definition register 8,21 Boot ROM 9,22 Decoding circuit

Claims (4)

[Claims] 1. A main memory, an address tag area,
A cache memory system including a cache block area, a decoding circuit for accessing the cache block area, and an address definition register and a virtual address register for defining an address to be accessed, wherein the address definition register is provided for each ownership and / or device. An address is assigned to the address tag area and the cache block area. When a tag of an address to be accessed is hit in the address tag area, the cache block area specified by the tag is accessed, and when no hit is made, the main memory is accessed. A cache memory system. 2. The cache memory system according to claim 1, wherein said virtual address definition memory manages an operating system (OS) in a main memory by referring to said address definition register. 3. The cache memory system according to claim 1, further comprising a boot ROM (read only memory) for setting the address definition register when the system is initialized. 4. The cache according to claim 1, wherein a latch output of a hit signal from the address tag area is ORed with a OR of a decode signal of an address tag section and a decode signal of an address index section lower than the address tag section. 2. The cache memory system according to claim 1, wherein the signal is a chip select signal of a block area.