JP2000269800A - Semiconductor output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent occurrence of through-current at an output stage of a semiconductor output circuit and to prevent the increase of time required for data outputting. SOLUTION: This semiconductor output circuit is provided with a P-channel output transistor(TR) 21, an N-channel output TR 22, and an output control circuit 30 that generates a gate control signal of both the output TRs 21, 22 in response to output data PGTn, NGTp to apply conduction control to both the output TRs 21, 22, detects the logic level of the output data TRs PGTn, NGTp and controls either of both the output TRs 21, 22 which cons them to be nonconductive for a prescribed period, when it detects that the output data logic level is converted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to an output circuit that outputs data to the outside of an integrated circuit.
In particular, the present invention relates to a semiconductor output circuit that outputs data by controlling conduction of two transistors having different polarities provided in an output stage of an output circuit.

[0002]

2. Description of the Related Art FIG. 5 shows an output circuit (Off Chip Drive) for outputting data outside a semiconductor integrated circuit.
3 is a circuit diagram illustrating a basic configuration of an output stage of r). The source and drain of the P-channel output transistor 101 are inserted between the power supply voltage supply node and the data output node. An N-channel output transistor 1 is connected between the data output node and the ground voltage supply node.
02 is inserted between the drain and the source. And
The output of the inverter 103 as a pre-driver is supplied to the gate of the P-channel output transistor 101,
The output of the inverter 104 as a pre-driver is supplied to the gate of the N-channel output transistor 102.

In a circuit having such a configuration, when the outputs of the two inverters 103 and 104 are both at "H" level, the output transistor 101 on the P-channel side is in a non-conductive state and the output transistor 102 on the N-channel side is The data output node is turned on, and "0" level data corresponding to the ground voltage is output from the data output node (hereinafter, this is referred to as "0" reading).

On the other hand, when the outputs of the two inverters 103 and 104 are both at "L" level, the output transistor 101 on the P-channel side becomes conductive and the output transistor 102 on the N-channel side becomes non-conductive, and the data output "1" level data corresponding to the power supply voltage is output from the node (hereinafter, this is referred to as "1" reading).

By the way, both output transistors 10
As the elements 1 and 102, those having a relatively large element size are used because it is necessary to sufficiently drive an external load capacitance. Therefore, at the time of reading "0", the output transistor 102 on the N-channel side switches from the non-conductive state to the conductive state, and when a relatively large current flows through this output transistor 102, the level of the ground line supplying the ground voltage is reduced. Rises. That is, power supply noise occurs in the ground wiring. This ground wiring is not limited to the output transistor 102 on the N-channel side.
Since the ground voltage is also supplied to the inverters 3 and 104, the level of the ground voltage supplied to the inverters 103 and 104 also increases.

When the output transistor 101 on the P-channel side is in a non-conductive state, an "L" level signal is input to the inverter 103, and the output of the inverter 103 is at an "H" level. At this time,
When the level of the ground voltage supplied to the inverter 103 increases, the circuit threshold voltage of the inverter 103 increases, and the voltage level of the output signal at the “H” level may decrease.

When the voltage level of the "H" level output from inverter 103 decreases, output transistor 101 on the P-channel side does not completely turn off, and although a little current flows between the source and the drain. Flows.

As a result, a through current flows between the supply node of the power supply voltage and the supply node of the ground voltage. Then N
Since the flow of the current drawn from the data output node via the channel-side output transistor 102 is hindered, the data output at the “0” level is delayed.

On the other hand, in the case of "1" reading, there is no such concern. That is, at the time of reading “1”, the level of the power supply voltage decreases due to the conduction of the output transistor 101 on the P-channel side, and the level of the power supply voltage supplied to the two inverters 103 and 104 decreases accordingly. However, the output of inverter 104 that supplies the "L" level to the gate of output transistor 102 on the N-channel side is not affected by this decrease in the power supply voltage level, and remains at the "L" level. Output transistor 102
Remain non-conductive.

That is, in an output circuit having a CMOS configuration in which an output stage includes P-channel and N-channel transistors, power supply noise has a serious influence on a "0" read operation.

Since a through current is generated by the power supply noise as described above, the output transistors 101, 10
It is necessary to strictly adjust the timing of the gate control signal so that the transistors 2 do not become conductive at the same time.

As described above, since power supply noise at the output stage greatly affects the performance of the integrated circuit, a careful timing design is particularly required when designing the output circuit.

Incidentally, a synchronous DRAM (SDRAM), which is a kind of integrated semiconductor memory, is about 2-3 times faster than a normal DRAM, for example, an EDO (Extended Data Output) type DRAM. To output data. Therefore, in order to realize the high read speed, the output circuit cannot insert a circuit having a complicated configuration in the middle of the path from the input stage to the gate of the final output stage transistor.

Therefore, both output transistors 10
It becomes difficult to finely control the gate control signals in steps 1 and 102, and so-called skew (skew) occurs between the gate control signals.
ew) is more likely to occur.

When such a signal skew occurs, both output transistors 101 and 102 are simultaneously turned on, thereby causing a through current to flow between the power supply and the ground node,
As a result, a large power supply noise may occur, and the output of the “0” level data may be significantly delayed.

Further, when a large through current flows between the power supply and the ground node, hot carriers are generated between the source and the drain of the MOS transistor. Here, when high-energy carriers exceeding the potential barrier are injected into the gate oxide film, the threshold voltage of the MOS transistor changes, and the threshold voltage becomes unstable. It can have a significant effect on growth.

Here, various configurations of the conventional output circuit will be described.

The output circuit shown in FIG. 6 includes a P-channel and N-channel output transistor 10 provided at an output stage.
1 and 102, an inverter 111 as a pre-driver for amplifying output data / RD and RD, respectively.
112, and a clocked inverter 113 for output control to which the output of each of the inverters 111 and 112 is input.
114 and each of the clocked inverters 113 and 114
Are respectively latched and output transistor 101,
Latch circuit 1 composed of two inverters 115 and 116 each outputting to gate 102 as each gate control signal
17 and 118, and an inverter 119 inserted between the one latch circuit 117 and the gate of the P-channel output transistor 101.

In the conventional circuit shown in FIG. 6, when the control signal DXFR supplied to the clocked inverters 113 and 114 becomes "H" level and / DXFR becomes "L" level, both the clocked inverters 113 and 114 operate. Each output of inverters 111 and 112 is clocked inverter 1
The signals are inverted at 13 and 114 and input to the latch circuits 117 and 118. The latch signal of the latch circuit 117 is input to the gate of the output transistor 101 via the inverter 119 as a gate control signal, and the latch signal of the latch circuit 118 is input to the gate of the output transistor 102 on the N-channel side as a gate control signal. As a result, one of the output transistors 101 and 102 becomes conductive and the other becomes non-conductive, and data “1” or “0” level data DQ is output.

The output circuit shown in FIG. 7 is different from the output circuit shown in FIG. 6 in that an output control circuit 120 is provided instead of the inverter 119 provided between one latch circuit 117 and the gate of the output transistor 101 on the P-channel side. 6 is different from that of FIG. 6 in that an output control circuit 130 is provided instead of the other latch circuit 118 in the output circuit of FIG.

The one output control circuit 120 includes one P-channel MOS transistor 121, two N-channel MOS transistors 122 and 123, and one inverter 124. In the output control circuit 120, the source and the drain of the N-channel MOS transistor 123 are inserted in the middle of the N-channel current path of the CMOS inverter composed of the P-channel and N-channel MOS transistors 121 and 122. Inverter 124 having a node connected to the gate of output transistor 102 on the N-channel side
Is gated by the output of

The other output control circuit 130 includes two P-channel MOS transistors 131 and 132, one N-channel MOS transistor 133, and two inverters 134 and 135. In this output control circuit 130, P-channel and N-channel MOS
A P-channel MOS transistor is provided in the middle of the P-channel current path of the CMOS inverter including the transistors 132 and 133.
A portion between the source and the drain of the transistor 131 is inserted,
The transistor 131 has its input node gate-controlled by the output of an inverter 134 connected to the gate of the output transistor 101 on the P-channel side, and has the CMOS
The input / output node of the inverter 135 is connected in anti-parallel to the inverter to form a latch circuit.

In the conventional circuit of FIG. 7, when one output data / RD is at "L" level and the other output data RD is at "H" level, output transistors 101 and 102 on the P-channel and N-channel sides. Are both at "L" level, the P-channel output transistor 101 becomes conductive, and the N-channel output transistor 1
02 is turned off, and "1" level data DQ is output.

In this state, when / RD is inverted to the "H" level and RD is inverted to the "L" level, first, the gate control signal of the output transistor 101 on the P channel side becomes "L".
The level changes from the level to the “H” level, and the control to turn off the P-channel output transistor 101 is started. Then, the output of the inverter 134 is inverted to the “L” level.

On the other hand, after RD changes to "L" level, the output of inverter 112 is sequentially inverted to "H" level and the output of clocked inverter 114 is sequentially inverted to "L" level. P channel MOS transistor 132 is rendered conductive. However, the P channel M
The OS transistor 131 is turned on only after the output of the inverter 134 is inverted to “L” level, and the gate control signal of the N-channel output transistor 102 becomes “H” level after the P-channel MOS transistor 131 is turned on. . Therefore, the N-channel output transistor 102 is connected to the P-channel output transistor 1.
It becomes conductive after 01 becomes non-conductive.

Similarly, contrary to the above, the output transistor 101 on the P channel side becomes conductive after the output transistor 102 on the N channel side becomes non-conductive.

As a result, the output transistors 101 and 102 on the P-channel side and the N-channel side do not have a period in which the output transistors 101 and 102 are simultaneously turned on, thereby preventing the generation of a through current.

The output circuit shown in FIG. 8 has two output circuits each having a source and a drain inserted in series between the input node of each of the latch circuits 117 and 118 and the power supply voltage supply node in the output circuit of FIG. P-channel MOS transistors 141, 142 and 143, 144 are provided, and two inverters 145, 1 connected in series for gate-controlling these four MOS transistors 141-144.
6 is different from that of FIG.

The two inverters 14 connected in series
5 and 146, a control signal / CAS (column address strobe signal) used to capture a data read command is input, and the output is supplied to each gate of the P-channel MOS transistors 141 and 144. . Further, the control signal DXFR is supplied to each gate of the P-channel MOS transistors 142 and 143.

In the conventional circuit of FIG. 8, the control signals DXFR,
/ DXFR clocked inverters 113 and 114
When the control signal / CAS at the "L" level is input during a period other than the data output period when the P-channel MOS transistor 141 is operating, two P-channel MOS transistors 141,
142, 143 and 144 are all conductive, and both latch circuits 1
Input nodes 17 and 118 are precharged to "H" level. As a result of this precharging, the outputs of both the latch circuits 117 and 118 become "L" level, the output of the inverter 119 becomes "H" level, and both the P-channel and N-channel output transistors 101 and 102 become non-conductive. Become.

That is, in the conventional circuit of FIG. 8, the node of data DQ is set to a high impedance state (hereinafter, referred to as HiZ state) every time data is output, thereby preventing generation of a through current.

[0032]

However, the conventional circuits shown in FIGS. 6 to 8 have the following disadvantages.

First, in the conventional circuit shown in FIG. 6, a complicated circuit is inserted in the path between the output data / RD and RD and the gates of the P-channel and N-channel output transistors 101 and 102. However, there is a possibility that skew may occur in the timing of a signal propagated therethrough due to a difference in wiring capacitance between the two paths and the like, whereby the output transistors 101 and 102 may conduct simultaneously, and a through current may occur. .

In the conventional circuit shown in FIG.
There is a problem that it takes a very long time to switch data because one of the devices 01 and 102 becomes nonconductive and the other becomes conductive.

In the conventional circuit shown in FIG. 8, since the data DQ node is always set to a high impedance state before outputting the data and the data is output, it takes a long time to output the data.

As described above, in the conventional output circuit, a countermeasure is not taken (the conventional circuit in FIG. 6), there is a problem that a through current is generated in the output stage. In this case (the conventional circuits shown in FIGS. 7 and 8), it takes a long time to output data.

The present invention has been made in view of the above circumstances, and has as its object to prevent the generation of a through current in the output stage and to prevent the time required for data output from increasing. It is to provide a semiconductor output circuit that can be used.

[0038]

A semiconductor output circuit according to the present invention comprises: a first output transistor having a first polarity, a current path inserted between a first power supply node and an output node; A second output transistor having a second polarity having a current path inserted between the first power supply node and the second power supply node; and the first output transistor according to output data for controlling conduction of the first and second output transistors. And generating a gate control signal for the second output transistor, detecting the logical level of the output data, and detecting that the logical level of the output data has been inverted when the first and second outputs are detected. An output control circuit for controlling one of the transistors to be in a non-conductive state for a predetermined period.

Further, the output control circuit in the semiconductor output circuit according to the present invention comprises: a first latch circuit for latching first output data for controlling conduction of the first output transistor; and the first latch. The output data of the circuit is
A first switch circuit that takes in synchronization with the synchronization signal of
A second latch circuit for latching data captured by the first switch circuit, and a first latch circuit for controlling conduction of the first output transistor based on the data latched by the second latch circuit. A first logic circuit for generating a gate control signal, a third latch circuit for latching second output data for controlling conduction of the second output transistor, and output data of the third latch circuit A second switch circuit that captures data in synchronization with the first synchronization signal, a fourth latch circuit that latches data captured by the second switch circuit,
Based on the data latched by the latch circuit of FIG.
And a second logic circuit for generating a second gate control signal for controlling the conduction of the output transistor, and comparing the latch data of the first and second latch circuits with the first output in different periods. A change in the logic level of the data for use, and the second gate control signal generated by the second logic circuit is supplied to the second output transistor for a predetermined period after the change in the logic level is detected. And a first control circuit for setting the logic level to a non-conducting state, and comparing the latch data of the third and fourth latch circuits with the logic level of the second output data in periods different from each other. , And during a predetermined period after the detection of the change in the logic level, the first output transistor non-conducts the first gate control signal generated by the first logic circuit. Is constituted by a second control circuit that sets the logic level such that state.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to the drawings.

FIG. 1 is a block diagram showing an overall schematic internal configuration of a synchronous DRAM implementing a semiconductor output circuit of the present invention.

In the figure, reference numeral 11 denotes a core circuit including a memory cell array, a sense amplifier, a row decoder and a column decoder, 12 denotes a control signal buffer to which various control signals such as a read / write control signal are input, and 13 denotes an address. An address buffer 14 is a DQ buffer for exchanging input / output data with the outside of the memory.
A control circuit 15 receives the outputs of the control signal buffer 12 and the address buffer 13 and controls the operations of the core circuit 11 and the DQ buffer 14.

In the synchronous DRAM having such a configuration, a control signal is input to the control signal buffer 12 and an address is input to the address buffer 13, so that
A memory cell corresponding to an input address is selected from a memory cell array in the core circuit 11. At the time of data reading, the data read from the selected memory cell is D
The data is output to the outside of the memory via the Q buffer 14, and at the time of data write, the write data input to the DQ buffer 14 is written to the selected memory cell.

Incidentally, the synchronous DRA shown in FIG.
M performs the burst read operation as described above, and the mode in which the output data DQ changes during the burst read operation can be classified into the following four types as shown in FIG.

First, as shown in FIG. 2A, the first mode is a case where DQ outputs "0" or "1" level data from a high impedance state (referred to as HiZ). . This state occurs at the start of the burst read operation. Note that “current Data” in FIG. 2 is the state of the data before the change, and “Next Data” is the state of the data after the change.

In the second embodiment, as shown in FIG.
This is the case where DQ changes from “0” or “1” level to HiZ. This state occurs at the end of the burst read operation.

In the third embodiment, as shown in FIG.
This is the case where DQ does not change from the “0” or “1” level. This state occurs during the burst read operation.

In the fourth embodiment, as shown in FIG.
This is the case where DQ changes from the “0” or “1” level to the opposite level. This state occurs during the burst read operation.

In the first to third embodiments, there is no possibility that a through current will flow between the supply node of the power supply voltage and the supply node of the ground voltage at the output stage of the DQ buffer 14. The problem is the above-described fourth embodiment. If the timing margin for inverting the data is not enough, the P-channel provided in the output stage of the DQ buffer 14 may be slightly skewed due to signal skew. In addition, there is a possibility that the N-channel output transistor and the N-channel output transistor both become conductive and a through current flows.

FIG. 3 shows a detailed circuit configuration of only a data output circuit (corresponding to the semiconductor output circuit of the present invention) for outputting data to the outside of the DRAM in the DQ buffer 14 in FIG. As described above, when DQ changes from "0" or "1" level to the opposite level during the burst read operation, both the P-channel and N-channel output transistors provided in the output stage conduct and pass through. Measures are taken to prevent the current from flowing.

This data output circuit has a P-channel output transistor 2 having a source and a drain inserted between a power supply voltage supply node and an output node (DQ node).
1, an N-channel output transistor 22 having a source and a drain inserted between the output node and the ground voltage supply node, and output data PGTn and NGTn for controlling conduction of these output transistors 21 and 22. Correspondingly, P-channel and N-channel output transistors 21,
22 and a logic level of the output data PGTn and NGTp is detected. When it is detected that the logic level of the output data is inverted, one of the output transistors 21 and 22 is turned off. And an output control circuit 30 for controlling the non-conduction state for a predetermined period.

The output control circuit 30 includes two inverters 3 for latching first output data PGTn for controlling conduction of the output transistor 21 on the P-channel side.
1 and 32, a clock signal CL is applied to a clock gate on the P channel side, and an inverted signal / CL of the clock signal CL is applied to a clock gate on the N channel side.
And a clocked inverter 34 as a first switch circuit for inverting and outputting the output data a of the latch circuit 33 in synchronization with the clock signals CL and / CL.
And a latch circuit 37 composed of two inverters 35 and 36 for latching the output b of the clocked inverter 34, and a series-connected 2 to which the output of the latch circuit 37 (the output of the inverter 35) is input. Inverters 3
8, 39 and the output c of the inverter 39 are input to one input terminal, and generate a gate control signal for controlling conduction of the P-channel output transistor 21 based on the data latched by the latch circuit 37. A NAND circuit 40 as a logic circuit to perform the operation, a latch circuit 43 composed of two inverters 41 and 42 for latching the second output data NGTp for controlling the conduction of the output transistor 22 on the N-channel side; The clock signal CL is input to the clock gate on the channel side, and the inverted signal / CL is input to the clock gate on the N channel side, and the output data f of the latch circuit 43 is converted to the clock signals CL and / C.
A clocked inverter 44 as a second switch circuit that inverts and outputs the signal in synchronization with L, and two inverters 45 and 4 that latch the output g of the clocked inverter 44
6 and the latch circuit 47
The output h of the inverter 49 and two inverters 48 and 49 connected in series to which the output of (the output of the inverter 45) is input are input to one input terminal. A NOR circuit 50 is provided as a logic circuit for generating a gate control signal for controlling the conduction of the output transistor 22 on the N-channel side based on the signal.

Further, the output control circuit 30 compares the latch data of the two latch circuits 33 and 37 and outputs the first output data PGTn in different periods.
And a control circuit 60 for setting the gate control signal generated by the NOR circuit 50 to the "0" level for a predetermined period after the detection of the change in the logic level. The latch data of the latch circuits 43 and 47 are compared to detect a change in the logic level of the second output data NGTp in different periods, and the NANp is detected in a predetermined period after the change in the logic level is detected.
And a control circuit 70 for setting the gate control signal generated by the D circuit 40 to the “1” level.

The one control circuit 60 includes a NAND circuit 61 to which the latch data a and b (b is the output of the inverter 36) of the latch circuits 33 and 37 is input, and an N
The two inverters 62 and 63 connected in series to which the output of the AND circuit 61 is input, the clock signal CLD is input to the P-channel clock gate, and the inverted signal / CLD is input to the N-channel clock gate. , The output d of the inverter 63 to the clock signals CLD, / C
Clocked inverter 64 that inverts and outputs in synchronization with LD
And an N-channel MOS transistor 65 having a source and a drain inserted between the output node of the clocked inverter 64 and the ground voltage supply node and having the gate to receive the clock signal CLD,
The signal e at the output node of clocked inverter 64 is input to the other input terminal of NOR circuit 50 described above.

The other control circuit 70 includes a NOR circuit 71 to which the latch data f and g (g is an output of the inverter 46) of the latch circuits 43 and 47 are input,
The two inverters 72 and 73 connected in series to which the output of the R circuit 71 is input, the clock signal CLD is input to the P-channel clock gate, and the inverted signal / CLD is input to the N-channel clock gate. , The output i of the inverter 73 is connected to the clock signals CLD and / CLD.
A clocked inverter 74 that inverts and outputs in synchronization with
A clocked inverter 74 comprises a P-channel MOS transistor 75 having a source and a drain inserted between its output node and a power supply voltage supply node and having the gate to which the clock signal / CLD is inputted, and The signal j at the output node of the inverter 74 is N
The signal is input to the other input terminal of the AND circuit 40.

The clock signals CLD, / CLD
Is a signal whose phase is slightly delayed with respect to the clock signals CL and / CL.

Next, the operation of the data output circuit configured as shown in FIG. 3 will be described with reference to the timing chart of FIG.

First, the case where output data DQ changes from "0" level to "1" level will be described. When the output data DQ is in a state before changing to the “1” level, the latch data of the latch circuits 37 and 47 (the inverters 35 and 47)
45 output) are both at the “0” level. Therefore, the output of the inverter 39 is precharged to the "0" level, the output node of the clocked inverter 74 is precharged to the "1" level by the P-channel MOS transistor 75 conducting, and the signal j is at the "1" level. Therefore, the output of the NAND circuit 40 becomes “1” level,
The output transistor 21 on the P channel side is off.

The output of inverter 49 is "0" level, the output node of clocked inverter 64 is previously discharged to "0" level by N-channel MOS transistor 65 conducting, and signal e is "0". Therefore, the output of the NOR circuit 50 becomes "1" level, and the output transistor 22 on the N-channel side is in a conductive state.

In this state, when the first output data PGTn and the second output data PGTn both having the “0” level are input, the respective data are latched by the latch circuits 33 and 4.
Latched at 3. Accordingly, the latch data a and f of the latch circuits 33 and 43 are both at the “1” level. Then
The output of the NAND circuit 61 in the control circuit 60 to which the data a and b are input is at 0 ″ level, and the output of the inverter 63 is at 0 ″.
Level, and as a result, the clock signal CLD becomes “0”.
After the transition to the level (/ CLD is the “1” level), the signal e is inverted to the “1” level. When the signal e becomes "1" level, the output of the NOR circuit 50 is inverted to "0" level, and the N-channel output transistor 22 immediately becomes non-conductive irrespective of the signal h.

On the other hand, when the clock signal CL transitions to the “0” level, the clocked inverter 34 operates, and the latch data “a” of the latch circuit 33 is sent to the latch circuit 37, where it is latched. That is, the data b is inverted to the "0" level, the output of the inverter 35 of the latch circuit 37 is inverted to the "1" level later than this, and the output c of the inverter 39 is further shifted to the "1" level later than this. Invert. At this time, since the signal j is precharged to the “1” level by the P-channel MOS transistor 75 in the control circuit 70, the signal N is inverted after the output c of the inverter 39 is inverted to the “1” level.
The output of the D circuit 40 is inverted to the “0” level, the output transistor 21 on the P-channel side is turned on, and the DQ is set to “1”.
Level data is output. At this time, during the period when the signal e in FIG. 4 is at the “1” level, the output transistor 22 on the N-channel side is in a non-conductive state, so that the output transistor 21 on the P-channel side and the N-channel side, 22 both conduct, and no through current flows between the supply node of the power supply voltage and the supply node of the ground voltage.

During the period when the N-channel output transistor 22 is in a non-conductive state, the clock signal C
The clocked inverter 34 operates in synchronization with L, and the two latch circuits 33 and 37 latch data corresponding to the output data PGTn of the same logical level, and the control circuit 60
The output of the NAND circuit 61 is inverted to "1" level,
After this, the output d of the inverter 63 is inverted to the “1” level, and after the output d of the clocked inverter 65 is inverted to the “0” level, it is released. Here, a period tHiZ (N) in FIG. 4 is a period in which both the P-channel side and the N-channel side output transistors 21 and 22 are non-conductive.

As described above, the first output data PGTn
The control circuit 60 detects that the logic level has changed from the "1" level to the "0" level. When this is detected, the output of the NOR circuit 50 is turned off and the output transistor 22 on the N-channel side is turned off. Therefore, the output transistor 21 on the P-channel side is turned on to prevent a through current from flowing when outputting data of “1” level. it can.

The output data DQ changes from "1" level to "0".
When the level changes to the level, the control circuit 70
As a result, it is detected that the logic level of the second output data NGTp has changed from “0” level to “1” level, and when this is detected, the output of the NAND circuit 60 is changed to
The P-channel output transistor 21 is set to the “1” level for a predetermined period so as to be in a non-conductive state. When the N-channel output transistor 22 is turned on to output “0” level data, a through current is set. Can be prevented from flowing.

The period tHiZ (P) in FIG.
The output transistor 21 on the channel side is a NAND circuit 40
Is a non-conducting state by the output of the P-side and the output transistors 21 and 22 on the P-channel side and the N-channel side are both in a non-conducting state.

Moreover, unlike the conventional circuit shown in FIG. 7, the control is not such that one of the P-channel and N-channel output transistors becomes non-conductive and then the other becomes conductive. The problem that it takes a very long time to switch data can also be solved.

Further, unlike the conventional circuit shown in FIG. 8, it is not necessary to set the output to a high impedance state before outputting the data, so that the problem that the data output takes a long time is solved. be able to.

[0068]

As described above, according to the present invention, it is possible to provide a semiconductor output circuit which can prevent a through current from occurring in an output stage and can prevent an increase in time for outputting data. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall schematic internal configuration of a synchronous DRAM implementing a semiconductor output circuit of the present invention.

FIG. 2 is a diagram showing a form in which output data DQ changes during a burst read operation of the synchronous DRAM of FIG. 1;

FIG. 3 is a diagram showing a detailed circuit configuration of only a data output circuit in a DQ buffer 14 in FIG. 1;

FIG. 4 is a timing chart showing the operation of the data output circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a basic configuration of an output stage of the output circuit.

FIG. 6 is a circuit diagram of a conventional output circuit.

FIG. 7 is a circuit diagram of a conventional output circuit.

FIG. 8 is a circuit diagram of a conventional output circuit.

[Explanation of symbols]

 11: Core circuit, 12: Control signal buffer, 13: Address buffer, 14: DQ buffer, 15: Control circuit, 21: P-channel output transistor, 22: N-channel output transistor, 30: Output control circuit, 33 ... Latch circuit, 34 clocked inverter, 37 latch circuit, 40 NAND circuit, 43 latch circuit, 44 clocked inverter, 47 latch circuit, 50 NAND circuit, 60 control circuit, 61 NAND circuit, 62, 63: Inverter, 64: Clocked inverter, 65: N-channel MOS transistor, 70: Control circuit, 71: NOR circuit, 72, 73: Inverter, 74: Clocked inverter, 75: P-channel MOS transistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J055 AX02 AX27 AX54 AX66 BX16 CX27 DX22 DX56 DX72 DX83 EX07 EX21 EY21 EZ07 EZ25 EZ29 FX12 FX17 FX35 GX00 GX01 5J056 AA04 AA39 BB02 BB19 CC00 CC04 DD13 DD07HFFH

Claims (2)

[Claims] A first output transistor having a first polarity having a current path inserted between the first power supply node and the output node; and a current path formed between the output node and the second power supply node. Generating a gate control signal for the first and second output transistors in accordance with the inserted second output transistor of the second polarity and output data for controlling conduction of the first and second output transistors; Detecting the logic level of the output data and detecting that the logic level of the output data has been inverted, causing one of the first and second output transistors to be in a non-conductive state for a predetermined period of time. A semiconductor output circuit comprising: an output control circuit that performs control for causing the semiconductor output circuit to perform the control. A first output transistor for controlling conduction of the first output transistor;
A first latch circuit that latches the output data of the first latch circuit, a first switch circuit that captures the output data of the first latch circuit in synchronization with a first synchronization signal, and a latch circuit that captures the output data of the first latch circuit. A second latch circuit for latching the read data, and a first latch circuit for controlling conduction of the first output transistor based on the data latched by the second latch circuit.
A first logic circuit for generating a gate control signal for the second output transistor; and a second logic circuit for controlling conduction of the second output transistor.
A third latch circuit that latches the output data of the second latch circuit, a second switch circuit that captures the output data of the third latch circuit in synchronization with the first synchronization signal, and a latch circuit that captures the output data of the third latch circuit. A fourth latch circuit for latching the latched data, and a second latch circuit for controlling conduction of the second output transistor based on the data latched by the fourth latch circuit.
Comparing the latch data of the first and second latch circuits to detect a change in the logic level of the first output data during periods different from each other; During a predetermined period after the change in the logic level is detected, the second gate control signal generated by the second logic circuit is changed to a logic level at which the second output transistor is turned off. Comparing the latch data of the first control circuit to be set with the latch data of the third and fourth latch circuits to detect a change in the logic level of the second output data during periods different from each other; The first gate control signal generated by the first logic circuit is set to a logic level that renders the first output transistor non-conductive for a predetermined period after the detection of the first gate. The semiconductor output circuit according to claim 1, characterized in that it is constituted and a control circuit.